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[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / ddr.c
1 /*
2 * Copyright (C) 2014 Gateworks Corporation
3 * Author: Tim Harvey <tharvey@gateworks.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <linux/types.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/mx6-ddr.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/io.h>
14 #include <asm/types.h>
15 #include <wait_bit.h>
16
17 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
18
19 static void reset_read_data_fifos(void)
20 {
21 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
22
23 /* Reset data FIFOs twice. */
24 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
25 wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
26
27 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
28 wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
29 }
30
31 static void precharge_all(const bool cs0_enable, const bool cs1_enable)
32 {
33 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
34
35 /*
36 * Issue the Precharge-All command to the DDR device for both
37 * chip selects. Note, CON_REQ bit should also remain set. If
38 * only using one chip select, then precharge only the desired
39 * chip select.
40 */
41 if (cs0_enable) { /* CS0 */
42 writel(0x04008050, &mmdc0->mdscr);
43 wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
44 }
45
46 if (cs1_enable) { /* CS1 */
47 writel(0x04008058, &mmdc0->mdscr);
48 wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
49 }
50 }
51
52 static void force_delay_measurement(int bus_size)
53 {
54 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
55 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
56
57 writel(0x800, &mmdc0->mpmur0);
58 if (bus_size == 0x2)
59 writel(0x800, &mmdc1->mpmur0);
60 }
61
62 static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
63 {
64 u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
65
66 /*
67 * DQS gating absolute offset should be modified from reflecting
68 * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
69 */
70
71 val_ctrl = readl(reg_ctrl);
72 val_ctrl &= 0xf0000000;
73
74 dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
75 dg_dl_abs_offset = dg_tmp_val & 0x7f;
76 dg_hc_del = (dg_tmp_val & 0x780) << 1;
77
78 val_ctrl |= dg_dl_abs_offset + dg_hc_del;
79
80 dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
81 dg_dl_abs_offset = dg_tmp_val & 0x7f;
82 dg_hc_del = (dg_tmp_val & 0x780) << 1;
83
84 val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
85
86 writel(val_ctrl, reg_ctrl);
87 }
88
89 int mmdc_do_write_level_calibration(void)
90 {
91 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
92 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
93 u32 esdmisc_val, zq_val;
94 u32 errors = 0;
95 u32 ldectrl[4];
96 u32 ddr_mr1 = 0x4;
97
98 /*
99 * Stash old values in case calibration fails,
100 * we need to restore them
101 */
102 ldectrl[0] = readl(&mmdc0->mpwldectrl0);
103 ldectrl[1] = readl(&mmdc0->mpwldectrl1);
104 ldectrl[2] = readl(&mmdc1->mpwldectrl0);
105 ldectrl[3] = readl(&mmdc1->mpwldectrl1);
106
107 /* disable DDR logic power down timer */
108 clrbits_le32(&mmdc0->mdpdc, 0xff00);
109
110 /* disable Adopt power down timer */
111 setbits_le32(&mmdc0->mapsr, 0x1);
112
113 debug("Starting write leveling calibration.\n");
114
115 /*
116 * 2. disable auto refresh and ZQ calibration
117 * before proceeding with Write Leveling calibration
118 */
119 esdmisc_val = readl(&mmdc0->mdref);
120 writel(0x0000C000, &mmdc0->mdref);
121 zq_val = readl(&mmdc0->mpzqhwctrl);
122 writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
123
124 /* 3. increase walat and ralat to maximum */
125 setbits_le32(&mmdc0->mdmisc,
126 (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
127 setbits_le32(&mmdc1->mdmisc,
128 (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
129 /*
130 * 4 & 5. Configure the external DDR device to enter write-leveling
131 * mode through Load Mode Register command.
132 * Register setting:
133 * Bits[31:16] MR1 value (0x0080 write leveling enable)
134 * Bit[9] set WL_EN to enable MMDC DQS output
135 * Bits[6:4] set CMD bits for Load Mode Register programming
136 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
137 */
138 writel(0x00808231, &mmdc0->mdscr);
139
140 /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
141 writel(0x00000001, &mmdc0->mpwlgcr);
142
143 /*
144 * 7. Upon completion of this process the MMDC de-asserts
145 * the MPWLGCR[HW_WL_EN]
146 */
147 wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
148
149 /*
150 * 8. check for any errors: check both PHYs for x64 configuration,
151 * if x32, check only PHY0
152 */
153 if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
154 errors |= 1;
155 if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
156 errors |= 2;
157
158 debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
159
160 /* check to see if cal failed */
161 if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
162 (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
163 (readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
164 (readl(&mmdc1->mpwldectrl1) == 0x001F001F)) {
165 debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
166 writel(ldectrl[0], &mmdc0->mpwldectrl0);
167 writel(ldectrl[1], &mmdc0->mpwldectrl1);
168 writel(ldectrl[2], &mmdc1->mpwldectrl0);
169 writel(ldectrl[3], &mmdc1->mpwldectrl1);
170 errors |= 4;
171 }
172
173 /*
174 * User should issue MRS command to exit write leveling mode
175 * through Load Mode Register command
176 * Register setting:
177 * Bits[31:16] MR1 value "ddr_mr1" value from initialization
178 * Bit[9] clear WL_EN to disable MMDC DQS output
179 * Bits[6:4] set CMD bits for Load Mode Register programming
180 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
181 */
182 writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
183
184 /* re-enable auto refresh and zq cal */
185 writel(esdmisc_val, &mmdc0->mdref);
186 writel(zq_val, &mmdc0->mpzqhwctrl);
187
188 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
189 readl(&mmdc0->mpwldectrl0));
190 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
191 readl(&mmdc0->mpwldectrl1));
192 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
193 readl(&mmdc1->mpwldectrl0));
194 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
195 readl(&mmdc1->mpwldectrl1));
196
197 /* We must force a readback of these values, to get them to stick */
198 readl(&mmdc0->mpwldectrl0);
199 readl(&mmdc0->mpwldectrl1);
200 readl(&mmdc1->mpwldectrl0);
201 readl(&mmdc1->mpwldectrl1);
202
203 /* enable DDR logic power down timer: */
204 setbits_le32(&mmdc0->mdpdc, 0x00005500);
205
206 /* Enable Adopt power down timer: */
207 clrbits_le32(&mmdc0->mapsr, 0x1);
208
209 /* Clear CON_REQ */
210 writel(0, &mmdc0->mdscr);
211
212 return errors;
213 }
214
215 int mmdc_do_dqs_calibration(void)
216 {
217 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
218 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
219 struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux =
220 (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
221 bool cs0_enable;
222 bool cs1_enable;
223 bool cs0_enable_initial;
224 bool cs1_enable_initial;
225 u32 esdmisc_val;
226 u32 bus_size;
227 u32 temp_ref;
228 u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
229 u32 errors = 0;
230 u32 initdelay = 0x40404040;
231
232 /* check to see which chip selects are enabled */
233 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
234 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
235
236 /* disable DDR logic power down timer: */
237 clrbits_le32(&mmdc0->mdpdc, 0xff00);
238
239 /* disable Adopt power down timer: */
240 setbits_le32(&mmdc0->mapsr, 0x1);
241
242 /* set DQS pull ups */
243 setbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000);
244 setbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000);
245 setbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000);
246 setbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000);
247 setbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000);
248 setbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000);
249 setbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000);
250 setbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000);
251
252 /* Save old RALAT and WALAT values */
253 esdmisc_val = readl(&mmdc0->mdmisc);
254
255 setbits_le32(&mmdc0->mdmisc,
256 (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
257
258 /* Disable auto refresh before proceeding with calibration */
259 temp_ref = readl(&mmdc0->mdref);
260 writel(0x0000c000, &mmdc0->mdref);
261
262 /*
263 * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
264 * this also sets the CON_REQ bit.
265 */
266 if (cs0_enable_initial)
267 writel(0x00008020, &mmdc0->mdscr);
268 if (cs1_enable_initial)
269 writel(0x00008028, &mmdc0->mdscr);
270
271 /* poll to make sure the con_ack bit was asserted */
272 wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
273
274 /*
275 * Check MDMISC register CALIB_PER_CS to see which CS calibration
276 * is targeted to (under normal cases, it should be cleared
277 * as this is the default value, indicating calibration is directed
278 * to CS0).
279 * Disable the other chip select not being target for calibration
280 * to avoid any potential issues. This will get re-enabled at end
281 * of calibration.
282 */
283 if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
284 clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
285 else
286 clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
287
288 /*
289 * Check to see which chip selects are now enabled for
290 * the remainder of the calibration.
291 */
292 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
293 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
294
295 /* Check to see what the data bus size is */
296 bus_size = (readl(&mmdc0->mdctl) & 0x30000) >> 16;
297 debug("Data bus size: %d (%d bits)\n", bus_size, 1 << (bus_size + 4));
298
299 precharge_all(cs0_enable, cs1_enable);
300
301 /* Write the pre-defined value into MPPDCMPR1 */
302 writel(pddword, &mmdc0->mppdcmpr1);
303
304 /*
305 * Issue a write access to the external DDR device by setting
306 * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
307 * this bit until it clears to indicate completion of the write access.
308 */
309 setbits_le32(&mmdc0->mpswdar0, 1);
310 wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
311
312 /* Set the RD_DL_ABS# bits to their default values
313 * (will be calibrated later in the read delay-line calibration).
314 * Both PHYs for x64 configuration, if x32, do only PHY0.
315 */
316 writel(initdelay, &mmdc0->mprddlctl);
317 if (bus_size == 0x2)
318 writel(initdelay, &mmdc1->mprddlctl);
319
320 /* Force a measurment, for previous delay setup to take effect. */
321 force_delay_measurement(bus_size);
322
323 /*
324 * ***************************
325 * Read DQS Gating calibration
326 * ***************************
327 */
328 debug("Starting Read DQS Gating calibration.\n");
329
330 /*
331 * Reset the read data FIFOs (two resets); only need to issue reset
332 * to PHY0 since in x64 mode, the reset will also go to PHY1.
333 */
334 reset_read_data_fifos();
335
336 /*
337 * Start the automatic read DQS gating calibration process by
338 * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
339 * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
340 * to indicate completion.
341 * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
342 * no errors were seen during calibration.
343 */
344
345 /*
346 * Set bit 30: chooses option to wait 32 cycles instead of
347 * 16 before comparing read data.
348 */
349 setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
350
351 /* Set bit 28 to start automatic read DQS gating calibration */
352 setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
353
354 /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
355 wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
356
357 /*
358 * Check to see if any errors were encountered during calibration
359 * (check MPDGCTRL0[HW_DG_ERR]).
360 * Check both PHYs for x64 configuration, if x32, check only PHY0.
361 */
362 if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
363 errors |= 1;
364
365 if ((bus_size == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
366 errors |= 2;
367
368 /*
369 * DQS gating absolute offset should be modified from
370 * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
371 * reflecting (HW_DG_UPx - 0x80)
372 */
373 modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
374 &mmdc0->mpdgctrl0);
375 modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
376 &mmdc0->mpdgctrl1);
377 if (bus_size == 0x2) {
378 modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
379 &mmdc1->mpdgctrl0);
380 modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
381 &mmdc1->mpdgctrl1);
382 }
383 debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
384
385 /*
386 * **********************
387 * Read Delay calibration
388 * **********************
389 */
390 debug("Starting Read Delay calibration.\n");
391
392 reset_read_data_fifos();
393
394 /*
395 * 4. Issue the Precharge-All command to the DDR device for both
396 * chip selects. If only using one chip select, then precharge
397 * only the desired chip select.
398 */
399 precharge_all(cs0_enable, cs1_enable);
400
401 /*
402 * 9. Read delay-line calibration
403 * Start the automatic read calibration process by asserting
404 * MPRDDLHWCTL[HW_RD_DL_EN].
405 */
406 writel(0x00000030, &mmdc0->mprddlhwctl);
407
408 /*
409 * 10. poll for completion
410 * MMDC indicates that the write data calibration had finished by
411 * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
412 * no error bits were set.
413 */
414 wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
415
416 /* check both PHYs for x64 configuration, if x32, check only PHY0 */
417 if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
418 errors |= 4;
419
420 if ((bus_size == 0x2) && (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
421 errors |= 8;
422
423 debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
424
425 /*
426 * ***********************
427 * Write Delay Calibration
428 * ***********************
429 */
430 debug("Starting Write Delay calibration.\n");
431
432 reset_read_data_fifos();
433
434 /*
435 * 4. Issue the Precharge-All command to the DDR device for both
436 * chip selects. If only using one chip select, then precharge
437 * only the desired chip select.
438 */
439 precharge_all(cs0_enable, cs1_enable);
440
441 /*
442 * 8. Set the WR_DL_ABS# bits to their default values.
443 * Both PHYs for x64 configuration, if x32, do only PHY0.
444 */
445 writel(initdelay, &mmdc0->mpwrdlctl);
446 if (bus_size == 0x2)
447 writel(initdelay, &mmdc1->mpwrdlctl);
448
449 /*
450 * XXX This isn't in the manual. Force a measurement,
451 * for previous delay setup to effect.
452 */
453 force_delay_measurement(bus_size);
454
455 /*
456 * 9. 10. Start the automatic write calibration process
457 * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
458 */
459 writel(0x00000030, &mmdc0->mpwrdlhwctl);
460
461 /*
462 * Poll for completion.
463 * MMDC indicates that the write data calibration had finished
464 * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
465 * Also, ensure that no error bits were set.
466 */
467 wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
468
469 /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
470 if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
471 errors |= 16;
472
473 if ((bus_size == 0x2) && (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
474 errors |= 32;
475
476 debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
477
478 reset_read_data_fifos();
479
480 /* Enable DDR logic power down timer */
481 setbits_le32(&mmdc0->mdpdc, 0x00005500);
482
483 /* Enable Adopt power down timer */
484 clrbits_le32(&mmdc0->mapsr, 0x1);
485
486 /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
487 writel(esdmisc_val, &mmdc0->mdmisc);
488
489 /* Clear DQS pull ups */
490 clrbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000);
491 clrbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000);
492 clrbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000);
493 clrbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000);
494 clrbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000);
495 clrbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000);
496 clrbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000);
497 clrbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000);
498
499 /* Re-enable SDE (chip selects) if they were set initially */
500 if (cs1_enable_initial)
501 /* Set SDE_1 */
502 setbits_le32(&mmdc0->mdctl, 1 << 30);
503
504 if (cs0_enable_initial)
505 /* Set SDE_0 */
506 setbits_le32(&mmdc0->mdctl, 1 << 31);
507
508 /* Re-enable to auto refresh */
509 writel(temp_ref, &mmdc0->mdref);
510
511 /* Clear the MDSCR (including the con_req bit) */
512 writel(0x0, &mmdc0->mdscr); /* CS0 */
513
514 /* Poll to make sure the con_ack bit is clear */
515 wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0);
516
517 /*
518 * Print out the registers that were updated as a result
519 * of the calibration process.
520 */
521 debug("MMDC registers updated from calibration\n");
522 debug("Read DQS gating calibration:\n");
523 debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));
524 debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));
525 debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
526 debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
527 debug("Read calibration:\n");
528 debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));
529 debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
530 debug("Write calibration:\n");
531 debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));
532 debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
533
534 /*
535 * Registers below are for debugging purposes. These print out
536 * the upper and lower boundaries captured during
537 * read DQS gating calibration.
538 */
539 debug("Status registers bounds for read DQS gating:\n");
540 debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
541 debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
542 debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
543 debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
544 debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
545 debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
546 debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
547 debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
548
549 debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
550
551 return errors;
552 }
553 #endif
554
555 #if defined(CONFIG_MX6SX)
556 /* Configure MX6SX mmdc iomux */
557 void mx6sx_dram_iocfg(unsigned width,
558 const struct mx6sx_iomux_ddr_regs *ddr,
559 const struct mx6sx_iomux_grp_regs *grp)
560 {
561 struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
562 struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
563
564 mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
565 mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
566
567 /* DDR IO TYPE */
568 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
569 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
570
571 /* CLOCK */
572 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
573
574 /* ADDRESS */
575 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
576 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
577 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
578
579 /* Control */
580 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
581 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
582 writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
583 writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
584 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
585 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
586 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
587
588 /* Data Strobes */
589 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
590 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
591 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
592 if (width >= 32) {
593 writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
594 writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
595 }
596
597 /* Data */
598 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
599 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
600 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
601 if (width >= 32) {
602 writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
603 writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
604 }
605 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
606 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
607 if (width >= 32) {
608 writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
609 writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
610 }
611 }
612 #endif
613
614 #ifdef CONFIG_MX6UL
615 void mx6ul_dram_iocfg(unsigned width,
616 const struct mx6ul_iomux_ddr_regs *ddr,
617 const struct mx6ul_iomux_grp_regs *grp)
618 {
619 struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
620 struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
621
622 mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
623 mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
624
625 /* DDR IO TYPE */
626 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
627 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
628
629 /* CLOCK */
630 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
631
632 /* ADDRESS */
633 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
634 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
635 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
636
637 /* Control */
638 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
639 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
640 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
641 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
642 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
643
644 /* Data Strobes */
645 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
646 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
647 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
648
649 /* Data */
650 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
651 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
652 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
653 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
654 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
655 }
656 #endif
657
658 #if defined(CONFIG_MX6SL)
659 void mx6sl_dram_iocfg(unsigned width,
660 const struct mx6sl_iomux_ddr_regs *ddr,
661 const struct mx6sl_iomux_grp_regs *grp)
662 {
663 struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
664 struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
665
666 mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
667 mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
668
669 /* DDR IO TYPE */
670 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
671 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
672
673 /* CLOCK */
674 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
675
676 /* ADDRESS */
677 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
678 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
679 mx6_grp_iomux->grp_addds = grp->grp_addds;
680
681 /* Control */
682 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
683 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
684 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
685
686 /* Data Strobes */
687 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
688 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
689 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
690 if (width >= 32) {
691 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
692 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
693 }
694
695 /* Data */
696 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
697 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
698 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
699 if (width >= 32) {
700 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
701 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
702 }
703
704 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
705 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
706 if (width >= 32) {
707 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
708 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
709 }
710 }
711 #endif
712
713 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
714 /* Configure MX6DQ mmdc iomux */
715 void mx6dq_dram_iocfg(unsigned width,
716 const struct mx6dq_iomux_ddr_regs *ddr,
717 const struct mx6dq_iomux_grp_regs *grp)
718 {
719 volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
720 volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
721
722 mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
723 mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
724
725 /* DDR IO Type */
726 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
727 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
728
729 /* Clock */
730 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
731 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
732
733 /* Address */
734 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
735 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
736 mx6_grp_iomux->grp_addds = grp->grp_addds;
737
738 /* Control */
739 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
740 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
741 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
742 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
743 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
744 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
745 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
746
747 /* Data Strobes */
748 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
749 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
750 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
751 if (width >= 32) {
752 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
753 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
754 }
755 if (width >= 64) {
756 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
757 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
758 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
759 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
760 }
761
762 /* Data */
763 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
764 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
765 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
766 if (width >= 32) {
767 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
768 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
769 }
770 if (width >= 64) {
771 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
772 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
773 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
774 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
775 }
776 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
777 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
778 if (width >= 32) {
779 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
780 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
781 }
782 if (width >= 64) {
783 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
784 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
785 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
786 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
787 }
788 }
789 #endif
790
791 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
792 /* Configure MX6SDL mmdc iomux */
793 void mx6sdl_dram_iocfg(unsigned width,
794 const struct mx6sdl_iomux_ddr_regs *ddr,
795 const struct mx6sdl_iomux_grp_regs *grp)
796 {
797 volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
798 volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
799
800 mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
801 mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
802
803 /* DDR IO Type */
804 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
805 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
806
807 /* Clock */
808 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
809 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
810
811 /* Address */
812 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
813 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
814 mx6_grp_iomux->grp_addds = grp->grp_addds;
815
816 /* Control */
817 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
818 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
819 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
820 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
821 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
822 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
823 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
824
825 /* Data Strobes */
826 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
827 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
828 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
829 if (width >= 32) {
830 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
831 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
832 }
833 if (width >= 64) {
834 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
835 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
836 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
837 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
838 }
839
840 /* Data */
841 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
842 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
843 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
844 if (width >= 32) {
845 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
846 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
847 }
848 if (width >= 64) {
849 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
850 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
851 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
852 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
853 }
854 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
855 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
856 if (width >= 32) {
857 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
858 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
859 }
860 if (width >= 64) {
861 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
862 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
863 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
864 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
865 }
866 }
867 #endif
868
869 /*
870 * Configure mx6 mmdc registers based on:
871 * - board-specific memory configuration
872 * - board-specific calibration data
873 * - ddr3/lpddr2 chip details
874 *
875 * The various calculations here are derived from the Freescale
876 * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
877 * MMDC configuration registers based on memory system and memory chip
878 * parameters.
879 *
880 * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
881 * configuration registers based on memory system and memory chip
882 * parameters.
883 *
884 * The defaults here are those which were specified in the spreadsheet.
885 * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
886 * and/or IMX6SLRM section titled MMDC initialization.
887 */
888 #define MR(val, ba, cmd, cs1) \
889 ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
890 #define MMDC1(entry, value) do { \
891 if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
892 !is_cpu_type(MXC_CPU_MX6SL)) \
893 mmdc1->entry = value; \
894 } while (0)
895
896 /*
897 * According JESD209-2B-LPDDR2: Table 103
898 * WL: write latency
899 */
900 static int lpddr2_wl(uint32_t mem_speed)
901 {
902 switch (mem_speed) {
903 case 1066:
904 case 933:
905 return 4;
906 case 800:
907 return 3;
908 case 677:
909 case 533:
910 return 2;
911 case 400:
912 case 333:
913 return 1;
914 default:
915 puts("invalid memory speed\n");
916 hang();
917 }
918
919 return 0;
920 }
921
922 /*
923 * According JESD209-2B-LPDDR2: Table 103
924 * RL: read latency
925 */
926 static int lpddr2_rl(uint32_t mem_speed)
927 {
928 switch (mem_speed) {
929 case 1066:
930 return 8;
931 case 933:
932 return 7;
933 case 800:
934 return 6;
935 case 677:
936 return 5;
937 case 533:
938 return 4;
939 case 400:
940 case 333:
941 return 3;
942 default:
943 puts("invalid memory speed\n");
944 hang();
945 }
946
947 return 0;
948 }
949
950 void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
951 const struct mx6_mmdc_calibration *calib,
952 const struct mx6_lpddr2_cfg *lpddr2_cfg)
953 {
954 volatile struct mmdc_p_regs *mmdc0;
955 u32 val;
956 u8 tcke, tcksrx, tcksre, trrd;
957 u8 twl, txp, tfaw, tcl;
958 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
959 u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
960 u16 cs0_end;
961 u8 coladdr;
962 int clkper; /* clock period in picoseconds */
963 int clock; /* clock freq in mHz */
964 int cs;
965
966 /* only support 16/32 bits */
967 if (sysinfo->dsize > 1)
968 hang();
969
970 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
971
972 clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
973 clkper = (1000 * 1000) / clock; /* pico seconds */
974
975 twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
976
977 /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
978 switch (lpddr2_cfg->density) {
979 case 1:
980 case 2:
981 case 4:
982 trfc = DIV_ROUND_UP(130000, clkper) - 1;
983 txsr = DIV_ROUND_UP(140000, clkper) - 1;
984 break;
985 case 8:
986 trfc = DIV_ROUND_UP(210000, clkper) - 1;
987 txsr = DIV_ROUND_UP(220000, clkper) - 1;
988 break;
989 default:
990 /*
991 * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
992 */
993 hang();
994 break;
995 }
996 /*
997 * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
998 * set them to 0. */
999 txp = DIV_ROUND_UP(7500, clkper) - 1;
1000 tcke = 3;
1001 if (lpddr2_cfg->mem_speed == 333)
1002 tfaw = DIV_ROUND_UP(60000, clkper) - 1;
1003 else
1004 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1005 trrd = DIV_ROUND_UP(10000, clkper) - 1;
1006
1007 /* tckesr for LPDDR2 */
1008 tcksre = DIV_ROUND_UP(15000, clkper);
1009 tcksrx = tcksre;
1010 twr = DIV_ROUND_UP(15000, clkper) - 1;
1011 /*
1012 * tMRR: 2, tMRW: 5
1013 * tMRD should be set to max(tMRR, tMRW)
1014 */
1015 tmrd = 5;
1016 tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
1017 /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
1018 trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
1019 trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
1020 clkper / 10) - 1;
1021 trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
1022 trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
1023 /* To LPDDR2, CL in MDCFG0 refers to RL */
1024 tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
1025 twtr = DIV_ROUND_UP(7500, clkper) - 1;
1026 trtp = DIV_ROUND_UP(7500, clkper) - 1;
1027
1028 cs0_end = 4 * sysinfo->cs_density - 1;
1029
1030 debug("density:%d Gb (%d Gb per chip)\n",
1031 sysinfo->cs_density, lpddr2_cfg->density);
1032 debug("clock: %dMHz (%d ps)\n", clock, clkper);
1033 debug("memspd:%d\n", lpddr2_cfg->mem_speed);
1034 debug("trcd_lp=%d\n", trcd_lp);
1035 debug("trppb_lp=%d\n", trppb_lp);
1036 debug("trpab_lp=%d\n", trpab_lp);
1037 debug("trc_lp=%d\n", trc_lp);
1038 debug("tcke=%d\n", tcke);
1039 debug("tcksrx=%d\n", tcksrx);
1040 debug("tcksre=%d\n", tcksre);
1041 debug("trfc=%d\n", trfc);
1042 debug("txsr=%d\n", txsr);
1043 debug("txp=%d\n", txp);
1044 debug("tfaw=%d\n", tfaw);
1045 debug("tcl=%d\n", tcl);
1046 debug("tras=%d\n", tras);
1047 debug("twr=%d\n", twr);
1048 debug("tmrd=%d\n", tmrd);
1049 debug("twl=%d\n", twl);
1050 debug("trtp=%d\n", trtp);
1051 debug("twtr=%d\n", twtr);
1052 debug("trrd=%d\n", trrd);
1053 debug("cs0_end=%d\n", cs0_end);
1054 debug("ncs=%d\n", sysinfo->ncs);
1055
1056 /*
1057 * board-specific configuration:
1058 * These values are determined empirically and vary per board layout
1059 */
1060 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1061 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1062 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1063 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1064 mmdc0->mprddlctl = calib->p0_mprddlctl;
1065 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1066 mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
1067
1068 /* Read data DQ Byte0-3 delay */
1069 mmdc0->mprddqby0dl = 0x33333333;
1070 mmdc0->mprddqby1dl = 0x33333333;
1071 if (sysinfo->dsize > 0) {
1072 mmdc0->mprddqby2dl = 0x33333333;
1073 mmdc0->mprddqby3dl = 0x33333333;
1074 }
1075
1076 /* Write data DQ Byte0-3 delay */
1077 mmdc0->mpwrdqby0dl = 0xf3333333;
1078 mmdc0->mpwrdqby1dl = 0xf3333333;
1079 if (sysinfo->dsize > 0) {
1080 mmdc0->mpwrdqby2dl = 0xf3333333;
1081 mmdc0->mpwrdqby3dl = 0xf3333333;
1082 }
1083
1084 /*
1085 * In LPDDR2 mode this register should be cleared,
1086 * so no termination will be activated.
1087 */
1088 mmdc0->mpodtctrl = 0;
1089
1090 /* complete calibration */
1091 val = (1 << 11); /* Force measurement on delay-lines */
1092 mmdc0->mpmur0 = val;
1093
1094 /* Step 1: configuration request */
1095 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1096
1097 /* Step 2: Timing configuration */
1098 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
1099 (tfaw << 4) | tcl;
1100 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
1101 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
1102 mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
1103 (trppb_lp << 4) | trpab_lp;
1104 mmdc0->mdotc = 0;
1105
1106 mmdc0->mdasp = cs0_end; /* CS addressing */
1107
1108 /* Step 3: Configure DDR type */
1109 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1110 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
1111 (sysinfo->ralat << 6) | (1 << 3);
1112
1113 /* Step 4: Configure delay while leaving reset */
1114 mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
1115 (sysinfo->rst_to_cke << 0);
1116
1117 /* Step 5: Configure DDR physical parameters (density and burst len) */
1118 coladdr = lpddr2_cfg->coladdr;
1119 if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
1120 coladdr += 4;
1121 else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
1122 coladdr += 1;
1123 mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
1124 (coladdr - 9) << 20 | /* COL */
1125 (0 << 19) | /* Burst Length = 4 for LPDDR2 */
1126 (sysinfo->dsize << 16); /* DDR data bus size */
1127
1128 /* Step 6: Perform ZQ calibration */
1129 val = 0xa1390003; /* one-time HW ZQ calib */
1130 mmdc0->mpzqhwctrl = val;
1131
1132 /* Step 7: Enable MMDC with desired chip select */
1133 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1134 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
1135
1136 /* Step 8: Write Mode Registers to Init LPDDR2 devices */
1137 for (cs = 0; cs < sysinfo->ncs; cs++) {
1138 /* MR63: reset */
1139 mmdc0->mdscr = MR(63, 0, 3, cs);
1140 /* MR10: calibration,
1141 * 0xff is calibration command after intilization.
1142 */
1143 val = 0xA | (0xff << 8);
1144 mmdc0->mdscr = MR(val, 0, 3, cs);
1145 /* MR1 */
1146 val = 0x1 | (0x82 << 8);
1147 mmdc0->mdscr = MR(val, 0, 3, cs);
1148 /* MR2 */
1149 val = 0x2 | (0x04 << 8);
1150 mmdc0->mdscr = MR(val, 0, 3, cs);
1151 /* MR3 */
1152 val = 0x3 | (0x02 << 8);
1153 mmdc0->mdscr = MR(val, 0, 3, cs);
1154 }
1155
1156 /* Step 10: Power down control and self-refresh */
1157 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1158 5 << 12 | /* PWDT_1: 256 cycles */
1159 5 << 8 | /* PWDT_0: 256 cycles */
1160 1 << 6 | /* BOTH_CS_PD */
1161 (tcksrx & 0x7) << 3 |
1162 (tcksre & 0x7);
1163 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1164
1165 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
1166 val = 0xa1310003;
1167 mmdc0->mpzqhwctrl = val;
1168
1169 /* Step 12: Configure and activate periodic refresh */
1170 mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */
1171 (3 << 11); /* REFR: Refresh Rate - 4 refreshes */
1172
1173 /* Step 13: Deassert config request - init complete */
1174 mmdc0->mdscr = 0x00000000;
1175
1176 /* wait for auto-ZQ calibration to complete */
1177 mdelay(1);
1178 }
1179
1180 void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1181 const struct mx6_mmdc_calibration *calib,
1182 const struct mx6_ddr3_cfg *ddr3_cfg)
1183 {
1184 volatile struct mmdc_p_regs *mmdc0;
1185 volatile struct mmdc_p_regs *mmdc1;
1186 u32 val;
1187 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
1188 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
1189 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
1190 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
1191 u16 cs0_end;
1192 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
1193 u8 coladdr;
1194 int clkper; /* clock period in picoseconds */
1195 int clock; /* clock freq in MHz */
1196 int cs;
1197 u16 mem_speed = ddr3_cfg->mem_speed;
1198
1199 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1200 if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
1201 !is_cpu_type(MXC_CPU_MX6SL))
1202 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1203
1204 /* Limit mem_speed for MX6D/MX6Q */
1205 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
1206 if (mem_speed > 1066)
1207 mem_speed = 1066; /* 1066 MT/s */
1208
1209 tcwl = 4;
1210 }
1211 /* Limit mem_speed for MX6S/MX6DL */
1212 else {
1213 if (mem_speed > 800)
1214 mem_speed = 800; /* 800 MT/s */
1215
1216 tcwl = 3;
1217 }
1218
1219 clock = mem_speed / 2;
1220 /*
1221 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
1222 * up to 528 MHz, so reduce the clock to fit chip specs
1223 */
1224 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
1225 if (clock > 528)
1226 clock = 528; /* 528 MHz */
1227 }
1228
1229 clkper = (1000 * 1000) / clock; /* pico seconds */
1230 todtlon = tcwl;
1231 taxpd = tcwl;
1232 tanpd = tcwl;
1233
1234 switch (ddr3_cfg->density) {
1235 case 1: /* 1Gb per chip */
1236 trfc = DIV_ROUND_UP(110000, clkper) - 1;
1237 txs = DIV_ROUND_UP(120000, clkper) - 1;
1238 break;
1239 case 2: /* 2Gb per chip */
1240 trfc = DIV_ROUND_UP(160000, clkper) - 1;
1241 txs = DIV_ROUND_UP(170000, clkper) - 1;
1242 break;
1243 case 4: /* 4Gb per chip */
1244 trfc = DIV_ROUND_UP(260000, clkper) - 1;
1245 txs = DIV_ROUND_UP(270000, clkper) - 1;
1246 break;
1247 case 8: /* 8Gb per chip */
1248 trfc = DIV_ROUND_UP(350000, clkper) - 1;
1249 txs = DIV_ROUND_UP(360000, clkper) - 1;
1250 break;
1251 default:
1252 /* invalid density */
1253 puts("invalid chip density\n");
1254 hang();
1255 break;
1256 }
1257 txpr = txs;
1258
1259 switch (mem_speed) {
1260 case 800:
1261 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1262 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1263 if (ddr3_cfg->pagesz == 1) {
1264 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
1265 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1266 } else {
1267 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1268 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1269 }
1270 break;
1271 case 1066:
1272 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1273 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
1274 if (ddr3_cfg->pagesz == 1) {
1275 tfaw = DIV_ROUND_UP(37500, clkper) - 1;
1276 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
1277 } else {
1278 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1279 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1280 }
1281 break;
1282 default:
1283 puts("invalid memory speed\n");
1284 hang();
1285 break;
1286 }
1287 txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
1288 tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
1289 taonpd = DIV_ROUND_UP(2000, clkper) - 1;
1290 tcksrx = tcksre;
1291 taofpd = taonpd;
1292 twr = DIV_ROUND_UP(15000, clkper) - 1;
1293 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
1294 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
1295 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
1296 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
1297 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
1298 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
1299 trcd = trp;
1300 trtp = twtr;
1301 cs0_end = 4 * sysinfo->cs_density - 1;
1302
1303 debug("density:%d Gb (%d Gb per chip)\n",
1304 sysinfo->cs_density, ddr3_cfg->density);
1305 debug("clock: %dMHz (%d ps)\n", clock, clkper);
1306 debug("memspd:%d\n", mem_speed);
1307 debug("tcke=%d\n", tcke);
1308 debug("tcksrx=%d\n", tcksrx);
1309 debug("tcksre=%d\n", tcksre);
1310 debug("taofpd=%d\n", taofpd);
1311 debug("taonpd=%d\n", taonpd);
1312 debug("todtlon=%d\n", todtlon);
1313 debug("tanpd=%d\n", tanpd);
1314 debug("taxpd=%d\n", taxpd);
1315 debug("trfc=%d\n", trfc);
1316 debug("txs=%d\n", txs);
1317 debug("txp=%d\n", txp);
1318 debug("txpdll=%d\n", txpdll);
1319 debug("tfaw=%d\n", tfaw);
1320 debug("tcl=%d\n", tcl);
1321 debug("trcd=%d\n", trcd);
1322 debug("trp=%d\n", trp);
1323 debug("trc=%d\n", trc);
1324 debug("tras=%d\n", tras);
1325 debug("twr=%d\n", twr);
1326 debug("tmrd=%d\n", tmrd);
1327 debug("tcwl=%d\n", tcwl);
1328 debug("tdllk=%d\n", tdllk);
1329 debug("trtp=%d\n", trtp);
1330 debug("twtr=%d\n", twtr);
1331 debug("trrd=%d\n", trrd);
1332 debug("txpr=%d\n", txpr);
1333 debug("cs0_end=%d\n", cs0_end);
1334 debug("ncs=%d\n", sysinfo->ncs);
1335 debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
1336 debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
1337 debug("SRT=%d\n", ddr3_cfg->SRT);
1338 debug("twr=%d\n", twr);
1339
1340 /*
1341 * board-specific configuration:
1342 * These values are determined empirically and vary per board layout
1343 * see:
1344 * appnote, ddr3 spreadsheet
1345 */
1346 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1347 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1348 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1349 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1350 mmdc0->mprddlctl = calib->p0_mprddlctl;
1351 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1352 if (sysinfo->dsize > 1) {
1353 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
1354 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
1355 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
1356 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
1357 MMDC1(mprddlctl, calib->p1_mprddlctl);
1358 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
1359 }
1360
1361 /* Read data DQ Byte0-3 delay */
1362 mmdc0->mprddqby0dl = 0x33333333;
1363 mmdc0->mprddqby1dl = 0x33333333;
1364 if (sysinfo->dsize > 0) {
1365 mmdc0->mprddqby2dl = 0x33333333;
1366 mmdc0->mprddqby3dl = 0x33333333;
1367 }
1368
1369 if (sysinfo->dsize > 1) {
1370 MMDC1(mprddqby0dl, 0x33333333);
1371 MMDC1(mprddqby1dl, 0x33333333);
1372 MMDC1(mprddqby2dl, 0x33333333);
1373 MMDC1(mprddqby3dl, 0x33333333);
1374 }
1375
1376 /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
1377 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
1378 mmdc0->mpodtctrl = val;
1379 if (sysinfo->dsize > 1)
1380 MMDC1(mpodtctrl, val);
1381
1382 /* complete calibration */
1383 val = (1 << 11); /* Force measurement on delay-lines */
1384 mmdc0->mpmur0 = val;
1385 if (sysinfo->dsize > 1)
1386 MMDC1(mpmur0, val);
1387
1388 /* Step 1: configuration request */
1389 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1390
1391 /* Step 2: Timing configuration */
1392 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
1393 (txpdll << 9) | (tfaw << 4) | tcl;
1394 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
1395 (tras << 16) | (1 << 15) /* trpa */ |
1396 (twr << 9) | (tmrd << 5) | tcwl;
1397 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
1398 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
1399 (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
1400 mmdc0->mdasp = cs0_end; /* CS addressing */
1401
1402 /* Step 3: Configure DDR type */
1403 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1404 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
1405 (sysinfo->ralat << 6);
1406
1407 /* Step 4: Configure delay while leaving reset */
1408 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
1409 (sysinfo->rst_to_cke << 0);
1410
1411 /* Step 5: Configure DDR physical parameters (density and burst len) */
1412 coladdr = ddr3_cfg->coladdr;
1413 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
1414 coladdr += 4;
1415 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
1416 coladdr += 1;
1417 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
1418 (coladdr - 9) << 20 | /* COL */
1419 (1 << 19) | /* Burst Length = 8 for DDR3 */
1420 (sysinfo->dsize << 16); /* DDR data bus size */
1421
1422 /* Step 6: Perform ZQ calibration */
1423 val = 0xa1390001; /* one-time HW ZQ calib */
1424 mmdc0->mpzqhwctrl = val;
1425 if (sysinfo->dsize > 1)
1426 MMDC1(mpzqhwctrl, val);
1427
1428 /* Step 7: Enable MMDC with desired chip select */
1429 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1430 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
1431
1432 /* Step 8: Write Mode Registers to Init DDR3 devices */
1433 for (cs = 0; cs < sysinfo->ncs; cs++) {
1434 /* MR2 */
1435 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
1436 ((tcwl - 3) & 3) << 3;
1437 debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
1438 mmdc0->mdscr = MR(val, 2, 3, cs);
1439 /* MR3 */
1440 debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
1441 mmdc0->mdscr = MR(0, 3, 3, cs);
1442 /* MR1 */
1443 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
1444 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
1445 debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
1446 mmdc0->mdscr = MR(val, 1, 3, cs);
1447 /* MR0 */
1448 val = ((tcl - 1) << 4) | /* CAS */
1449 (1 << 8) | /* DLL Reset */
1450 ((twr - 3) << 9) | /* Write Recovery */
1451 (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
1452 debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
1453 mmdc0->mdscr = MR(val, 0, 3, cs);
1454 /* ZQ calibration */
1455 val = (1 << 10);
1456 mmdc0->mdscr = MR(val, 0, 4, cs);
1457 }
1458
1459 /* Step 10: Power down control and self-refresh */
1460 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1461 5 << 12 | /* PWDT_1: 256 cycles */
1462 5 << 8 | /* PWDT_0: 256 cycles */
1463 1 << 6 | /* BOTH_CS_PD */
1464 (tcksrx & 0x7) << 3 |
1465 (tcksre & 0x7);
1466 if (!sysinfo->pd_fast_exit)
1467 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
1468 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1469
1470 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
1471 val = 0xa1390003;
1472 mmdc0->mpzqhwctrl = val;
1473 if (sysinfo->dsize > 1)
1474 MMDC1(mpzqhwctrl, val);
1475
1476 /* Step 12: Configure and activate periodic refresh */
1477 mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
1478 (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
1479
1480 /* Step 13: Deassert config request - init complete */
1481 mmdc0->mdscr = 0x00000000;
1482
1483 /* wait for auto-ZQ calibration to complete */
1484 mdelay(1);
1485 }
1486
1487 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1488 const struct mx6_mmdc_calibration *calib,
1489 const void *ddr_cfg)
1490 {
1491 if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
1492 mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
1493 } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
1494 mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
1495 } else {
1496 puts("Unsupported ddr type\n");
1497 hang();
1498 }
1499 }
"Das U-Boot" Source Tree