arch/arm/cpu/armv7/mx6/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/errno.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/imx-regs.h>
  30 #include <asm/arch/clock.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <asm/imx-common/boot_mode.h>
  33 #include <asm/imx-common/dma.h>
  34 #include <stdbool.h>
  35 #include <asm/arch/mxc_hdmi.h>
  36 #include <asm/arch/crm_regs.h>
  37
  38 struct scu_regs {
  39         u32     ctrl;
  40         u32     config;
  41         u32     status;
  42         u32     invalidate;
  43         u32     fpga_rev;
  44 };
  45
  46 u32 get_cpu_rev(void)
  47 {
  48         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  49         u32 reg = readl(&anatop->digprog_sololite);
  50         u32 type = ((reg >> 16) & 0xff);
  51
  52         if (type != MXC_CPU_MX6SL) {
  53                 reg = readl(&anatop->digprog);
  54                 type = ((reg >> 16) & 0xff);
  55                 if (type == MXC_CPU_MX6DL) {
  56                         struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  57                         u32 cfg = readl(&scu->config) & 3;
  58
  59                         if (!cfg)
  60                                 type = MXC_CPU_MX6SOLO;
  61                 }
  62         }
  63         reg &= 0xff;            /* mx6 silicon revision */
  64         return (type << 12) | (reg + 0x10);
  65 }
  66
  67 #ifdef CONFIG_REVISION_TAG
  68 u32 __weak get_board_rev(void)
  69 {
  70         u32 cpurev = get_cpu_rev();
  71         u32 type = ((cpurev >> 12) & 0xff);
  72         if (type == MXC_CPU_MX6SOLO)
  73                 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
  74
  75         return cpurev;
  76 }
  77 #endif
  78
  79 void init_aips(void)
  80 {
  81         struct aipstz_regs *aips1, *aips2;
  82
  83         aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
  84         aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  85
  86         /*
  87          * Set all MPROTx to be non-bufferable, trusted for R/W,
  88          * not forced to user-mode.
  89          */
  90         writel(0x77777777, &aips1->mprot0);
  91         writel(0x77777777, &aips1->mprot1);
  92         writel(0x77777777, &aips2->mprot0);
  93         writel(0x77777777, &aips2->mprot1);
  94
  95         /*
  96          * Set all OPACRx to be non-bufferable, not require
  97          * supervisor privilege level for access,allow for
  98          * write access and untrusted master access.
  99          */
 100         writel(0x00000000, &aips1->opacr0);
 101         writel(0x00000000, &aips1->opacr1);
 102         writel(0x00000000, &aips1->opacr2);
 103         writel(0x00000000, &aips1->opacr3);
 104         writel(0x00000000, &aips1->opacr4);
 105         writel(0x00000000, &aips2->opacr0);
 106         writel(0x00000000, &aips2->opacr1);
 107         writel(0x00000000, &aips2->opacr2);
 108         writel(0x00000000, &aips2->opacr3);
 109         writel(0x00000000, &aips2->opacr4);
 110 }
 111
 112 /*
 113  * Set the VDDSOC
 114  *
 115  * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
 116  * them to the specified millivolt level.
 117  * Possible values are from 0.725V to 1.450V in steps of
 118  * 0.025V (25mV).
 119  */
 120 void set_vddsoc(u32 mv)
 121 {
 122         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 123         u32 val, reg = readl(&anatop->reg_core);
 124
 125         if (mv < 725)
 126                 val = 0x00;     /* Power gated off */
 127         else if (mv > 1450)
 128                 val = 0x1F;     /* Power FET switched full on. No regulation */
 129         else
 130                 val = (mv - 700) / 25;
 131
 132         /*
 133          * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
 134          * and set them to the calculated value (0.7V + val * 0.25V)
 135          */
 136         reg = (reg & ~(0x1F << 18)) | (val << 18);
 137         writel(reg, &anatop->reg_core);
 138 }
 139
 140 static void imx_set_wdog_powerdown(bool enable)
 141 {
 142         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 143         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 144
 145         /* Write to the PDE (Power Down Enable) bit */
 146         writew(enable, &wdog1->wmcr);
 147         writew(enable, &wdog2->wmcr);
 148 }
 149
 150 int arch_cpu_init(void)
 151 {
 152         init_aips();
 153
 154         set_vddsoc(1200);       /* Set VDDSOC to 1.2V */
 155
 156         imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 157
 158 #ifdef CONFIG_APBH_DMA
 159         /* Start APBH DMA */
 160         mxs_dma_init();
 161 #endif
 162
 163         return 0;
 164 }
 165
 166 #ifndef CONFIG_SYS_DCACHE_OFF
 167 void enable_caches(void)
 168 {
 169         /* Enable D-cache. I-cache is already enabled in start.S */
 170         dcache_enable();
 171 }
 172 #endif
 173
 174 #if defined(CONFIG_FEC_MXC)
 175 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 176 {
 177         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 178         struct fuse_bank *bank = &ocotp->bank[4];
 179         struct fuse_bank4_regs *fuse =
 180                         (struct fuse_bank4_regs *)bank->fuse_regs;
 181
 182         u32 value = readl(&fuse->mac_addr_high);
 183         mac[0] = (value >> 8);
 184         mac[1] = value ;
 185
 186         value = readl(&fuse->mac_addr_low);
 187         mac[2] = value >> 24 ;
 188         mac[3] = value >> 16 ;
 189         mac[4] = value >> 8 ;
 190         mac[5] = value ;
 191
 192 }
 193 #endif
 194
 195 void boot_mode_apply(unsigned cfg_val)
 196 {
 197         unsigned reg;
 198         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 199         writel(cfg_val, &psrc->gpr9);
 200         reg = readl(&psrc->gpr10);
 201         if (cfg_val)
 202                 reg |= 1 << 28;
 203         else
 204                 reg &= ~(1 << 28);
 205         writel(reg, &psrc->gpr10);
 206 }
 207 /*
 208  * cfg_val will be used for
 209  * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 210  * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
 211  * to SBMR1, which will determine the boot device.
 212  */
 213 const struct boot_mode soc_boot_modes[] = {
 214         {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 215         /* reserved value should start rom usb */
 216         {"usb",         MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 217         {"sata",        MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 218         {"escpi1:0",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
 219         {"escpi1:1",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
 220         {"escpi1:2",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
 221         {"escpi1:3",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
 222         /* 4 bit bus width */
 223         {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 224         {"esdhc2",      MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 225         {"esdhc3",      MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 226         {"esdhc4",      MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 227         {NULL,          0},
 228 };
 229
 230 void s_init(void)
 231 {
 232 }
 233
 234 #ifdef CONFIG_IMX_HDMI
 235 void imx_enable_hdmi_phy(void)
 236 {
 237         struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 238         u8 reg;
 239         reg = readb(&hdmi->phy_conf0);
 240         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 241         writeb(reg, &hdmi->phy_conf0);
 242         udelay(3000);
 243         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 244         writeb(reg, &hdmi->phy_conf0);
 245         udelay(3000);
 246         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 247         writeb(reg, &hdmi->phy_conf0);
 248         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 249 }
 250
 251 void imx_setup_hdmi(void)
 252 {
 253         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 254         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 255         int reg;
 256
 257         /* Turn on HDMI PHY clock */
 258         reg = readl(&mxc_ccm->CCGR2);
 259         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
 260                  MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 261         writel(reg, &mxc_ccm->CCGR2);
 262         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 263         reg = readl(&mxc_ccm->chsccdr);
 264         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
 265                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
 266                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 267         reg |= (CHSCCDR_PODF_DIVIDE_BY_3
 268                  << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 269                  |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 270                  << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 271         writel(reg, &mxc_ccm->chsccdr);
 272 }
 273 #endif