arch/arm/cpu/armv7/omap3/board.c

   1 /*
   2  *
   3  * Common board functions for OMAP3 based boards.
   4  *
   5  * (C) Copyright 2004-2008
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Sunil Kumar <sunilsaini05@gmail.com>
  10  *      Shashi Ranjan <shashiranjanmca05@gmail.com>
  11  *
  12  * Derived from Beagle Board and 3430 SDP code by
  13  *      Richard Woodruff <r-woodruff2@ti.com>
  14  *      Syed Mohammed Khasim <khasim@ti.com>
  15  *
  16  *
  17  * SPDX-License-Identifier:     GPL-2.0+
  18  */
  19 #include <common.h>
  20 #include <dm.h>
  21 #include <mmc.h>
  22 #include <spl.h>
  23 #include <asm/io.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/arch/mem.h>
  26 #include <asm/cache.h>
  27 #include <asm/armv7.h>
  28 #include <asm/gpio.h>
  29 #include <asm/omap_common.h>
  30 #include <asm/arch/mmc_host_def.h>
  31 #include <i2c.h>
  32 #include <linux/compiler.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 /* Declarations */
  37 extern omap3_sysinfo sysinfo;
  38 #ifndef CONFIG_SYS_L2CACHE_OFF
  39 static void omap3_invalidate_l2_cache_secure(void);
  40 #endif
  41
  42 #ifdef CONFIG_DM_GPIO
  43 static const struct omap_gpio_platdata omap34xx_gpio[] = {
  44         { 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
  45         { 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
  46         { 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
  47         { 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
  48         { 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
  49         { 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
  50 };
  51
  52 U_BOOT_DEVICES(am33xx_gpios) = {
  53         { "gpio_omap", &omap34xx_gpio[0] },
  54         { "gpio_omap", &omap34xx_gpio[1] },
  55         { "gpio_omap", &omap34xx_gpio[2] },
  56         { "gpio_omap", &omap34xx_gpio[3] },
  57         { "gpio_omap", &omap34xx_gpio[4] },
  58         { "gpio_omap", &omap34xx_gpio[5] },
  59 };
  60
  61 #else
  62
  63 static const struct gpio_bank gpio_bank_34xx[6] = {
  64         { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
  65         { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
  66         { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
  67         { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
  68         { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
  69         { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
  70 };
  71
  72 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
  73
  74 #endif
  75
  76 #ifdef CONFIG_SPL_BUILD
  77 /*
  78 * We use static variables because global data is not ready yet.
  79 * Initialized data is available in SPL right from the beginning.
  80 * We would not typically need to save these parameters in regular
  81 * U-Boot. This is needed only in SPL at the moment.
  82 */
  83 u32 omap3_boot_device = BOOT_DEVICE_NAND;
  84
  85 /* auto boot mode detection is not possible for OMAP3 - hard code */
  86 u32 spl_boot_mode(void)
  87 {
  88         switch (spl_boot_device()) {
  89         case BOOT_DEVICE_MMC2:
  90                 return MMCSD_MODE_RAW;
  91         case BOOT_DEVICE_MMC1:
  92                 return MMCSD_MODE_FS;
  93                 break;
  94         default:
  95                 puts("spl: ERROR:  unknown device - can't select boot mode\n");
  96                 hang();
  97         }
  98 }
  99
 100 u32 spl_boot_device(void)
 101 {
 102         return omap3_boot_device;
 103 }
 104
 105 int board_mmc_init(bd_t *bis)
 106 {
 107         switch (spl_boot_device()) {
 108         case BOOT_DEVICE_MMC1:
 109                 omap_mmc_init(0, 0, 0, -1, -1);
 110                 break;
 111         case BOOT_DEVICE_MMC2:
 112         case BOOT_DEVICE_MMC2_2:
 113                 omap_mmc_init(1, 0, 0, -1, -1);
 114                 break;
 115         }
 116         return 0;
 117 }
 118
 119 void spl_board_init(void)
 120 {
 121         preloader_console_init();
 122 #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
 123         gpmc_init();
 124 #endif
 125 #ifdef CONFIG_SPL_I2C_SUPPORT
 126         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 127 #endif
 128 }
 129 #endif /* CONFIG_SPL_BUILD */
 130
 131
 132 /******************************************************************************
 133  * Routine: secure_unlock
 134  * Description: Setup security registers for access
 135  *              (GP Device only)
 136  *****************************************************************************/
 137 void secure_unlock_mem(void)
 138 {
 139         struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
 140         struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
 141         struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
 142         struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
 143         struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
 144
 145         /* Protection Module Register Target APE (PM_RT) */
 146         writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
 147         writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
 148         writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
 149         writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
 150
 151         writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
 152         writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
 153         writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
 154
 155         writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
 156         writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
 157         writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
 158         writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
 159
 160         /* IVA Changes */
 161         writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
 162         writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
 163         writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
 164
 165         /* SDRC region 0 public */
 166         writel(UNLOCK_1, &sms_base->rg_att0);
 167 }
 168
 169 /******************************************************************************
 170  * Routine: secureworld_exit()
 171  * Description: If chip is EMU and boot type is external
 172  *              configure secure registers and exit secure world
 173  *              general use.
 174  *****************************************************************************/
 175 void secureworld_exit(void)
 176 {
 177         unsigned long i;
 178
 179         /* configure non-secure access control register */
 180         __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
 181         /* enabling co-processor CP10 and CP11 accesses in NS world */
 182         __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
 183         /*
 184          * allow allocation of locked TLBs and L2 lines in NS world
 185          * allow use of PLE registers in NS world also
 186          */
 187         __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
 188         __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
 189
 190         /* Enable ASA in ACR register */
 191         __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 192         __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
 193         __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
 194
 195         /* Exiting secure world */
 196         __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
 197         __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
 198         __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
 199 }
 200
 201 /******************************************************************************
 202  * Routine: try_unlock_sram()
 203  * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 204  *              general use.
 205  *****************************************************************************/
 206 void try_unlock_memory(void)
 207 {
 208         int mode;
 209         int in_sdram = is_running_in_sdram();
 210
 211         /*
 212          * if GP device unlock device SRAM for general use
 213          * secure code breaks for Secure/Emulation device - HS/E/T
 214          */
 215         mode = get_device_type();
 216         if (mode == GP_DEVICE)
 217                 secure_unlock_mem();
 218
 219         /*
 220          * If device is EMU and boot is XIP external booting
 221          * Unlock firewalls and disable L2 and put chip
 222          * out of secure world
 223          *
 224          * Assuming memories are unlocked by the demon who put us in SDRAM
 225          */
 226         if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
 227             && (!in_sdram)) {
 228                 secure_unlock_mem();
 229                 secureworld_exit();
 230         }
 231
 232         return;
 233 }
 234
 235 /******************************************************************************
 236  * Routine: s_init
 237  * Description: Does early system init of muxing and clocks.
 238  *              - Called path is with SRAM stack.
 239  *****************************************************************************/
 240 void s_init(void)
 241 {
 242         watchdog_init();
 243
 244         try_unlock_memory();
 245
 246 #ifndef CONFIG_SYS_L2CACHE_OFF
 247         /* Invalidate L2-cache from secure mode */
 248         omap3_invalidate_l2_cache_secure();
 249 #endif
 250
 251         set_muxconf_regs();
 252         sdelay(100);
 253
 254         prcm_init();
 255
 256         per_clocks_enable();
 257
 258 #ifdef CONFIG_USB_EHCI_OMAP
 259         ehci_clocks_enable();
 260 #endif
 261 }
 262
 263 #ifdef CONFIG_SPL_BUILD
 264 void board_init_f(ulong dummy)
 265 {
 266         mem_init();
 267 }
 268 #endif
 269
 270 /*
 271  * Routine: misc_init_r
 272  * Description: A basic misc_init_r that just displays the die ID
 273  */
 274 int __weak misc_init_r(void)
 275 {
 276         dieid_num_r();
 277
 278         return 0;
 279 }
 280
 281 /******************************************************************************
 282  * Routine: wait_for_command_complete
 283  * Description: Wait for posting to finish on watchdog
 284  *****************************************************************************/
 285 static void wait_for_command_complete(struct watchdog *wd_base)
 286 {
 287         int pending = 1;
 288         do {
 289                 pending = readl(&wd_base->wwps);
 290         } while (pending);
 291 }
 292
 293 /******************************************************************************
 294  * Routine: watchdog_init
 295  * Description: Shut down watch dogs
 296  *****************************************************************************/
 297 void watchdog_init(void)
 298 {
 299         struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
 300         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 301
 302         /*
 303          * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
 304          * either taken care of by ROM (HS/EMU) or not accessible (GP).
 305          * We need to take care of WD2-MPU or take a PRCM reset. WD3
 306          * should not be running and does not generate a PRCM reset.
 307          */
 308
 309         setbits_le32(&prcm_base->fclken_wkup, 0x20);
 310         setbits_le32(&prcm_base->iclken_wkup, 0x20);
 311         wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
 312
 313         writel(WD_UNLOCK1, &wd2_base->wspr);
 314         wait_for_command_complete(wd2_base);
 315         writel(WD_UNLOCK2, &wd2_base->wspr);
 316 }
 317
 318 /******************************************************************************
 319  * Dummy function to handle errors for EABI incompatibility
 320  *****************************************************************************/
 321 void abort(void)
 322 {
 323 }
 324
 325 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
 326 /******************************************************************************
 327  * OMAP3 specific command to switch between NAND HW and SW ecc
 328  *****************************************************************************/
 329 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 330 {
 331         if (argc < 2 || argc > 3)
 332                 goto usage;
 333
 334         if (strncmp(argv[1], "hw", 2) == 0) {
 335                 if (argc == 2) {
 336                         omap_nand_switch_ecc(1, 1);
 337                 } else {
 338                         if (strncmp(argv[2], "hamming", 7) == 0)
 339                                 omap_nand_switch_ecc(1, 1);
 340                         else if (strncmp(argv[2], "bch8", 4) == 0)
 341                                 omap_nand_switch_ecc(1, 8);
 342                         else
 343                                 goto usage;
 344                 }
 345         } else if (strncmp(argv[1], "sw", 2) == 0) {
 346                 if (argc == 2) {
 347                         omap_nand_switch_ecc(0, 1);
 348                 } else {
 349                         if (strncmp(argv[2], "hamming", 7) == 0)
 350                                 omap_nand_switch_ecc(0, 1);
 351                         else if (strncmp(argv[2], "bch8", 4) == 0)
 352                                 omap_nand_switch_ecc(0, 8);
 353                         else
 354                                 goto usage;
 355                 }
 356         } else {
 357                 goto usage;
 358         }
 359
 360         return 0;
 361
 362 usage:
 363         printf ("Usage: nandecc %s\n", cmdtp->usage);
 364         return 1;
 365 }
 366
 367 U_BOOT_CMD(
 368         nandecc, 3, 1,  do_switch_ecc,
 369         "switch OMAP3 NAND ECC calculation algorithm",
 370         "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
 371         " 8-bit BCH\n"
 372         "                           ecc calculation (second parameter may"
 373         " be omitted).\n"
 374         "nandecc sw               - Switch to NAND software ecc algorithm."
 375 );
 376
 377 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
 378
 379 #ifdef CONFIG_DISPLAY_BOARDINFO
 380 /**
 381  * Print board information
 382  */
 383 int checkboard (void)
 384 {
 385         char *mem_s ;
 386
 387         if (is_mem_sdr())
 388                 mem_s = "mSDR";
 389         else
 390                 mem_s = "LPDDR";
 391
 392         printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
 393                         sysinfo.nand_string);
 394
 395         return 0;
 396 }
 397 #endif  /* CONFIG_DISPLAY_BOARDINFO */
 398
 399 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
 400 {
 401         u32 i, num_params = *parameters;
 402         u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
 403
 404         /*
 405          * copy the parameters to an un-cached area to avoid coherency
 406          * issues
 407          */
 408         for (i = 0; i < num_params; i++) {
 409                 __raw_writel(*parameters, sram_scratch_space);
 410                 parameters++;
 411                 sram_scratch_space++;
 412         }
 413
 414         /* Now make the PPA call */
 415         do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 416 }
 417
 418 void __weak omap3_set_aux_cr_secure(u32 acr)
 419 {
 420         struct emu_hal_params emu_romcode_params;
 421
 422         emu_romcode_params.num_params = 1;
 423         emu_romcode_params.param1 = acr;
 424         omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
 425                                (u32 *)&emu_romcode_params);
 426 }
 427
 428 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
 429                           u32 cpu_variant, u32 cpu_rev)
 430 {
 431         /* Write ACR - affects secure banked bits */
 432         if (get_device_type() == GP_DEVICE)
 433                 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
 434         else
 435                 omap3_set_aux_cr_secure(acr);
 436
 437         /* Write ACR - affects non-secure banked bits - some erratas need it */
 438         asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
 439 }
 440
 441
 442 #ifndef CONFIG_SYS_L2CACHE_OFF
 443 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 444 {
 445         u32 acr;
 446
 447         /* Read ACR */
 448         asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 449         acr &= ~clear_bits;
 450         acr |= set_bits;
 451         v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
 452
 453 }
 454
 455 /* Invalidate the entire L2 cache from secure mode */
 456 static void omap3_invalidate_l2_cache_secure(void)
 457 {
 458         if (get_device_type() == GP_DEVICE) {
 459                 omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
 460         } else {
 461                 struct emu_hal_params emu_romcode_params;
 462                 emu_romcode_params.num_params = 1;
 463                 emu_romcode_params.param1 = 0;
 464                 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
 465                                        (u32 *)&emu_romcode_params);
 466         }
 467 }
 468
 469 void v7_outer_cache_enable(void)
 470 {
 471
 472         /*
 473          * Set L2EN
 474          * On some revisions L2EN bit is banked on some revisions it's not
 475          * No harm in setting both banked bits(in fact this is required
 476          * by an erratum)
 477          */
 478         omap3_update_aux_cr(0x2, 0);
 479 }
 480
 481 void omap3_outer_cache_disable(void)
 482 {
 483         /*
 484          * Clear L2EN
 485          * On some revisions L2EN bit is banked on some revisions it's not
 486          * No harm in clearing both banked bits(in fact this is required
 487          * by an erratum)
 488          */
 489         omap3_update_aux_cr(0, 0x2);
 490 }
 491 #endif /* !CONFIG_SYS_L2CACHE_OFF */