arch/arm/cpu/armv7/start.S

   1 /*
   2  * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
   3  *
   4  * Copyright (c) 2004   Texas Instruments <r-woodruff2@ti.com>
   5  *
   6  * Copyright (c) 2001   Marius Gröger <mag@sysgo.de>
   7  * Copyright (c) 2002   Alex Züpke <azu@sysgo.de>
   8  * Copyright (c) 2002   Gary Jennejohn <garyj@denx.de>
   9  * Copyright (c) 2003   Richard Woodruff <r-woodruff2@ti.com>
  10  * Copyright (c) 2003   Kshitij <kshitij@ti.com>
  11  * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <asm-offsets.h>
  17 #include <config.h>
  18 #include <asm/system.h>
  19 #include <linux/linkage.h>
  20
  21 /*************************************************************************
  22  *
  23  * Startup Code (reset vector)
  24  *
  25  * Do important init only if we don't start from memory!
  26  * Setup memory and board specific bits prior to relocation.
  27  * Relocate armboot to ram. Setup stack.
  28  *
  29  *************************************************************************/
  30
  31         .globl  reset
  32         .globl  save_boot_params_ret
  33
  34 reset:
  35         /* Allow the board to save important registers */
  36         b       save_boot_params
  37 save_boot_params_ret:
  38         /*
  39          * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
  40          * except if in HYP mode already
  41          */
  42         mrs     r0, cpsr
  43         and     r1, r0, #0x1f           @ mask mode bits
  44         teq     r1, #0x1a               @ test for HYP mode
  45         bicne   r0, r0, #0x1f           @ clear all mode bits
  46         orrne   r0, r0, #0x13           @ set SVC mode
  47         orr     r0, r0, #0xc0           @ disable FIQ and IRQ
  48         msr     cpsr,r0
  49
  50 /*
  51  * Setup vector:
  52  * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
  53  * Continue to use ROM code vector only in OMAP4 spl)
  54  */
  55 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
  56         /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
  57         mrc     p15, 0, r0, c1, c0, 0   @ Read CP15 SCTLR Register
  58         bic     r0, #CR_V               @ V = 0
  59         mcr     p15, 0, r0, c1, c0, 0   @ Write CP15 SCTLR Register
  60
  61         /* Set vector address in CP15 VBAR register */
  62         ldr     r0, =_start
  63         mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
  64 #endif
  65
  66         /* the mask ROM code should have PLL and others stable */
  67 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  68         bl      cpu_init_cp15
  69 #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  70         bl      cpu_init_crit
  71 #endif
  72 #endif
  73
  74         bl      _main
  75
  76 /*------------------------------------------------------------------------------*/
  77
  78 ENTRY(c_runtime_cpu_setup)
  79 /*
  80  * If I-cache is enabled invalidate it
  81  */
  82 #ifndef CONFIG_SYS_ICACHE_OFF
  83         mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
  84         mcr     p15, 0, r0, c7, c10, 4  @ DSB
  85         mcr     p15, 0, r0, c7, c5, 4   @ ISB
  86 #endif
  87
  88         bx      lr
  89
  90 ENDPROC(c_runtime_cpu_setup)
  91
  92 /*************************************************************************
  93  *
  94  * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
  95  *      __attribute__((weak));
  96  *
  97  * Stack pointer is not yet initialized at this moment
  98  * Don't save anything to stack even if compiled with -O0
  99  *
 100  *************************************************************************/
 101 ENTRY(save_boot_params)
 102         b       save_boot_params_ret            @ back to my caller
 103 ENDPROC(save_boot_params)
 104         .weak   save_boot_params
 105
 106 /*************************************************************************
 107  *
 108  * cpu_init_cp15
 109  *
 110  * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
 111  * CONFIG_SYS_ICACHE_OFF is defined.
 112  *
 113  *************************************************************************/
 114 ENTRY(cpu_init_cp15)
 115         /*
 116          * Invalidate L1 I/D
 117          */
 118         mov     r0, #0                  @ set up for MCR
 119         mcr     p15, 0, r0, c8, c7, 0   @ invalidate TLBs
 120         mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
 121         mcr     p15, 0, r0, c7, c5, 6   @ invalidate BP array
 122         mcr     p15, 0, r0, c7, c10, 4  @ DSB
 123         mcr     p15, 0, r0, c7, c5, 4   @ ISB
 124
 125         /*
 126          * disable MMU stuff and caches
 127          */
 128         mrc     p15, 0, r0, c1, c0, 0
 129         bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
 130         bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
 131         orr     r0, r0, #0x00000002     @ set bit 1 (--A-) Align
 132         orr     r0, r0, #0x00000800     @ set bit 11 (Z---) BTB
 133 #ifdef CONFIG_SYS_ICACHE_OFF
 134         bic     r0, r0, #0x00001000     @ clear bit 12 (I) I-cache
 135 #else
 136         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-cache
 137 #endif
 138         mcr     p15, 0, r0, c1, c0, 0
 139
 140 #ifdef CONFIG_ARM_ERRATA_716044
 141         mrc     p15, 0, r0, c1, c0, 0   @ read system control register
 142         orr     r0, r0, #1 << 11        @ set bit #11
 143         mcr     p15, 0, r0, c1, c0, 0   @ write system control register
 144 #endif
 145
 146 #if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
 147         mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
 148         orr     r0, r0, #1 << 4         @ set bit #4
 149         mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 150 #endif
 151
 152 #ifdef CONFIG_ARM_ERRATA_743622
 153         mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
 154         orr     r0, r0, #1 << 6         @ set bit #6
 155         mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 156 #endif
 157
 158 #ifdef CONFIG_ARM_ERRATA_751472
 159         mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
 160         orr     r0, r0, #1 << 11        @ set bit #11
 161         mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 162 #endif
 163 #ifdef CONFIG_ARM_ERRATA_761320
 164         mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
 165         orr     r0, r0, #1 << 21        @ set bit #21
 166         mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 167 #endif
 168
 169         mov     r5, lr                  @ Store my Caller
 170         mrc     p15, 0, r1, c0, c0, 0   @ r1 has Read Main ID Register (MIDR)
 171         mov     r3, r1, lsr #20         @ get variant field
 172         and     r3, r3, #0xf            @ r3 has CPU variant
 173         and     r4, r1, #0xf            @ r4 has CPU revision
 174         mov     r2, r3, lsl #4          @ shift variant field for combined value
 175         orr     r2, r4, r2              @ r2 has combined CPU variant + revision
 176
 177 #ifdef CONFIG_ARM_ERRATA_798870
 178         cmp     r2, #0x30               @ Applies to lower than R3p0
 179         bge     skip_errata_798870      @ skip if not affected rev
 180         cmp     r2, #0x20               @ Applies to including and above R2p0
 181         blt     skip_errata_798870      @ skip if not affected rev
 182
 183         mrc     p15, 1, r0, c15, c0, 0  @ read l2 aux ctrl reg
 184         orr     r0, r0, #1 << 7         @ Enable hazard-detect timeout
 185         push    {r1-r5}                 @ Save the cpu info registers
 186         bl      v7_arch_cp15_set_l2aux_ctrl
 187         isb                             @ Recommended ISB after l2actlr update
 188         pop     {r1-r5}                 @ Restore the cpu info - fall through
 189 skip_errata_798870:
 190 #endif
 191
 192 #ifdef CONFIG_ARM_ERRATA_801819
 193         cmp     r2, #0x24               @ Applies to lt including R2p4
 194         bgt     skip_errata_801819      @ skip if not affected rev
 195         cmp     r2, #0x20               @ Applies to including and above R2p0
 196         blt     skip_errata_801819      @ skip if not affected rev
 197         mrc     p15, 0, r0, c0, c0, 6   @ pick up REVIDR reg
 198         and     r0, r0, #1 << 3         @ check REVIDR[3]
 199         cmp     r0, #1 << 3
 200         beq     skip_errata_801819      @ skip erratum if REVIDR[3] is set
 201
 202         mrc     p15, 0, r0, c1, c0, 1   @ read auxilary control register
 203         orr     r0, r0, #3 << 27        @ Disables streaming. All write-allocate
 204                                         @ lines allocate in the L1 or L2 cache.
 205         orr     r0, r0, #3 << 25        @ Disables streaming. All write-allocate
 206                                         @ lines allocate in the L1 cache.
 207         push    {r1-r5}                 @ Save the cpu info registers
 208         bl      v7_arch_cp15_set_acr
 209         pop     {r1-r5}                 @ Restore the cpu info - fall through
 210 skip_errata_801819:
 211 #endif
 212
 213 #ifdef CONFIG_ARM_ERRATA_454179
 214         cmp     r2, #0x21               @ Only on < r2p1
 215         bge     skip_errata_454179
 216
 217         mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
 218         orr     r0, r0, #(0x3 << 6)     @ Set DBSM(BIT7) and IBE(BIT6) bits
 219         push    {r1-r5}                 @ Save the cpu info registers
 220         bl      v7_arch_cp15_set_acr
 221         pop     {r1-r5}                 @ Restore the cpu info - fall through
 222
 223 skip_errata_454179:
 224 #endif
 225
 226 #ifdef CONFIG_ARM_ERRATA_430973
 227         cmp     r2, #0x21               @ Only on < r2p1
 228         bge     skip_errata_430973
 229
 230         mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
 231         orr     r0, r0, #(0x1 << 6)     @ Set IBE bit
 232         push    {r1-r5}                 @ Save the cpu info registers
 233         bl      v7_arch_cp15_set_acr
 234         pop     {r1-r5}                 @ Restore the cpu info - fall through
 235
 236 skip_errata_430973:
 237 #endif
 238
 239 #ifdef CONFIG_ARM_ERRATA_621766
 240         cmp     r2, #0x21               @ Only on < r2p1
 241         bge     skip_errata_621766
 242
 243         mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
 244         orr     r0, r0, #(0x1 << 5)     @ Set L1NEON bit
 245         push    {r1-r5}                 @ Save the cpu info registers
 246         bl      v7_arch_cp15_set_acr
 247         pop     {r1-r5}                 @ Restore the cpu info - fall through
 248
 249 skip_errata_621766:
 250 #endif
 251
 252         mov     pc, r5                  @ back to my caller
 253 ENDPROC(cpu_init_cp15)
 254
 255 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
 256         !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 257 /*************************************************************************
 258  *
 259  * CPU_init_critical registers
 260  *
 261  * setup important registers
 262  * setup memory timing
 263  *
 264  *************************************************************************/
 265 ENTRY(cpu_init_crit)
 266         /*
 267          * Jump to board specific initialization...
 268          * The Mask ROM will have already initialized
 269          * basic memory. Go here to bump up clock rate and handle
 270          * wake up conditions.
 271          */
 272         b       lowlevel_init           @ go setup pll,mux,memory
 273 ENDPROC(cpu_init_crit)
 274 #endif