arch/arm/cpu/armv8/fsl-layerscape/Kconfig

   1 config ARCH_LS1012A
   2         bool
   3         select ARMV8_SET_SMPEN
   4         select FSL_LSCH2
   5         select SYS_FSL_DDR_BE
   6         select SYS_FSL_MMDC
   7         select SYS_FSL_ERRATUM_A010315
   8         select ARCH_EARLY_INIT_R
   9         select BOARD_EARLY_INIT_F
  10
  11 config ARCH_LS1043A
  12         bool
  13         select ARMV8_SET_SMPEN
  14         select FSL_LSCH2
  15         select SYS_FSL_DDR
  16         select SYS_FSL_DDR_BE
  17         select SYS_FSL_DDR_VER_50
  18         select SYS_FSL_ERRATUM_A008850
  19         select SYS_FSL_ERRATUM_A009660
  20         select SYS_FSL_ERRATUM_A009663
  21         select SYS_FSL_ERRATUM_A009929
  22         select SYS_FSL_ERRATUM_A009942
  23         select SYS_FSL_ERRATUM_A010315
  24         select SYS_FSL_ERRATUM_A010539
  25         select SYS_FSL_HAS_DDR3
  26         select SYS_FSL_HAS_DDR4
  27         select ARCH_EARLY_INIT_R
  28         select BOARD_EARLY_INIT_F
  29
  30 config ARCH_LS1046A
  31         bool
  32         select ARMV8_SET_SMPEN
  33         select FSL_LSCH2
  34         select SYS_FSL_DDR
  35         select SYS_FSL_DDR_BE
  36         select SYS_FSL_DDR_VER_50
  37         select SYS_FSL_ERRATUM_A008336
  38         select SYS_FSL_ERRATUM_A008511
  39         select SYS_FSL_ERRATUM_A009801
  40         select SYS_FSL_ERRATUM_A009803
  41         select SYS_FSL_ERRATUM_A009942
  42         select SYS_FSL_ERRATUM_A010165
  43         select SYS_FSL_ERRATUM_A010539
  44         select SYS_FSL_HAS_DDR4
  45         select SYS_FSL_SRDS_2
  46         select ARCH_EARLY_INIT_R
  47         select BOARD_EARLY_INIT_F
  48
  49 config ARCH_LS2080A
  50         bool
  51         select ARMV8_SET_SMPEN
  52         select ARM_ERRATA_826974
  53         select ARM_ERRATA_828024
  54         select ARM_ERRATA_829520
  55         select ARM_ERRATA_833471
  56         select FSL_LSCH3
  57         select SYS_FSL_DDR
  58         select SYS_FSL_DDR_LE
  59         select SYS_FSL_DDR_VER_50
  60         select SYS_FSL_HAS_DP_DDR
  61         select SYS_FSL_HAS_SEC
  62         select SYS_FSL_HAS_DDR4
  63         select SYS_FSL_SEC_COMPAT_5
  64         select SYS_FSL_SEC_LE
  65         select SYS_FSL_SRDS_2
  66         select SYS_FSL_ERRATUM_A008336
  67         select SYS_FSL_ERRATUM_A008511
  68         select SYS_FSL_ERRATUM_A008514
  69         select SYS_FSL_ERRATUM_A008585
  70         select SYS_FSL_ERRATUM_A009635
  71         select SYS_FSL_ERRATUM_A009663
  72         select SYS_FSL_ERRATUM_A009801
  73         select SYS_FSL_ERRATUM_A009803
  74         select SYS_FSL_ERRATUM_A009942
  75         select SYS_FSL_ERRATUM_A010165
  76         select ARCH_EARLY_INIT_R
  77         select BOARD_EARLY_INIT_F
  78
  79 config FSL_LSCH2
  80         bool
  81         select SYS_FSL_HAS_SEC
  82         select SYS_FSL_SEC_COMPAT_5
  83         select SYS_FSL_SEC_BE
  84         select SYS_FSL_SRDS_1
  85         select SYS_HAS_SERDES
  86
  87 config FSL_LSCH3
  88         bool
  89         select SYS_FSL_SRDS_1
  90         select SYS_HAS_SERDES
  91
  92 menu "Layerscape architecture"
  93         depends on FSL_LSCH2 || FSL_LSCH3
  94
  95 config FSL_PCIE_COMPAT
  96         string "PCIe compatible of Kernel DT"
  97         depends on PCIE_LAYERSCAPE
  98         default "fsl,ls1012a-pcie" if ARCH_LS1012A
  99         default "fsl,ls1043a-pcie" if ARCH_LS1043A
 100         default "fsl,ls1046a-pcie" if ARCH_LS1046A
 101         default "fsl,ls2080a-pcie" if ARCH_LS2080A
 102         help
 103           This compatible is used to find pci controller node in Kernel DT
 104           to complete fixup.
 105
 106 config HAS_FEATURE_GIC64K_ALIGN
 107         bool
 108         default y if ARCH_LS1043A
 109
 110 config HAS_FEATURE_ENHANCED_MSI
 111         bool
 112         default y if ARCH_LS1043A
 113
 114 menu "Layerscape PPA"
 115 config FSL_LS_PPA
 116         bool "FSL Layerscape PPA firmware support"
 117         depends on !ARMV8_PSCI
 118         select ARMV8_SEC_FIRMWARE_SUPPORT
 119         select SEC_FIRMWARE_ARMV8_PSCI
 120         select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
 121         help
 122           The FSL Primary Protected Application (PPA) is a software component
 123           which is loaded during boot stage, and then remains resident in RAM
 124           and runs in the TrustZone after boot.
 125           Say y to enable it.
 126 choice
 127         prompt "FSL Layerscape PPA firmware loading-media select"
 128         depends on FSL_LS_PPA
 129         default SYS_LS_PPA_FW_IN_XIP
 130
 131 config SYS_LS_PPA_FW_IN_XIP
 132         bool "XIP"
 133         help
 134           Say Y here if the PPA firmware locate at XIP flash, such
 135           as NOR or QSPI flash.
 136
 137 endchoice
 138
 139 config SYS_LS_PPA_FW_ADDR
 140         hex "Address of PPA firmware loading from"
 141         depends on FSL_LS_PPA
 142         default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
 143         default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
 144         help
 145           If the PPA firmware locate at XIP flash, such as NOR or
 146           QSPI flash, this address is a directly memory-mapped.
 147           If it is in a serial accessed flash, such as NAND and SD
 148           card, it is a byte offset.
 149 endmenu
 150
 151 config SYS_FSL_ERRATUM_A010315
 152         bool "Workaround for PCIe erratum A010315"
 153
 154 config SYS_FSL_ERRATUM_A010539
 155         bool "Workaround for PIN MUX erratum A010539"
 156
 157 config MAX_CPUS
 158         int "Maximum number of CPUs permitted for Layerscape"
 159         default 4 if ARCH_LS1043A
 160         default 4 if ARCH_LS1046A
 161         default 16 if ARCH_LS2080A
 162         default 1
 163         help
 164           Set this number to the maximum number of possible CPUs in the SoC.
 165           SoCs may have multiple clusters with each cluster may have multiple
 166           ports. If some ports are reserved but higher ports are used for
 167           cores, count the reserved ports. This will allocate enough memory
 168           in spin table to properly handle all cores.
 169
 170 config SECURE_BOOT
 171         bool "Secure Boot"
 172         help
 173                 Enable Freescale Secure Boot feature
 174
 175 config QSPI_AHB_INIT
 176         bool "Init the QSPI AHB bus"
 177         help
 178           The default setting for QSPI AHB bus just support 3bytes addressing.
 179           But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
 180           bus for those flashes to support the full QSPI flash size.
 181
 182 config SYS_FSL_IFC_BANK_COUNT
 183         int "Maximum banks of Integrated flash controller"
 184         depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
 185         default 4 if ARCH_LS1043A
 186         default 4 if ARCH_LS1046A
 187         default 8 if ARCH_LS2080A
 188
 189 config SYS_FSL_HAS_DP_DDR
 190         bool
 191
 192 config SYS_FSL_SRDS_1
 193         bool
 194
 195 config SYS_FSL_SRDS_2
 196         bool
 197
 198 config SYS_HAS_SERDES
 199         bool
 200
 201 endmenu
 202
 203 menu "Layerscape clock tree configuration"
 204         depends on FSL_LSCH2 || FSL_LSCH3
 205
 206 config SYS_FSL_CLK
 207         bool "Enable clock tree initialization"
 208         default y
 209
 210 config CLUSTER_CLK_FREQ
 211         int "Reference clock of core cluster"
 212         depends on ARCH_LS1012A
 213         default 100000000
 214         help
 215           This number is the reference clock frequency of core PLL.
 216           For most platforms, the core PLL and Platform PLL have the same
 217           reference clock, but for some platforms, LS1012A for instance,
 218           they are provided sepatately.
 219
 220 config SYS_FSL_PCLK_DIV
 221         int "Platform clock divider"
 222         default 1 if ARCH_LS1043A
 223         default 1 if ARCH_LS1046A
 224         default 2
 225         help
 226           This is the divider that is used to derive Platform clock from
 227           Platform PLL, in another word:
 228                 Platform_clk = Platform_PLL_freq / this_divider
 229
 230 config SYS_FSL_DSPI_CLK_DIV
 231         int "DSPI clock divider"
 232         default 1 if ARCH_LS1043A
 233         default 2
 234         help
 235           This is the divider that is used to derive DSPI clock from Platform
 236           PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
 237
 238 config SYS_FSL_DUART_CLK_DIV
 239         int "DUART clock divider"
 240         default 1 if ARCH_LS1043A
 241         default 2
 242         help
 243           This is the divider that is used to derive DUART clock from Platform
 244           clock, in another word DUART_clk = Platform_clk / this_divider.
 245
 246 config SYS_FSL_I2C_CLK_DIV
 247         int "I2C clock divider"
 248         default 1 if ARCH_LS1043A
 249         default 2
 250         help
 251           This is the divider that is used to derive I2C clock from Platform
 252           clock, in another word I2C_clk = Platform_clk / this_divider.
 253
 254 config SYS_FSL_IFC_CLK_DIV
 255         int "IFC clock divider"
 256         default 1 if ARCH_LS1043A
 257         default 2
 258         help
 259           This is the divider that is used to derive IFC clock from Platform
 260           clock, in another word IFC_clk = Platform_clk / this_divider.
 261
 262 config SYS_FSL_LPUART_CLK_DIV
 263         int "LPUART clock divider"
 264         default 1 if ARCH_LS1043A
 265         default 2
 266         help
 267           This is the divider that is used to derive LPUART clock from Platform
 268           clock, in another word LPUART_clk = Platform_clk / this_divider.
 269
 270 config SYS_FSL_SDHC_CLK_DIV
 271         int "SDHC clock divider"
 272         default 1 if ARCH_LS1043A
 273         default 1 if ARCH_LS1012A
 274         default 2
 275         help
 276           This is the divider that is used to derive SDHC clock from Platform
 277           clock, in another word SDHC_clk = Platform_clk / this_divider.
 278 endmenu
 279
 280 config RESV_RAM
 281         bool
 282         help
 283           Reserve memory from the top, tracked by gd->arch.resv_ram. This
 284           reserved RAM can be used by special driver that resides in memory
 285           after U-Boot exits. It's up to implementation to allocate and allow
 286           access to this reserved memory. For example, the reserved RAM can
 287           be at the high end of physical memory. The reserve RAM may be
 288           excluded from memory bank(s) passed to OS, or marked as reserved.
 289
 290 config SYS_FSL_ERRATUM_A008336
 291         bool
 292
 293 config SYS_FSL_ERRATUM_A008514
 294         bool
 295
 296 config SYS_FSL_ERRATUM_A008585
 297         bool
 298
 299 config SYS_FSL_ERRATUM_A008850
 300         bool
 301
 302 config SYS_FSL_ERRATUM_A009635
 303         bool
 304
 305 config SYS_FSL_ERRATUM_A009660
 306         bool
 307
 308 config SYS_FSL_ERRATUM_A009929
 309         bool