arch/arm/cpu/armv8/fsl-layerscape/soc.c

   1 /*
   2  * Copyright 2014-2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <fsl_ifc.h>
   9 #include <ahci.h>
  10 #include <scsi.h>
  11 #include <asm/arch/soc.h>
  12 #include <asm/io.h>
  13 #include <asm/global_data.h>
  14 #include <asm/arch-fsl-layerscape/config.h>
  15 #ifdef CONFIG_SYS_FSL_DDR
  16 #include <fsl_ddr_sdram.h>
  17 #include <fsl_ddr.h>
  18 #endif
  19 #ifdef CONFIG_CHAIN_OF_TRUST
  20 #include <fsl_validate.h>
  21 #endif
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 bool soc_has_dp_ddr(void)
  26 {
  27         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  28         u32 svr = gur_in32(&gur->svr);
  29
  30         /* LS2085A has DP_DDR */
  31         if (SVR_SOC_VER(svr) == SVR_LS2085)
  32                 return true;
  33
  34         return false;
  35 }
  36
  37 bool soc_has_aiop(void)
  38 {
  39         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  40         u32 svr = gur_in32(&gur->svr);
  41
  42         /* LS2085A has AIOP */
  43         if (SVR_SOC_VER(svr) == SVR_LS2085)
  44                 return true;
  45
  46         return false;
  47 }
  48
  49 #ifdef CONFIG_LS2080A
  50 /*
  51  * This erratum requires setting a value to eddrtqcr1 to
  52  * optimal the DDR performance.
  53  */
  54 static void erratum_a008336(void)
  55 {
  56         u32 *eddrtqcr1;
  57
  58 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  59 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
  60         eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
  61         out_le32(eddrtqcr1, 0x63b30002);
  62 #endif
  63 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
  64         eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
  65         out_le32(eddrtqcr1, 0x63b30002);
  66 #endif
  67 #endif
  68 }
  69
  70 /*
  71  * This erratum requires a register write before being Memory
  72  * controller 3 being enabled.
  73  */
  74 static void erratum_a008514(void)
  75 {
  76         u32 *eddrtqcr1;
  77
  78 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
  79 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
  80         eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
  81         out_le32(eddrtqcr1, 0x63b20002);
  82 #endif
  83 #endif
  84 }
  85 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  86 #define PLATFORM_CYCLE_ENV_VAR  "a009635_interval_val"
  87
  88 static unsigned long get_internval_val_mhz(void)
  89 {
  90         char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
  91         /*
  92          *  interval is the number of platform cycles(MHz) between
  93          *  wake up events generated by EPU.
  94          */
  95         ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
  96
  97         if (interval)
  98                 interval_mhz = simple_strtoul(interval, NULL, 10);
  99
 100         return interval_mhz;
 101 }
 102
 103 void erratum_a009635(void)
 104 {
 105         u32 val;
 106         unsigned long interval_mhz = get_internval_val_mhz();
 107
 108         if (!interval_mhz)
 109                 return;
 110
 111         val = in_le32(DCSR_CGACRE5);
 112         writel(val | 0x00000200, DCSR_CGACRE5);
 113
 114         val = in_le32(EPU_EPCMPR5);
 115         writel(interval_mhz, EPU_EPCMPR5);
 116         val = in_le32(EPU_EPCCR5);
 117         writel(val | 0x82820000, EPU_EPCCR5);
 118         val = in_le32(EPU_EPSMCR5);
 119         writel(val | 0x002f0000, EPU_EPSMCR5);
 120         val = in_le32(EPU_EPECR5);
 121         writel(val | 0x20000000, EPU_EPECR5);
 122         val = in_le32(EPU_EPGCR);
 123         writel(val | 0x80000000, EPU_EPGCR);
 124 }
 125 #endif  /* CONFIG_SYS_FSL_ERRATUM_A009635 */
 126
 127 static void erratum_a008751(void)
 128 {
 129 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751
 130         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 131
 132         writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
 133 #endif
 134 }
 135
 136 static void erratum_rcw_src(void)
 137 {
 138 #if defined(CONFIG_SPL)
 139         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 140         u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
 141         u32 val;
 142
 143         val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 144         val &= ~DCFG_PORSR1_RCW_SRC;
 145         val |= DCFG_PORSR1_RCW_SRC_NOR;
 146         out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
 147 #endif
 148 }
 149
 150 #define I2C_DEBUG_REG 0x6
 151 #define I2C_GLITCH_EN 0x8
 152 /*
 153  * This erratum requires setting glitch_en bit to enable
 154  * digital glitch filter to improve clock stability.
 155  */
 156 static void erratum_a009203(void)
 157 {
 158         u8 __iomem *ptr;
 159 #ifdef CONFIG_SYS_I2C
 160 #ifdef I2C1_BASE_ADDR
 161         ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
 162
 163         writeb(I2C_GLITCH_EN, ptr);
 164 #endif
 165 #ifdef I2C2_BASE_ADDR
 166         ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
 167
 168         writeb(I2C_GLITCH_EN, ptr);
 169 #endif
 170 #ifdef I2C3_BASE_ADDR
 171         ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
 172
 173         writeb(I2C_GLITCH_EN, ptr);
 174 #endif
 175 #ifdef I2C4_BASE_ADDR
 176         ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
 177
 178         writeb(I2C_GLITCH_EN, ptr);
 179 #endif
 180 #endif
 181 }
 182 void bypass_smmu(void)
 183 {
 184         u32 val;
 185         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 186         out_le32(SMMU_SCR0, val);
 187         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 188         out_le32(SMMU_NSCR0, val);
 189 }
 190 void fsl_lsch3_early_init_f(void)
 191 {
 192         erratum_a008751();
 193         erratum_rcw_src();
 194         init_early_memctl_regs();       /* tighten IFC timing */
 195         erratum_a009203();
 196         erratum_a008514();
 197         erratum_a008336();
 198 #ifdef CONFIG_CHAIN_OF_TRUST
 199         /* In case of Secure Boot, the IBR configures the SMMU
 200         * to allow only Secure transactions.
 201         * SMMU must be reset in bypass mode.
 202         * Set the ClientPD bit and Clear the USFCFG Bit
 203         */
 204         if (fsl_check_boot_mode_secure() == 1)
 205                 bypass_smmu();
 206 #endif
 207 }
 208
 209 #ifdef CONFIG_SCSI_AHCI_PLAT
 210 int sata_init(void)
 211 {
 212         struct ccsr_ahci __iomem *ccsr_ahci;
 213
 214         ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
 215         out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 216         out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 217
 218         ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
 219         out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 220         out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 221
 222         ahci_init((void __iomem *)CONFIG_SYS_SATA1);
 223         scsi_scan(0);
 224
 225         return 0;
 226 }
 227 #endif
 228
 229 #elif defined(CONFIG_FSL_LSCH2)
 230 #ifdef CONFIG_SCSI_AHCI_PLAT
 231 int sata_init(void)
 232 {
 233         struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 234
 235         out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 236         out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
 237         out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
 238         out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 239
 240         ahci_init((void __iomem *)CONFIG_SYS_SATA);
 241         scsi_scan(0);
 242
 243         return 0;
 244 }
 245 #endif
 246
 247 static void erratum_a009929(void)
 248 {
 249 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
 250         struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 251         u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
 252         u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
 253
 254         rstrqmr1 |= 0x00000400;
 255         gur_out32(&gur->rstrqmr1, rstrqmr1);
 256         writel(0x01000000, dcsr_cop_ccp);
 257 #endif
 258 }
 259
 260 /*
 261  * This erratum requires setting a value to eddrtqcr1 to optimal
 262  * the DDR performance. The eddrtqcr1 register is in SCFG space
 263  * of LS1043A and the offset is 0x157_020c.
 264  */
 265 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
 266         && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
 267 #error A009660 and A008514 can not be both enabled.
 268 #endif
 269
 270 static void erratum_a009660(void)
 271 {
 272 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
 273         u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
 274         out_be32(eddrtqcr1, 0x63b20042);
 275 #endif
 276 }
 277
 278 static void erratum_a008850_early(void)
 279 {
 280 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
 281         /* part 1 of 2 */
 282         struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
 283         struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 284
 285         /* disables propagation of barrier transactions to DDRC from CCI400 */
 286         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 287
 288         /* disable the re-ordering in DDRC */
 289         ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
 290 #endif
 291 }
 292
 293 void erratum_a008850_post(void)
 294 {
 295 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
 296         /* part 2 of 2 */
 297         struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
 298         struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 299         u32 tmp;
 300
 301         /* enable propagation of barrier transactions to DDRC from CCI400 */
 302         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 303
 304         /* enable the re-ordering in DDRC */
 305         tmp = ddr_in32(&ddr->eor);
 306         tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
 307         ddr_out32(&ddr->eor, tmp);
 308 #endif
 309 }
 310
 311 void fsl_lsch2_early_init_f(void)
 312 {
 313         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 314         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 315
 316 #ifdef CONFIG_FSL_IFC
 317         init_early_memctl_regs();       /* tighten IFC timing */
 318 #endif
 319
 320 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
 321         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 322 #endif
 323         /* Make SEC reads and writes snoopable */
 324         setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
 325                      SCFG_SNPCNFGCR_SECWRSNP);
 326
 327         /*
 328          * Enable snoop requests and DVM message requests for
 329          * Slave insterface S4 (A53 core cluster)
 330          */
 331         out_le32(&cci->slave[4].snoop_ctrl,
 332                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 333
 334         /* Erratum */
 335         erratum_a008850_early(); /* part 1 of 2 */
 336         erratum_a009929();
 337         erratum_a009660();
 338 }
 339 #endif
 340
 341 #ifdef CONFIG_BOARD_LATE_INIT
 342 int board_late_init(void)
 343 {
 344 #ifdef CONFIG_SCSI_AHCI_PLAT
 345         sata_init();
 346 #endif
 347 #ifdef CONFIG_CHAIN_OF_TRUST
 348         fsl_setenv_chain_of_trust();
 349 #endif
 350
 351         return 0;
 352 }
 353 #endif