arch/arm/cpu/tegra20-common/warmboot.c

   1 /*
   2  * (C) Copyright 2010 - 2011
   3  * NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/errno.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/emc.h>
  29 #include <asm/arch/gp_padctrl.h>
  30 #include <asm/arch/pinmux.h>
  31 #include <asm/arch/sdram_param.h>
  32 #include <asm/arch/tegra.h>
  33 #include <asm/arch-tegra/ap.h>
  34 #include <asm/arch-tegra/clk_rst.h>
  35 #include <asm/arch-tegra/pmc.h>
  36 #include <asm/arch-tegra/fuse.h>
  37 #include <asm/arch-tegra/warmboot.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #ifndef CONFIG_TEGRA_CLOCK_SCALING
  42 #error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
  43 #endif
  44
  45 /*
  46  * This is the place in SRAM where the SDRAM parameters are stored. There
  47  * are 4 blocks, one for each RAM code
  48  */
  49 #define SDRAM_PARAMS_BASE       (AP20_BASE_PA_SRAM + 0x188)
  50
  51 /* TODO: If we later add support for the Misc GP controller, refactor this */
  52 union xm2cfga_reg {
  53         struct {
  54                 u32 reserved0:2;
  55                 u32 hsm_en:1;
  56                 u32 reserved1:2;
  57                 u32 preemp_en:1;
  58                 u32 vref_en:1;
  59                 u32 reserved2:5;
  60                 u32 cal_drvdn:5;
  61                 u32 reserved3:3;
  62                 u32 cal_drvup:5;
  63                 u32 reserved4:3;
  64                 u32 cal_drvdn_slwr:2;
  65                 u32 cal_drvup_slwf:2;
  66         };
  67         u32 word;
  68 };
  69
  70 union xm2cfgd_reg {
  71         struct {
  72                 u32 reserved0:2;
  73                 u32 hsm_en:1;
  74                 u32 schmt_en:1;
  75                 u32 lpmd:2;
  76                 u32 vref_en:1;
  77                 u32 reserved1:5;
  78                 u32 cal_drvdn:5;
  79                 u32 reserved2:3;
  80                 u32 cal_drvup:5;
  81                 u32 reserved3:3;
  82                 u32 cal_drvdn_slwr:2;
  83                 u32 cal_drvup_slwf:2;
  84         };
  85         u32 word;
  86 };
  87
  88 /*
  89  * TODO: This register is not documented in the TRM yet. We could move this
  90  * into the EMC and give it a proper interface, but not while it is
  91  * undocumented.
  92  */
  93 union fbio_spare_reg {
  94         struct {
  95                 u32 reserved:24;
  96                 u32 cfg_wb0:8;
  97         };
  98         u32 word;
  99 };
 100
 101 /* We pack the resume information into these unions for later */
 102 union scratch2_reg {
 103         struct {
 104                 u32 pllm_base_divm:5;
 105                 u32 pllm_base_divn:10;
 106                 u32 pllm_base_divp:3;
 107                 u32 pllm_misc_lfcon:4;
 108                 u32 pllm_misc_cpcon:4;
 109                 u32 gp_xm2cfga_padctrl_preemp:1;
 110                 u32 gp_xm2cfgd_padctrl_schmt:1;
 111                 u32 osc_ctrl_xobp:1;
 112                 u32 memory_type:3;
 113         };
 114         u32 word;
 115 };
 116
 117 union scratch4_reg {
 118         struct {
 119                 u32 emc_clock_divider:8;
 120                 u32 pllm_stable_time:8;
 121                 u32 pllx_stable_time:8;
 122                 u32 emc_fbio_spare_cfg_wb0:8;
 123         };
 124         u32 word;
 125 };
 126
 127 union scratch24_reg {
 128         struct {
 129                 u32 emc_auto_cal_wait:8;
 130                 u32 emc_pin_program_wait:8;
 131                 u32 warmboot_wait:8;
 132                 u32 reserved:8;
 133         };
 134         u32 word;
 135 };
 136
 137 int warmboot_save_sdram_params(void)
 138 {
 139         u32 ram_code;
 140         struct sdram_params sdram;
 141         struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
 142         struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 143         struct apb_misc_gp_ctlr *gp =
 144                         (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 145         struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
 146         union scratch2_reg scratch2;
 147         union scratch4_reg scratch4;
 148         union scratch24_reg scratch24;
 149         union xm2cfga_reg xm2cfga;
 150         union xm2cfgd_reg xm2cfgd;
 151         union fbio_spare_reg fbio_spare;
 152
 153         /* get ram code that is used as index to array sdram_params in BCT */
 154         ram_code = (readl(&pmt->pmt_strap_opt_a) >>
 155                         STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
 156         memcpy(&sdram,
 157                (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
 158                sizeof(sdram));
 159
 160         xm2cfga.word = readl(&gp->xm2cfga);
 161         xm2cfgd.word = readl(&gp->xm2cfgd);
 162
 163         scratch2.word = 0;
 164         scratch2.osc_ctrl_xobp = clock_get_osc_bypass();
 165
 166         /* Get the memory PLL settings */
 167         {
 168                 u32 divm, divn, divp, cpcon, lfcon;
 169
 170                 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
 171                                         &cpcon, &lfcon))
 172                         return -1;
 173                 scratch2.pllm_base_divm = divm;
 174                 scratch2.pllm_base_divn = divn;
 175                 scratch2.pllm_base_divp = divp;
 176                 scratch2.pllm_misc_cpcon = cpcon;
 177                 scratch2.pllm_misc_lfcon = lfcon;
 178         }
 179
 180         scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en;
 181         scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en;
 182         scratch2.memory_type = sdram.memory_type;
 183         writel(scratch2.word, &pmc->pmc_scratch2);
 184
 185         /* collect data from various sources for pmc_scratch4 */
 186         fbio_spare.word = readl(&emc->fbio_spare);
 187         scratch4.word = 0;
 188         scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0;
 189         scratch4.emc_clock_divider = sdram.emc_clock_divider;
 190         scratch4.pllm_stable_time = -1;
 191         scratch4.pllx_stable_time = -1;
 192         writel(scratch4.word, &pmc->pmc_scratch4);
 193
 194         /* collect various data from sdram for pmc_scratch24 */
 195         scratch24.word = 0;
 196         scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait;
 197         scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait;
 198         scratch24.warmboot_wait = sdram.warm_boot_wait;
 199         writel(scratch24.word, &pmc->pmc_scratch24);
 200
 201         return 0;
 202 }
 203
 204 static u32 get_major_version(void)
 205 {
 206         u32 major_id;
 207         struct apb_misc_gp_ctlr *gp =
 208                 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 209
 210         major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
 211                         HIDREV_MAJORPREV_SHIFT;
 212         return major_id;
 213 }
 214
 215 static int is_production_mode_fuse_set(struct fuse_regs *fuse)
 216 {
 217         return readl(&fuse->production_mode);
 218 }
 219
 220 static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse)
 221 {
 222         return readl(&fuse->security_mode);
 223 }
 224
 225 static int is_failure_analysis_mode(struct fuse_regs *fuse)
 226 {
 227         return readl(&fuse->fa);
 228 }
 229
 230 static int ap20_is_odm_production_mode(void)
 231 {
 232         struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 233
 234         if (!is_failure_analysis_mode(fuse) &&
 235             is_odm_production_mode_fuse_set(fuse))
 236                 return 1;
 237         else
 238                 return 0;
 239 }
 240
 241 static int ap20_is_production_mode(void)
 242 {
 243         struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 244
 245         if (get_major_version() == 0)
 246                 return 1;
 247
 248         if (!is_failure_analysis_mode(fuse) &&
 249             is_production_mode_fuse_set(fuse) &&
 250             !is_odm_production_mode_fuse_set(fuse))
 251                 return 1;
 252         else
 253                 return 0;
 254 }
 255
 256 static enum fuse_operating_mode fuse_get_operation_mode(void)
 257 {
 258         u32 chip_id;
 259         struct apb_misc_gp_ctlr *gp =
 260                 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 261
 262         chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
 263                         HIDREV_CHIPID_SHIFT;
 264         if (chip_id == CHIPID_TEGRA20) {
 265                 if (ap20_is_odm_production_mode()) {
 266                         printf("!! odm_production_mode is not supported !!\n");
 267                         return MODE_UNDEFINED;
 268                 } else
 269                         if (ap20_is_production_mode())
 270                                 return MODE_PRODUCTION;
 271                         else
 272                                 return MODE_UNDEFINED;
 273         }
 274         return MODE_UNDEFINED;
 275 }
 276
 277 static void determine_crypto_options(int *is_encrypted, int *is_signed,
 278                                      int *use_zero_key)
 279 {
 280         switch (fuse_get_operation_mode()) {
 281         case MODE_PRODUCTION:
 282                 *is_encrypted = 0;
 283                 *is_signed = 1;
 284                 *use_zero_key = 1;
 285                 break;
 286         case MODE_UNDEFINED:
 287         default:
 288                 *is_encrypted = 0;
 289                 *is_signed = 0;
 290                 *use_zero_key  = 0;
 291                 break;
 292         }
 293 }
 294
 295 static int sign_wb_code(u32 start, u32 length, int use_zero_key)
 296 {
 297         int err;
 298         u8 *source;             /* Pointer to source */
 299         u8 *hash;
 300
 301         /* Calculate AES block parameters. */
 302         source = (u8 *)(start + offsetof(struct wb_header, random_aes_block));
 303         length -= offsetof(struct wb_header, random_aes_block);
 304         hash = (u8 *)(start + offsetof(struct wb_header, hash));
 305         err = sign_data_block(source, length, hash);
 306
 307         return err;
 308 }
 309
 310 int warmboot_prepare_code(u32 seg_address, u32 seg_length)
 311 {
 312         int err = 0;
 313         u32 length;                     /* length of the signed/encrypt code */
 314         struct wb_header *dst_header;   /* Pointer to dest WB header */
 315         int is_encrypted;               /* Segment is encrypted */
 316         int is_signed;                  /* Segment is signed */
 317         int use_zero_key;               /* Use key of all zeros */
 318
 319         /* Determine crypto options. */
 320         determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key);
 321
 322         /* Get the actual code limits. */
 323         length = roundup(((u32)wb_end - (u32)wb_start), 16);
 324
 325         /*
 326          * The region specified by seg_address must be in SDRAM and must be
 327          * nonzero in length.
 328          */
 329         if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE ||
 330                 seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) {
 331                 err = -EFAULT;
 332                 goto fail;
 333         }
 334
 335         /* Things must be 16-byte aligned. */
 336         if ((seg_length & 0xF) || (seg_address & 0xF)) {
 337                 err = -EINVAL;
 338                 goto fail;
 339         }
 340
 341         /* Will the code fit? (destination includes wb_header + wb code) */
 342         if (seg_length < (length + sizeof(struct wb_header))) {
 343                 err = -EINVAL;
 344                 goto fail;
 345         }
 346
 347         dst_header = (struct wb_header *)seg_address;
 348         memset((char *)dst_header, 0, sizeof(struct wb_header));
 349
 350         /* Populate the random_aes_block as requested. */
 351         {
 352                 u32 *aes_block = (u32 *)&(dst_header->random_aes_block);
 353                 u32 *end = (u32 *)(((u32)aes_block) +
 354                                    sizeof(dst_header->random_aes_block));
 355
 356                 do {
 357                         *aes_block++ = 0;
 358                 } while (aes_block < end);
 359         }
 360
 361         /* Populate the header. */
 362         dst_header->length_insecure = length + sizeof(struct wb_header);
 363         dst_header->length_secure = length + sizeof(struct wb_header);
 364         dst_header->destination = NV_WB_RUN_ADDRESS;
 365         dst_header->entry_point = NV_WB_RUN_ADDRESS;
 366         dst_header->code_length = length;
 367
 368         if (is_encrypted) {
 369                 printf("!!!! Encryption is not supported !!!!\n");
 370                 dst_header->length_insecure = 0;
 371                 err = -EACCES;
 372                 goto fail;
 373         } else
 374                 /* copy the wb code directly following dst_header. */
 375                 memcpy((char *)(dst_header+1), (char *)wb_start, length);
 376
 377         if (is_signed)
 378                 err = sign_wb_code(seg_address, dst_header->length_insecure,
 379                                    use_zero_key);
 380
 381 fail:
 382         if (err)
 383                 printf("Warning: warmboot code copy failed (error=%d)\n", err);
 384
 385         return err;
 386 }