arch/arm/imx-common/iomux-v3.c

   1 /*
   2  * Based on the iomux-v3.c from Linux kernel:
   3  * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
   4  * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
   5  *                       <armlinux@phytec.de>
   6  *
   7  * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11 #include <common.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/imx-common/iomux-v3.h>
  15 #include <asm/imx-common/sys_proto.h>
  16
  17 static void *base = (void *)IOMUXC_BASE_ADDR;
  18
  19 /*
  20  * configures a single pad in the iomuxer
  21  */
  22 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
  23 {
  24         u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
  25         u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
  26         u32 sel_input_ofs =
  27                 (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
  28         u32 sel_input =
  29                 (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
  30         u32 pad_ctrl_ofs =
  31                 (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
  32         u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
  33
  34 #if defined CONFIG_MX6SL
  35         /* Check whether LVE bit needs to be set */
  36         if (pad_ctrl & PAD_CTL_LVE) {
  37                 pad_ctrl &= ~PAD_CTL_LVE;
  38                 pad_ctrl |= PAD_CTL_LVE_BIT;
  39         }
  40 #endif
  41
  42 #ifdef CONFIG_IOMUX_LPSR
  43         u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
  44
  45         if (lpsr == IOMUX_CONFIG_LPSR) {
  46                 base = (void *)IOMUXC_LPSR_BASE_ADDR;
  47                 mux_mode &= ~IOMUX_CONFIG_LPSR;
  48                 /* set daisy chain sel_input */
  49                 if (sel_input_ofs)
  50                         sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
  51         }
  52 #endif
  53
  54         if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs)
  55                 __raw_writel(mux_mode, base + mux_ctrl_ofs);
  56
  57         if (sel_input_ofs)
  58                 __raw_writel(sel_input, base + sel_input_ofs);
  59
  60 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
  61         if (!(pad_ctrl & NO_PAD_CTRL))
  62                 __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
  63                         base + pad_ctrl_ofs);
  64 #else
  65         if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
  66                 __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
  67 #endif
  68
  69 #ifdef CONFIG_IOMUX_LPSR
  70         if (lpsr == IOMUX_CONFIG_LPSR)
  71                 base = (void *)IOMUXC_BASE_ADDR;
  72 #endif
  73
  74 }
  75
  76 /* configures a list of pads within declared with IOMUX_PADS macro */
  77 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
  78                                       unsigned count)
  79 {
  80         iomux_v3_cfg_t const *p = pad_list;
  81         int stride;
  82         int i;
  83
  84 #if defined(CONFIG_MX6QDL)
  85         stride = 2;
  86         if (!is_mx6dq())
  87                 p += 1;
  88 #else
  89         stride = 1;
  90 #endif
  91         for (i = 0; i < count; i++) {
  92                 imx_iomux_v3_setup_pad(*p);
  93                 p += stride;
  94         }
  95 }
  96
  97 void imx_iomux_set_gpr_register(int group, int start_bit,
  98                                         int num_bits, int value)
  99 {
 100         int i = 0;
 101         u32 reg;
 102         reg = readl(base + group * 4);
 103         while (num_bits) {
 104                 reg &= ~(1<<(start_bit + i));
 105                 i++;
 106                 num_bits--;
 107         }
 108         reg |= (value << start_bit);
 109         writel(reg, base + group * 4);
 110 }
 111
 112 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
 113 void imx_iomux_gpio_set_direction(unsigned int gpio,
 114                                 unsigned int direction)
 115 {
 116         u32 reg;
 117         /*
 118          * Only on Vybrid the input/output buffer enable flags
 119          * are part of the shared mux/conf register.
 120          */
 121         reg = readl(base + (gpio << 2));
 122
 123         if (direction)
 124                 reg |= 0x2;
 125         else
 126                 reg &= ~0x2;
 127
 128         writel(reg, base + (gpio << 2));
 129 }
 130
 131 void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
 132 {
 133         *gpio_state = readl(base + (gpio << 2)) &
 134                 ((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
 135 }
 136 #endif