2 * Copyright 2014-2015, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _FSL_LAYERSCAPE_CPU_H
8 #define _FSL_LAYERSCAPE_CPU_H
10 static struct cpu_type cpu_type_list
[] = {
11 CPU_TYPE_ENTRY(LS2080
, LS2080
, 8),
12 CPU_TYPE_ENTRY(LS2085
, LS2085
, 8),
13 CPU_TYPE_ENTRY(LS2045
, LS2045
, 4),
14 CPU_TYPE_ENTRY(LS1043
, LS1043
, 4),
15 CPU_TYPE_ENTRY(LS2040
, LS2040
, 4),
18 #ifndef CONFIG_SYS_DCACHE_OFF
20 #define SECTION_SHIFT_L0 39UL
21 #define SECTION_SHIFT_L1 30UL
22 #define SECTION_SHIFT_L2 21UL
23 #define BLOCK_SIZE_L0 0x8000000000
24 #define BLOCK_SIZE_L1 0x40000000
25 #define BLOCK_SIZE_L2 0x200000
26 #define NUM_OF_ENTRY 512
27 #define TCR_EL2_PS_40BIT (2 << 16)
29 #define LAYERSCAPE_VA_BITS (40)
30 #define LAYERSCAPE_TCR (TCR_TG0_4K | \
35 TCR_T0SZ(LAYERSCAPE_VA_BITS))
36 #define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \
41 TCR_T0SZ(LAYERSCAPE_VA_BITS))
43 #ifdef CONFIG_FSL_LSCH3
44 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
45 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
46 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
47 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
48 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
49 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
50 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
51 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
52 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
53 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
54 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
55 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
56 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
57 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
58 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
59 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000
60 #define CONFIG_SYS_FSL_MC_SIZE 0x4000000
61 #define CONFIG_SYS_FSL_NI_BASE 0x810000000
62 #define CONFIG_SYS_FSL_NI_SIZE 0x8000000
63 #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
64 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
65 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
66 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
67 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
68 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
69 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
70 #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
71 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
72 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
73 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
74 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
75 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
76 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
77 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
78 #elif defined(CONFIG_FSL_LSCH2)
79 #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
80 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
81 #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
82 #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
83 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
84 #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
85 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
86 #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
87 #define CONFIG_SYS_FSL_IFC_BASE 0x60000000
88 #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
89 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
90 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
91 #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
92 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
93 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
94 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
95 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
96 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
97 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
98 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
99 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
102 struct sys_mmu_table
{
116 static const struct sys_mmu_table early_mmu_table
[] = {
117 #ifdef CONFIG_FSL_LSCH3
118 { CONFIG_SYS_FSL_CCSR_BASE
, CONFIG_SYS_FSL_CCSR_BASE
,
119 CONFIG_SYS_FSL_CCSR_SIZE
, MT_DEVICE_NGNRNE
,
120 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
121 { CONFIG_SYS_FSL_OCRAM_BASE
, CONFIG_SYS_FSL_OCRAM_BASE
,
122 CONFIG_SYS_FSL_OCRAM_SIZE
, MT_NORMAL
, PMD_SECT_NON_SHARE
},
123 /* For IFC Region #1, only the first 4MB is cache-enabled */
124 { CONFIG_SYS_FSL_IFC_BASE1
, CONFIG_SYS_FSL_IFC_BASE1
,
125 CONFIG_SYS_FSL_IFC_SIZE1_1
, MT_NORMAL
, PMD_SECT_NON_SHARE
},
126 { CONFIG_SYS_FSL_IFC_BASE1
+ CONFIG_SYS_FSL_IFC_SIZE1_1
,
127 CONFIG_SYS_FSL_IFC_BASE1
+ CONFIG_SYS_FSL_IFC_SIZE1_1
,
128 CONFIG_SYS_FSL_IFC_SIZE1
- CONFIG_SYS_FSL_IFC_SIZE1_1
,
129 MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
130 { CONFIG_SYS_FLASH_BASE
, CONFIG_SYS_FSL_IFC_BASE1
,
131 CONFIG_SYS_FSL_IFC_SIZE1
, MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
132 { CONFIG_SYS_FSL_DRAM_BASE1
, CONFIG_SYS_FSL_DRAM_BASE1
,
133 CONFIG_SYS_FSL_DRAM_SIZE1
, MT_NORMAL
,
134 PMD_SECT_OUTER_SHARE
| PMD_SECT_NS
},
135 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
136 { CONFIG_SYS_FSL_IFC_BASE2
, CONFIG_SYS_FSL_IFC_BASE2
,
137 CONFIG_SYS_FLASH_BASE
- CONFIG_SYS_FSL_IFC_BASE2
,
138 MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
139 { CONFIG_SYS_FSL_DCSR_BASE
, CONFIG_SYS_FSL_DCSR_BASE
,
140 CONFIG_SYS_FSL_DCSR_SIZE
, MT_DEVICE_NGNRNE
,
141 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
142 { CONFIG_SYS_FSL_DRAM_BASE2
, CONFIG_SYS_FSL_DRAM_BASE2
,
143 CONFIG_SYS_FSL_DRAM_SIZE2
, MT_NORMAL
,
144 PMD_SECT_OUTER_SHARE
| PMD_SECT_NS
},
145 #elif defined(CONFIG_FSL_LSCH2)
146 { CONFIG_SYS_FSL_CCSR_BASE
, CONFIG_SYS_FSL_CCSR_BASE
,
147 CONFIG_SYS_FSL_CCSR_SIZE
, MT_DEVICE_NGNRNE
,
148 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
149 { CONFIG_SYS_FSL_OCRAM_BASE
, CONFIG_SYS_FSL_OCRAM_BASE
,
150 CONFIG_SYS_FSL_OCRAM_SIZE
, MT_NORMAL
, PMD_SECT_NON_SHARE
},
151 { CONFIG_SYS_FSL_DCSR_BASE
, CONFIG_SYS_FSL_DCSR_BASE
,
152 CONFIG_SYS_FSL_DCSR_SIZE
, MT_DEVICE_NGNRNE
,
153 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
154 { CONFIG_SYS_FSL_QSPI_BASE
, CONFIG_SYS_FSL_QSPI_BASE
,
155 CONFIG_SYS_FSL_QSPI_SIZE
, MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
156 { CONFIG_SYS_FSL_IFC_BASE
, CONFIG_SYS_FSL_IFC_BASE
,
157 CONFIG_SYS_FSL_IFC_SIZE
, MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
158 { CONFIG_SYS_FSL_DRAM_BASE1
, CONFIG_SYS_FSL_DRAM_BASE1
,
159 CONFIG_SYS_FSL_DRAM_SIZE1
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
160 { CONFIG_SYS_FSL_DRAM_BASE2
, CONFIG_SYS_FSL_DRAM_BASE2
,
161 CONFIG_SYS_FSL_DRAM_SIZE2
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
165 static const struct sys_mmu_table final_mmu_table
[] = {
166 #ifdef CONFIG_FSL_LSCH3
167 { CONFIG_SYS_FSL_CCSR_BASE
, CONFIG_SYS_FSL_CCSR_BASE
,
168 CONFIG_SYS_FSL_CCSR_SIZE
, MT_DEVICE_NGNRNE
,
169 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
170 { CONFIG_SYS_FSL_OCRAM_BASE
, CONFIG_SYS_FSL_OCRAM_BASE
,
171 CONFIG_SYS_FSL_OCRAM_SIZE
, MT_NORMAL
, PMD_SECT_NON_SHARE
},
172 { CONFIG_SYS_FSL_DRAM_BASE1
, CONFIG_SYS_FSL_DRAM_BASE1
,
173 CONFIG_SYS_FSL_DRAM_SIZE1
, MT_NORMAL
,
174 PMD_SECT_OUTER_SHARE
| PMD_SECT_NS
},
175 { CONFIG_SYS_FSL_QSPI_BASE2
, CONFIG_SYS_FSL_QSPI_BASE2
,
176 CONFIG_SYS_FSL_QSPI_SIZE2
, MT_DEVICE_NGNRNE
,
177 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
178 { CONFIG_SYS_FSL_IFC_BASE2
, CONFIG_SYS_FSL_IFC_BASE2
,
179 CONFIG_SYS_FSL_IFC_SIZE2
, MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
180 { CONFIG_SYS_FSL_DCSR_BASE
, CONFIG_SYS_FSL_DCSR_BASE
,
181 CONFIG_SYS_FSL_DCSR_SIZE
, MT_DEVICE_NGNRNE
,
182 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
183 { CONFIG_SYS_FSL_MC_BASE
, CONFIG_SYS_FSL_MC_BASE
,
184 CONFIG_SYS_FSL_MC_SIZE
, MT_DEVICE_NGNRNE
,
185 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
186 { CONFIG_SYS_FSL_NI_BASE
, CONFIG_SYS_FSL_NI_BASE
,
187 CONFIG_SYS_FSL_NI_SIZE
, MT_DEVICE_NGNRNE
,
188 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
189 /* For QBMAN portal, only the first 64MB is cache-enabled */
190 { CONFIG_SYS_FSL_QBMAN_BASE
, CONFIG_SYS_FSL_QBMAN_BASE
,
191 CONFIG_SYS_FSL_QBMAN_SIZE_1
, MT_NORMAL
,
192 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
| PMD_SECT_NS
},
193 { CONFIG_SYS_FSL_QBMAN_BASE
+ CONFIG_SYS_FSL_QBMAN_SIZE_1
,
194 CONFIG_SYS_FSL_QBMAN_BASE
+ CONFIG_SYS_FSL_QBMAN_SIZE_1
,
195 CONFIG_SYS_FSL_QBMAN_SIZE
- CONFIG_SYS_FSL_QBMAN_SIZE_1
,
196 MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
197 { CONFIG_SYS_PCIE1_PHYS_ADDR
, CONFIG_SYS_PCIE1_PHYS_ADDR
,
198 CONFIG_SYS_PCIE1_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
199 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
200 { CONFIG_SYS_PCIE2_PHYS_ADDR
, CONFIG_SYS_PCIE2_PHYS_ADDR
,
201 CONFIG_SYS_PCIE2_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
202 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
203 { CONFIG_SYS_PCIE3_PHYS_ADDR
, CONFIG_SYS_PCIE3_PHYS_ADDR
,
204 CONFIG_SYS_PCIE3_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
205 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
206 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
207 { CONFIG_SYS_PCIE4_PHYS_ADDR
, CONFIG_SYS_PCIE4_PHYS_ADDR
,
208 CONFIG_SYS_PCIE4_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
209 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
211 { CONFIG_SYS_FSL_WRIOP1_BASE
, CONFIG_SYS_FSL_WRIOP1_BASE
,
212 CONFIG_SYS_FSL_WRIOP1_SIZE
, MT_DEVICE_NGNRNE
,
213 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
214 { CONFIG_SYS_FSL_AIOP1_BASE
, CONFIG_SYS_FSL_AIOP1_BASE
,
215 CONFIG_SYS_FSL_AIOP1_SIZE
, MT_DEVICE_NGNRNE
,
216 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
217 { CONFIG_SYS_FSL_PEBUF_BASE
, CONFIG_SYS_FSL_PEBUF_BASE
,
218 CONFIG_SYS_FSL_PEBUF_SIZE
, MT_DEVICE_NGNRNE
,
219 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
220 { CONFIG_SYS_FSL_DRAM_BASE2
, CONFIG_SYS_FSL_DRAM_BASE2
,
221 CONFIG_SYS_FSL_DRAM_SIZE2
, MT_NORMAL
,
222 PMD_SECT_OUTER_SHARE
| PMD_SECT_NS
},
223 #elif defined(CONFIG_FSL_LSCH2)
224 { CONFIG_SYS_FSL_BOOTROM_BASE
, CONFIG_SYS_FSL_BOOTROM_BASE
,
225 CONFIG_SYS_FSL_BOOTROM_SIZE
, MT_DEVICE_NGNRNE
,
226 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
227 { CONFIG_SYS_FSL_CCSR_BASE
, CONFIG_SYS_FSL_CCSR_BASE
,
228 CONFIG_SYS_FSL_CCSR_SIZE
, MT_DEVICE_NGNRNE
,
229 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
230 { CONFIG_SYS_FSL_OCRAM_BASE
, CONFIG_SYS_FSL_OCRAM_BASE
,
231 CONFIG_SYS_FSL_OCRAM_SIZE
, MT_NORMAL
, PMD_SECT_NON_SHARE
},
232 { CONFIG_SYS_FSL_DCSR_BASE
, CONFIG_SYS_FSL_DCSR_BASE
,
233 CONFIG_SYS_FSL_DCSR_SIZE
, MT_DEVICE_NGNRNE
,
234 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
235 { CONFIG_SYS_FSL_QSPI_BASE
, CONFIG_SYS_FSL_QSPI_BASE
,
236 CONFIG_SYS_FSL_QSPI_SIZE
, MT_DEVICE_NGNRNE
,
237 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
238 { CONFIG_SYS_FSL_IFC_BASE
, CONFIG_SYS_FSL_IFC_BASE
,
239 CONFIG_SYS_FSL_IFC_SIZE
, MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
240 { CONFIG_SYS_FSL_DRAM_BASE1
, CONFIG_SYS_FSL_DRAM_BASE1
,
241 CONFIG_SYS_FSL_DRAM_SIZE1
, MT_NORMAL
,
242 PMD_SECT_OUTER_SHARE
| PMD_SECT_NS
},
243 { CONFIG_SYS_FSL_QBMAN_BASE
, CONFIG_SYS_FSL_QBMAN_BASE
,
244 CONFIG_SYS_FSL_QBMAN_SIZE
, MT_DEVICE_NGNRNE
,
245 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
246 { CONFIG_SYS_FSL_DRAM_BASE2
, CONFIG_SYS_FSL_DRAM_BASE2
,
247 CONFIG_SYS_FSL_DRAM_SIZE2
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
248 { CONFIG_SYS_PCIE1_PHYS_ADDR
, CONFIG_SYS_PCIE1_PHYS_ADDR
,
249 CONFIG_SYS_PCIE1_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
250 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
251 { CONFIG_SYS_PCIE2_PHYS_ADDR
, CONFIG_SYS_PCIE2_PHYS_ADDR
,
252 CONFIG_SYS_PCIE2_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
253 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
254 { CONFIG_SYS_PCIE3_PHYS_ADDR
, CONFIG_SYS_PCIE3_PHYS_ADDR
,
255 CONFIG_SYS_PCIE3_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
256 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
257 { CONFIG_SYS_FSL_DRAM_BASE3
, CONFIG_SYS_FSL_DRAM_BASE3
,
258 CONFIG_SYS_FSL_DRAM_SIZE3
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
263 int fsl_qoriq_core_to_cluster(unsigned int core
);
265 #endif /* _FSL_LAYERSCAPE_CPU_H */