arch/arm/include/asm/arch-kirkwood/cpu.h

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22  * MA 02110-1301 USA
  23  */
  24
  25 #ifndef _KWCPU_H
  26 #define _KWCPU_H
  27
  28 #include <asm/system.h>
  29
  30 #ifndef __ASSEMBLY__
  31
  32 #define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
  33                         | (attr << 8) | (kw_winctrl_calcsize(size) << 16))
  34
  35 #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)      \
  36                 ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
  37
  38 #define KW_REG_DEVICE_ID                (KW_MPP_BASE + 0x34)
  39 #define KW_REG_SYSRST_CNT               (KW_MPP_BASE + 0x50)
  40 #define SYSRST_CNT_1SEC_VAL             (25*1000000)
  41 #define KW_REG_MPP_OUT_DRV_REG          (KW_MPP_BASE + 0xE0)
  42
  43 enum memory_bank {
  44         BANK0,
  45         BANK1,
  46         BANK2,
  47         BANK3
  48 };
  49
  50 enum kwcpu_winen {
  51         KWCPU_WIN_DISABLE,
  52         KWCPU_WIN_ENABLE
  53 };
  54
  55 enum kwcpu_target {
  56         KWCPU_TARGET_RESERVED,
  57         KWCPU_TARGET_MEMORY,
  58         KWCPU_TARGET_1RESERVED,
  59         KWCPU_TARGET_SASRAM,
  60         KWCPU_TARGET_PCIE
  61 };
  62
  63 enum kwcpu_attrib {
  64         KWCPU_ATTR_SASRAM = 0x01,
  65         KWCPU_ATTR_DRAM_CS0 = 0x0e,
  66         KWCPU_ATTR_DRAM_CS1 = 0x0d,
  67         KWCPU_ATTR_DRAM_CS2 = 0x0b,
  68         KWCPU_ATTR_DRAM_CS3 = 0x07,
  69         KWCPU_ATTR_NANDFLASH = 0x2f,
  70         KWCPU_ATTR_SPIFLASH = 0x1e,
  71         KWCPU_ATTR_BOOTROM = 0x1d,
  72         KWCPU_ATTR_PCIE_IO = 0xe0,
  73         KWCPU_ATTR_PCIE_MEM = 0xe8
  74 };
  75
  76 /*
  77  * Default Device Address MAP BAR values
  78  */
  79 #define KW_DEFADR_PCI_MEM       0x90000000
  80 #define KW_DEFADR_PCI_IO        0xC0000000
  81 #define KW_DEFADR_PCI_IO_REMAP  0xC0000000
  82 #define KW_DEFADR_SASRAM        0xC8010000
  83 #define KW_DEFADR_NANDF         0xD8000000
  84 #define KW_DEFADR_SPIF          0xE8000000
  85 #define KW_DEFADR_BOOTROM       0xF8000000
  86
  87 /*
  88  * read feroceon/sheeva core extra feature register
  89  * using co-proc instruction
  90  */
  91 static inline unsigned int readfr_extra_feature_reg(void)
  92 {
  93         unsigned int val;
  94         asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
  95                         (val)::"cc");
  96         return val;
  97 }
  98
  99 /*
 100  * write feroceon/sheeva core extra feature register
 101  * using co-proc instruction
 102  */
 103 static inline void writefr_extra_feature_reg(unsigned int val)
 104 {
 105         asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
 106                         (val):"cc");
 107         isb();
 108 }
 109
 110 /*
 111  * MBus-L to Mbus Bridge Registers
 112  * Ref: Datasheet sec:A.3
 113  */
 114 struct kwwin_registers {
 115         u32 ctrl;
 116         u32 base;
 117         u32 remap_lo;
 118         u32 remap_hi;
 119 };
 120
 121 /*
 122  * CPU control and status Registers
 123  * Ref: Datasheet sec:A.3.2
 124  */
 125 struct kwcpu_registers {
 126         u32 config;     /*0x20100 */
 127         u32 ctrl_stat;  /*0x20104 */
 128         u32 rstoutn_mask; /* 0x20108 */
 129         u32 sys_soft_rst; /* 0x2010C */
 130         u32 ahb_mbus_cause_irq; /* 0x20110 */
 131         u32 ahb_mbus_mask_irq; /* 0x20114 */
 132         u32 pad1[2];
 133         u32 ftdll_config; /* 0x20120 */
 134         u32 pad2;
 135         u32 l2_cfg;     /* 0x20128 */
 136 };
 137
 138 /*
 139  * GPIO Registers
 140  * Ref: Datasheet sec:A.19
 141  */
 142 struct kwgpio_registers {
 143         u32 dout;
 144         u32 oe;
 145         u32 blink_en;
 146         u32 din_pol;
 147         u32 din;
 148         u32 irq_cause;
 149         u32 irq_mask;
 150         u32 irq_level;
 151 };
 152
 153 /*
 154  * functions
 155  */
 156 void reset_cpu(unsigned long ignored);
 157 unsigned char get_random_hex(void);
 158 unsigned int kw_sdram_bar(enum memory_bank bank);
 159 unsigned int kw_sdram_bs(enum memory_bank bank);
 160 int kw_config_adr_windows(void);
 161 void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
 162                 unsigned int gpp0_oe, unsigned int gpp1_oe);
 163 int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
 164                 unsigned int mpp16_23, unsigned int mpp24_31,
 165                 unsigned int mpp32_39, unsigned int mpp40_47,
 166                 unsigned int mpp48_55);
 167 unsigned int kw_winctrl_calcsize(unsigned int sizeval);
 168 #endif /* __ASSEMBLY__ */
 169 #endif /* _KWCPU_H */