arch/arm/include/asm/arch-mx51/asm-offsets.h

   1 /*
   2  * needed for arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
   3  *
   4  * These should be auto-generated
   5  */
   6 /* CCM */
   7 #define CLKCTL_CCR              0x00
   8 #define CLKCTL_CCDR             0x04
   9 #define CLKCTL_CSR              0x08
  10 #define CLKCTL_CCSR             0x0C
  11 #define CLKCTL_CACRR            0x10
  12 #define CLKCTL_CBCDR            0x14
  13 #define CLKCTL_CBCMR            0x18
  14 #define CLKCTL_CSCMR1           0x1C
  15 #define CLKCTL_CSCMR2           0x20
  16 #define CLKCTL_CSCDR1           0x24
  17 #define CLKCTL_CS1CDR           0x28
  18 #define CLKCTL_CS2CDR           0x2C
  19 #define CLKCTL_CDCDR            0x30
  20 #define CLKCTL_CHSCCDR          0x34
  21 #define CLKCTL_CSCDR2           0x38
  22 #define CLKCTL_CSCDR3           0x3C
  23 #define CLKCTL_CSCDR4           0x40
  24 #define CLKCTL_CWDR             0x44
  25 #define CLKCTL_CDHIPR           0x48
  26 #define CLKCTL_CDCR             0x4C
  27 #define CLKCTL_CTOR             0x50
  28 #define CLKCTL_CLPCR            0x54
  29 #define CLKCTL_CISR             0x58
  30 #define CLKCTL_CIMR             0x5C
  31 #define CLKCTL_CCOSR            0x60
  32 #define CLKCTL_CGPR             0x64
  33 #define CLKCTL_CCGR0            0x68
  34 #define CLKCTL_CCGR1            0x6C
  35 #define CLKCTL_CCGR2            0x70
  36 #define CLKCTL_CCGR3            0x74
  37 #define CLKCTL_CCGR4            0x78
  38 #define CLKCTL_CCGR5            0x7C
  39 #define CLKCTL_CCGR6            0x80
  40 #define CLKCTL_CMEOR            0x84
  41
  42 /* DPLL */
  43 #define PLL_DP_CTL      0x00
  44 #define PLL_DP_CONFIG   0x04
  45 #define PLL_DP_OP       0x08
  46 #define PLL_DP_MFD      0x0C
  47 #define PLL_DP_MFN      0x10
  48 #define PLL_DP_HFS_OP   0x1C
  49 #define PLL_DP_HFS_MFD  0x20
  50 #define PLL_DP_HFS_MFN  0x24