arch/arm/include/asm/arch-mxs/sys_proto.h

   1 /*
   2  * Freescale i.MX23/i.MX28 specific functions
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __MXS_SYS_PROTO_H__
  11 #define __MXS_SYS_PROTO_H__
  12
  13 #include <asm/imx-common/sys_proto.h>
  14
  15 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
  16
  17 #ifdef CONFIG_SPL_BUILD
  18
  19 #if defined(CONFIG_MX23)
  20 #include <asm/arch/iomux-mx23.h>
  21 #elif defined(CONFIG_MX28)
  22 #include <asm/arch/iomux-mx28.h>
  23 #endif
  24
  25 void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
  26                          const iomux_cfg_t *iomux_setup,
  27                          const unsigned int iomux_size);
  28 #endif
  29
  30 struct mxs_pair {
  31         uint8_t boot_pads;
  32         uint8_t boot_mask;
  33         const char *mode;
  34 };
  35
  36 static const struct mxs_pair mxs_boot_modes[] = {
  37 #if defined(CONFIG_MX23)
  38         { 0x00, 0x0f, "USB" },
  39         { 0x01, 0x1f, "I2C, master" },
  40         { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
  41         { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
  42         { 0x04, 0x1f, "NAND" },
  43         { 0x06, 0x1f, "JTAG" },
  44         { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
  45         { 0x09, 0x1f, "SSP SD/MMC #0" },
  46         { 0x0a, 0x1f, "SSP SD/MMC #1" },
  47         { 0x00, 0x00, "Reserved/Unknown/Wrong" },
  48 #elif defined(CONFIG_MX28)
  49         { 0x00, 0x0f, "USB #0" },
  50         { 0x01, 0x1f, "I2C #0, master, 3V3" },
  51         { 0x11, 0x1f, "I2C #0, master, 1V8" },
  52         { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
  53         { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
  54         { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
  55         { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
  56         { 0x04, 0x1f, "NAND, 3V3" },
  57         { 0x14, 0x1f, "NAND, 1V8" },
  58         { 0x06, 0x1f, "JTAG" },
  59         { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
  60         { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
  61         { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
  62         { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
  63         { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
  64         { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
  65         { 0x00, 0x00, "Reserved/Unknown/Wrong" },
  66 #endif
  67 };
  68
  69 #define MXS_BM_USB                      0x00
  70 #define MXS_BM_I2C_MASTER_3V3           0x01
  71 #define MXS_BM_I2C_MASTER_1V8           0x11
  72 #define MXS_BM_SPI2_MASTER_3V3_NOR      0x02
  73 #define MXS_BM_SPI2_MASTER_1V8_NOR      0x12
  74 #define MXS_BM_SPI3_MASTER_3V3_NOR      0x03
  75 #define MXS_BM_SPI3_MASTER_1V8_NOR      0x13
  76 #define MXS_BM_NAND_3V3                 0x04
  77 #define MXS_BM_NAND_1V8                 0x14
  78 #define MXS_BM_JTAG                     0x06
  79 #define MXS_BM_SPI3_MASTER_3V3_EEPROM   0x08
  80 #define MXS_BM_SPI3_MASTER_1V8_EEPROM   0x18
  81 #define MXS_BM_SDMMC0_3V3               0x09
  82 #define MXS_BM_SDMMC0_1V8               0x19
  83 #define MXS_BM_SDMMC1_3V3               0x0a
  84 #define MXS_BM_SDMMC1_1V8               0x1a
  85
  86 struct mxs_spl_data {
  87         uint8_t         boot_mode_idx;
  88         uint32_t        mem_dram_size;
  89 };
  90
  91 int mxs_dram_init(void);
  92
  93 #endif  /* __SYS_PROTO_H__ */