arch/arm/include/asm/arch-s32v234/mc_me_regs.h

   1 /*
   2  * (C) Copyright 2015, Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
   8 #define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
   9
  10 #ifndef __ASSEMBLY__
  11
  12 /* MC_ME registers definitions */
  13
  14 /* MC_ME_GS */
  15 #define MC_ME_GS                                                (MC_ME_BASE_ADDR + 0x00000000)
  16
  17 #define MC_ME_GS_S_SYSCLK_FIRC                  (0x0 << 0)
  18 #define MC_ME_GS_S_SYSCLK_FXOSC                 (0x1 << 0)
  19 #define MC_ME_GS_S_SYSCLK_ARMPLL                (0x2 << 0)
  20 #define MC_ME_GS_S_STSCLK_DISABLE               (0xF << 0)
  21 #define MC_ME_GS_S_FIRC                                 (1 << 4)
  22 #define MC_ME_GS_S_XOSC                                 (1 << 5)
  23 #define MC_ME_GS_S_ARMPLL                               (1 << 6)
  24 #define MC_ME_GS_S_PERPLL                               (1 << 7)
  25 #define MC_ME_GS_S_ENETPLL                              (1 << 8)
  26 #define MC_ME_GS_S_DDRPLL                               (1 << 9)
  27 #define MC_ME_GS_S_VIDEOPLL                             (1 << 10)
  28 #define MC_ME_GS_S_MVR                                  (1 << 20)
  29 #define MC_ME_GS_S_PDO                                  (1 << 23)
  30 #define MC_ME_GS_S_MTRANS                               (1 << 27)
  31 #define MC_ME_GS_S_CRT_MODE_RESET               (0x0 << 28)
  32 #define MC_ME_GS_S_CRT_MODE_TEST                (0x1 << 28)
  33 #define MC_ME_GS_S_CRT_MODE_DRUN                (0x3 << 28)
  34 #define MC_ME_GS_S_CRT_MODE_RUN0                (0x4 << 28)
  35 #define MC_ME_GS_S_CRT_MODE_RUN1                (0x5 << 28)
  36 #define MC_ME_GS_S_CRT_MODE_RUN2                (0x6 << 28)
  37 #define MC_ME_GS_S_CRT_MODE_RUN3                (0x7 << 28)
  38
  39 /* MC_ME_MCTL */
  40 #define MC_ME_MCTL                                              (MC_ME_BASE_ADDR + 0x00000004)
  41
  42 #define MC_ME_MCTL_KEY                                  (0x00005AF0)
  43 #define MC_ME_MCTL_INVERTEDKEY                  (0x0000A50F)
  44 #define MC_ME_MCTL_RESET                                (0x0 << 28)
  45 #define MC_ME_MCTL_TEST                                 (0x1 << 28)
  46 #define MC_ME_MCTL_DRUN                                 (0x3 << 28)
  47 #define MC_ME_MCTL_RUN0                                 (0x4 << 28)
  48 #define MC_ME_MCTL_RUN1                                 (0x5 << 28)
  49 #define MC_ME_MCTL_RUN2                                 (0x6 << 28)
  50 #define MC_ME_MCTL_RUN3                                 (0x7 << 28)
  51
  52 /* MC_ME_ME */
  53 #define MC_ME_ME                                                (MC_ME_BASE_ADDR + 0x00000008)
  54
  55 #define MC_ME_ME_RESET_FUNC                             (1 << 0)
  56 #define MC_ME_ME_TEST                                   (1 << 1)
  57 #define MC_ME_ME_DRUN                                   (1 << 3)
  58 #define MC_ME_ME_RUN0                                   (1 << 4)
  59 #define MC_ME_ME_RUN1                                   (1 << 5)
  60 #define MC_ME_ME_RUN2                                   (1 << 6)
  61 #define MC_ME_ME_RUN3                                   (1 << 7)
  62
  63 /* MC_ME_RUN_PCn */
  64 #define MC_ME_RUN_PCn(n)                                (MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n))
  65
  66 #define MC_ME_RUN_PCn_RESET                             (1 << 0)
  67 #define MC_ME_RUN_PCn_TEST                              (1 << 1)
  68 #define MC_ME_RUN_PCn_DRUN                              (1 << 3)
  69 #define MC_ME_RUN_PCn_RUN0                              (1 << 4)
  70 #define MC_ME_RUN_PCn_RUN1                              (1 << 5)
  71 #define MC_ME_RUN_PCn_RUN2                              (1 << 6)
  72 #define MC_ME_RUN_PCn_RUN3                              (1 << 7)
  73
  74 /*
  75  * MC_ME_RESET_MC/MC_ME_TEST_MC
  76  * MC_ME_DRUN_MC
  77  * MC_ME_RUNn_MC
  78  */
  79 #define MC_ME_RESET_MC                                          (MC_ME_BASE_ADDR + 0x00000020)
  80 #define MC_ME_TEST_MC                                           (MC_ME_BASE_ADDR + 0x00000024)
  81 #define MC_ME_DRUN_MC                                           (MC_ME_BASE_ADDR + 0x0000002C)
  82 #define MC_ME_RUNn_MC(n)                                        (MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n))
  83
  84 #define MC_ME_RUNMODE_MC_SYSCLK(val)    (MC_ME_RUNMODE_MC_SYSCLK_MASK & (val))
  85 #define MC_ME_RUNMODE_MC_SYSCLK_MASK    (0x0000000F)
  86 #define MC_ME_RUNMODE_MC_FIRCON                 (1 << 4)
  87 #define MC_ME_RUNMODE_MC_XOSCON                 (1 << 5)
  88 #define MC_ME_RUNMODE_MC_PLL(pll)               (1 << (6 + (pll)))
  89 #define MC_ME_RUNMODE_MC_MVRON                  (1 << 20)
  90 #define MC_ME_RUNMODE_MC_PDO                    (1 << 23)
  91 #define MC_ME_RUNMODE_MC_PWRLVL0                (1 << 28)
  92 #define MC_ME_RUNMODE_MC_PWRLVL1                (1 << 29)
  93 #define MC_ME_RUNMODE_MC_PWRLVL2                (1 << 30)
  94
  95 /* MC_ME_DRUN_SEC_CC_I */
  96 #define MC_ME_DRUN_SEC_CC_I                                     (MC_ME_BASE_ADDR + 0x260)
  97 /* MC_ME_RUNn_SEC_CC_I */
  98 #define MC_ME_RUNn_SEC_CC_I(n)                          (MC_ME_BASE_ADDR + 0x270 + (n) * 0x10)
  99 #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset)       ((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset)
 100 #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET   (4)
 101 #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET   (8)
 102 #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET   (12)
 103 #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK              (0x3)
 104
 105 /*
 106  * ME_PCTLn
 107  * Please note that these registers are 8 bits width, so
 108  * the operations over them should be done using 8 bits operations.
 109  */
 110 #define MC_ME_PCTLn_RUNPCm(n)                   ( (n) & MC_ME_PCTLn_RUNPCm_MASK )
 111 #define MC_ME_PCTLn_RUNPCm_MASK                 (0x7)
 112
 113 /* DEC200 Peripheral Control Register           */
 114 #define MC_ME_PCTL39    (MC_ME_BASE_ADDR + 0x000000E4)
 115 /* 2D-ACE Peripheral Control Register           */
 116 #define MC_ME_PCTL40    (MC_ME_BASE_ADDR + 0x000000EB)
 117 /* ENET Peripheral Control Register             */
 118 #define MC_ME_PCTL50    (MC_ME_BASE_ADDR + 0x000000F1)
 119 /* DMACHMUX0 Peripheral Control Register        */
 120 #define MC_ME_PCTL49    (MC_ME_BASE_ADDR + 0x000000F2)
 121 /* CSI0 Peripheral Control Register                     */
 122 #define MC_ME_PCTL48    (MC_ME_BASE_ADDR + 0x000000F3)
 123 /* MMDC0 Peripheral Control Register            */
 124 #define MC_ME_PCTL54    (MC_ME_BASE_ADDR + 0x000000F5)
 125 /* FRAY Peripheral Control Register                     */
 126 #define MC_ME_PCTL52    (MC_ME_BASE_ADDR + 0x000000F7)
 127 /* PIT0 Peripheral Control Register                     */
 128 #define MC_ME_PCTL58    (MC_ME_BASE_ADDR + 0x000000F9)
 129 /* FlexTIMER0 Peripheral Control Register       */
 130 #define MC_ME_PCTL79    (MC_ME_BASE_ADDR + 0x0000010C)
 131 /* SARADC0 Peripheral Control Register          */
 132 #define MC_ME_PCTL77    (MC_ME_BASE_ADDR + 0x0000010E)
 133 /* LINFLEX0 Peripheral Control Register         */
 134 #define MC_ME_PCTL83    (MC_ME_BASE_ADDR + 0x00000110)
 135 /* IIC0 Peripheral Control Register                     */
 136 #define MC_ME_PCTL81    (MC_ME_BASE_ADDR + 0x00000112)
 137 /* DSPI0 Peripheral Control Register            */
 138 #define MC_ME_PCTL87    (MC_ME_BASE_ADDR + 0x00000114)
 139 /* CANFD0 Peripheral Control Register           */
 140 #define MC_ME_PCTL85    (MC_ME_BASE_ADDR + 0x00000116)
 141 /* CRC0 Peripheral Control Register                     */
 142 #define MC_ME_PCTL91    (MC_ME_BASE_ADDR + 0x00000118)
 143 /* DSPI2 Peripheral Control Register            */
 144 #define MC_ME_PCTL89    (MC_ME_BASE_ADDR + 0x0000011A)
 145 /* SDHC Peripheral Control Register                     */
 146 #define MC_ME_PCTL93    (MC_ME_BASE_ADDR + 0x0000011E)
 147 /* VIU0 Peripheral Control Register                     */
 148 #define MC_ME_PCTL100   (MC_ME_BASE_ADDR + 0x00000127)
 149 /* HPSMI Peripheral Control Register            */
 150 #define MC_ME_PCTL104   (MC_ME_BASE_ADDR + 0x0000012B)
 151 /* SIPI Peripheral Control Register                     */
 152 #define MC_ME_PCTL116   (MC_ME_BASE_ADDR + 0x00000137)
 153 /* LFAST Peripheral Control Register            */
 154 #define MC_ME_PCTL120   (MC_ME_BASE_ADDR + 0x0000013B)
 155 /* MMDC1 Peripheral Control Register            */
 156 #define MC_ME_PCTL162   (MC_ME_BASE_ADDR + 0x00000161)
 157 /* DMACHMUX1 Peripheral Control Register        */
 158 #define MC_ME_PCTL161   (MC_ME_BASE_ADDR + 0x00000162)
 159 /* CSI1 Peripheral Control Register                     */
 160 #define MC_ME_PCTL160   (MC_ME_BASE_ADDR + 0x00000163)
 161 /* QUADSPI0 Peripheral Control Register         */
 162 #define MC_ME_PCTL166   (MC_ME_BASE_ADDR + 0x00000165)
 163 /* PIT1 Peripheral Control Register                     */
 164 #define MC_ME_PCTL170   (MC_ME_BASE_ADDR + 0x00000169)
 165 /* FlexTIMER1 Peripheral Control Register       */
 166 #define MC_ME_PCTL182   (MC_ME_BASE_ADDR + 0x00000175)
 167 /* IIC2 Peripheral Control Register                     */
 168 #define MC_ME_PCTL186   (MC_ME_BASE_ADDR + 0x00000179)
 169 /* IIC1 Peripheral Control Register                     */
 170 #define MC_ME_PCTL184   (MC_ME_BASE_ADDR + 0x0000017B)
 171 /* CANFD1 Peripheral Control Register           */
 172 #define MC_ME_PCTL190   (MC_ME_BASE_ADDR + 0x0000017D)
 173 /* LINFLEX1 Peripheral Control Register         */
 174 #define MC_ME_PCTL188   (MC_ME_BASE_ADDR + 0x0000017F)
 175 /* DSPI3 Peripheral Control Register            */
 176 #define MC_ME_PCTL194   (MC_ME_BASE_ADDR + 0x00000181)
 177 /* DSPI1 Peripheral Control Register            */
 178 #define MC_ME_PCTL192   (MC_ME_BASE_ADDR + 0x00000183)
 179 /* TSENS Peripheral Control Register            */
 180 #define MC_ME_PCTL206   (MC_ME_BASE_ADDR + 0x0000018D)
 181 /* CRC1 Peripheral Control Register                     */
 182 #define MC_ME_PCTL204   (MC_ME_BASE_ADDR + 0x0000018F)
 183 /* VIU1 Peripheral Control Register             */
 184 #define MC_ME_PCTL208   (MC_ME_BASE_ADDR + 0x00000193)
 185 /* JPEG Peripheral Control Register             */
 186 #define MC_ME_PCTL212   (MC_ME_BASE_ADDR + 0x00000197)
 187 /* H264_DEC Peripheral Control Register */
 188 #define MC_ME_PCTL216   (MC_ME_BASE_ADDR + 0x0000019B)
 189 /* H264_ENC Peripheral Control Register */
 190 #define MC_ME_PCTL220   (MC_ME_BASE_ADDR + 0x0000019F)
 191 /* MBIST Peripheral Control Register    */
 192 #define MC_ME_PCTL236   (MC_ME_BASE_ADDR + 0x000001A9)
 193
 194 /* Core status register */
 195 #define MC_ME_CS               (MC_ME_BASE_ADDR + 0x000001C0)
 196
 197 #endif
 198
 199 #endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */