arch/arm/include/asm/imx-common/iomux-v3.h

   1 /*
   2  * Based on Linux i.MX iomux-v3.h file:
   3  * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
   4  *                      <armlinux@phytec.de>
   5  *
   6  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __MACH_IOMUX_V3_H__
  12 #define __MACH_IOMUX_V3_H__
  13
  14 #include <common.h>
  15
  16 /*
  17  *      build IOMUX_PAD structure
  18  *
  19  * This iomux scheme is based around pads, which are the physical balls
  20  * on the processor.
  21  *
  22  * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
  23  *   things like driving strength and pullup/pulldown.
  24  * - Each pad can have but not necessarily does have an output routing register
  25  *   (IOMUXC_SW_MUX_CTL_PAD_x).
  26  * - Each pad can have but not necessarily does have an input routing register
  27  *   (IOMUXC_x_SELECT_INPUT)
  28  *
  29  * The three register sets do not have a fixed offset to each other,
  30  * hence we order this table by pad control registers (which all pads
  31  * have) and put the optional i/o routing registers into additional
  32  * fields.
  33  *
  34  * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
  35  * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
  36  *
  37  * IOMUX/PAD Bit field definitions
  38  *
  39  * MUX_CTRL_OFS:            0..11 (12)
  40  * PAD_CTRL_OFS:           12..23 (12)
  41  * SEL_INPUT_OFS:          24..35 (12)
  42  * MUX_MODE + SION:        36..40  (5)
  43  * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
  44  * SEL_INP:                59..62  (4)
  45  * reserved:                 63    (1)
  46 */
  47
  48 typedef u64 iomux_v3_cfg_t;
  49
  50 #define MUX_CTRL_OFS_SHIFT      0
  51 #define MUX_CTRL_OFS_MASK       ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
  52 #define MUX_PAD_CTRL_OFS_SHIFT  12
  53 #define MUX_PAD_CTRL_OFS_MASK   ((iomux_v3_cfg_t)0xfff << \
  54         MUX_PAD_CTRL_OFS_SHIFT)
  55 #define MUX_SEL_INPUT_OFS_SHIFT 24
  56 #define MUX_SEL_INPUT_OFS_MASK  ((iomux_v3_cfg_t)0xfff << \
  57         MUX_SEL_INPUT_OFS_SHIFT)
  58
  59 #define MUX_MODE_SHIFT          36
  60 #define MUX_MODE_MASK           ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
  61 #define MUX_PAD_CTRL_SHIFT      41
  62 #define MUX_PAD_CTRL_MASK       ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
  63 #define MUX_SEL_INPUT_SHIFT     59
  64 #define MUX_SEL_INPUT_MASK      ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
  65
  66 #define MUX_MODE_SION           ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
  67         MUX_MODE_SHIFT)
  68 #define MUX_PAD_CTRL(x)         ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
  69
  70 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,  \
  71                 sel_input, pad_ctrl)                                    \
  72         (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT)     |   \
  73         ((iomux_v3_cfg_t)(mux_mode)      << MUX_MODE_SHIFT)         |   \
  74         ((iomux_v3_cfg_t)(pad_ctrl_ofs)  << MUX_PAD_CTRL_OFS_SHIFT) |   \
  75         ((iomux_v3_cfg_t)(pad_ctrl)      << MUX_PAD_CTRL_SHIFT)     |   \
  76         ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)|   \
  77         ((iomux_v3_cfg_t)(sel_input)     << MUX_SEL_INPUT_SHIFT))
  78
  79 #define NEW_PAD_CTRL(cfg, pad)  (((cfg) & ~MUX_PAD_CTRL_MASK) | \
  80                                         MUX_PAD_CTRL(pad))
  81
  82 #define __NA_                   0x000
  83 #define NO_MUX_I                0
  84 #define NO_PAD_I                0
  85
  86 #define NO_PAD_CTRL             (1 << 17)
  87
  88 #ifdef CONFIG_MX6
  89
  90 #define PAD_CTL_HYS             (1 << 16)
  91
  92 #define PAD_CTL_PUS_100K_DOWN   (0 << 14 | PAD_CTL_PUE)
  93 #define PAD_CTL_PUS_47K_UP      (1 << 14 | PAD_CTL_PUE)
  94 #define PAD_CTL_PUS_100K_UP     (2 << 14 | PAD_CTL_PUE)
  95 #define PAD_CTL_PUS_22K_UP      (3 << 14 | PAD_CTL_PUE)
  96 #define PAD_CTL_PUE             (1 << 13 | PAD_CTL_PKE)
  97 #define PAD_CTL_PKE             (1 << 12)
  98
  99 #define PAD_CTL_ODE             (1 << 11)
 100
 101 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
 102 #define PAD_CTL_SPEED_LOW       (0 << 6)
 103 #else
 104 #define PAD_CTL_SPEED_LOW       (1 << 6)
 105 #endif
 106 #define PAD_CTL_SPEED_MED       (2 << 6)
 107 #define PAD_CTL_SPEED_HIGH      (3 << 6)
 108
 109 #define PAD_CTL_DSE_DISABLE     (0 << 3)
 110 #define PAD_CTL_DSE_240ohm      (1 << 3)
 111 #define PAD_CTL_DSE_120ohm      (2 << 3)
 112 #define PAD_CTL_DSE_80ohm       (3 << 3)
 113 #define PAD_CTL_DSE_60ohm       (4 << 3)
 114 #define PAD_CTL_DSE_48ohm       (5 << 3)
 115 #define PAD_CTL_DSE_40ohm       (6 << 3)
 116 #define PAD_CTL_DSE_34ohm       (7 << 3)
 117
 118 #if defined CONFIG_MX6SL
 119 #define PAD_CTL_LVE             (1 << 1)
 120 #define PAD_CTL_LVE_BIT         (1 << 22)
 121 #endif
 122
 123 #elif defined(CONFIG_VF610)
 124
 125 #define PAD_MUX_MODE_SHIFT      20
 126
 127 #define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
 128
 129 #define PAD_CTL_SPEED_MED       (1 << 12)
 130 #define PAD_CTL_SPEED_HIGH      (3 << 12)
 131
 132 #define PAD_CTL_SRE             (1 << 11)
 133
 134 #define PAD_CTL_ODE             (1 << 10)
 135
 136 #define PAD_CTL_DSE_150ohm      (1 << 6)
 137 #define PAD_CTL_DSE_50ohm       (3 << 6)
 138 #define PAD_CTL_DSE_25ohm       (6 << 6)
 139 #define PAD_CTL_DSE_20ohm       (7 << 6)
 140
 141 #define PAD_CTL_PUS_47K_UP      (1 << 4 | PAD_CTL_PUE)
 142 #define PAD_CTL_PUS_100K_UP     (2 << 4 | PAD_CTL_PUE)
 143 #define PAD_CTL_PUS_22K_UP      (3 << 4 | PAD_CTL_PUE)
 144 #define PAD_CTL_PKE             (1 << 3)
 145 #define PAD_CTL_PUE             (1 << 2 | PAD_CTL_PKE)
 146
 147 #define PAD_CTL_OBE_IBE_ENABLE  (3 << 0)
 148 #define PAD_CTL_OBE_ENABLE      (1 << 1)
 149 #define PAD_CTL_IBE_ENABLE      (1 << 0)
 150
 151 #else
 152
 153 #define PAD_CTL_DVS             (1 << 13)
 154 #define PAD_CTL_INPUT_DDR       (1 << 9)
 155 #define PAD_CTL_HYS             (1 << 8)
 156
 157 #define PAD_CTL_PKE             (1 << 7)
 158 #define PAD_CTL_PUE             (1 << 6 | PAD_CTL_PKE)
 159 #define PAD_CTL_PUS_100K_DOWN   (0 << 4 | PAD_CTL_PUE)
 160 #define PAD_CTL_PUS_47K_UP      (1 << 4 | PAD_CTL_PUE)
 161 #define PAD_CTL_PUS_100K_UP     (2 << 4 | PAD_CTL_PUE)
 162 #define PAD_CTL_PUS_22K_UP      (3 << 4 | PAD_CTL_PUE)
 163
 164 #define PAD_CTL_ODE             (1 << 3)
 165
 166 #define PAD_CTL_DSE_LOW         (0 << 1)
 167 #define PAD_CTL_DSE_MED         (1 << 1)
 168 #define PAD_CTL_DSE_HIGH        (2 << 1)
 169 #define PAD_CTL_DSE_MAX         (3 << 1)
 170
 171 #endif
 172
 173 #define PAD_CTL_SRE_SLOW        (0 << 0)
 174 #define PAD_CTL_SRE_FAST        (1 << 0)
 175
 176 #define IOMUX_CONFIG_SION       0x10
 177
 178 #define GPIO_PIN_MASK           0x1f
 179 #define GPIO_PORT_SHIFT         5
 180 #define GPIO_PORT_MASK          (0x7 << GPIO_PORT_SHIFT)
 181 #define GPIO_PORTA              (0 << GPIO_PORT_SHIFT)
 182 #define GPIO_PORTB              (1 << GPIO_PORT_SHIFT)
 183 #define GPIO_PORTC              (2 << GPIO_PORT_SHIFT)
 184 #define GPIO_PORTD              (3 << GPIO_PORT_SHIFT)
 185 #define GPIO_PORTE              (4 << GPIO_PORT_SHIFT)
 186 #define GPIO_PORTF              (5 << GPIO_PORT_SHIFT)
 187
 188 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 189 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 190                                      unsigned count);
 191 /*
 192 * Set bits for general purpose registers
 193 */
 194 void imx_iomux_set_gpr_register(int group, int start_bit,
 195                                          int num_bits, int value);
 196 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
 197 void imx_iomux_gpio_set_direction(unsigned int gpio,
 198                                 unsigned int direction);
 199 void imx_iomux_gpio_get_function(unsigned int gpio,
 200                                 u32 *gpio_state);
 201 #endif
 202
 203 /* macros for declaring and using pinmux array */
 204 #if defined(CONFIG_MX6QDL)
 205 #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
 206 #define SETUP_IOMUX_PAD(def)                                    \
 207 if (is_cpu_type(MXC_CPU_MX6Q)) {                                \
 208         imx_iomux_v3_setup_pad(MX6Q_##def);                     \
 209 } else {                                                        \
 210         imx_iomux_v3_setup_pad(MX6DL_##def);                    \
 211 }
 212 #define SETUP_IOMUX_PADS(x)                                     \
 213         imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
 214 #elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 215 #define IOMUX_PADS(x) MX6Q_##x
 216 #define SETUP_IOMUX_PAD(def)                                    \
 217         imx_iomux_v3_setup_pad(MX6Q_##def);
 218 #define SETUP_IOMUX_PADS(x)                                     \
 219         imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
 220 #else
 221 #define IOMUX_PADS(x) MX6DL_##x
 222 #define SETUP_IOMUX_PAD(def)                                    \
 223         imx_iomux_v3_setup_pad(MX6DL_##def);
 224 #define SETUP_IOMUX_PADS(x)                                     \
 225         imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
 226 #endif
 227
 228 #endif  /* __MACH_IOMUX_V3_H__*/