arch/arm/include/asm/system.h

   1 #ifndef __ASM_ARM_SYSTEM_H
   2 #define __ASM_ARM_SYSTEM_H
   3
   4 #ifdef CONFIG_ARM64
   5
   6 /*
   7  * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
   8  */
   9 #define CR_M            (1 << 0)        /* MMU enable                   */
  10 #define CR_A            (1 << 1)        /* Alignment abort enable       */
  11 #define CR_C            (1 << 2)        /* Dcache enable                */
  12 #define CR_SA           (1 << 3)        /* Stack Alignment Check Enable */
  13 #define CR_I            (1 << 12)       /* Icache enable                */
  14 #define CR_WXN          (1 << 19)       /* Write Permision Imply XN     */
  15 #define CR_EE           (1 << 25)       /* Exception (Big) Endian       */
  16
  17 #ifndef CONFIG_SYS_FULL_VA
  18 #define PGTABLE_SIZE    (0x10000)
  19 #else
  20 #define PGTABLE_SIZE    CONFIG_SYS_PGTABLE_SIZE
  21 #endif
  22
  23 /* 2MB granularity */
  24 #define MMU_SECTION_SHIFT       21
  25 #define MMU_SECTION_SIZE        (1 << MMU_SECTION_SHIFT)
  26
  27 #ifndef __ASSEMBLY__
  28
  29 enum dcache_option {
  30         DCACHE_OFF = 0x3,
  31 };
  32
  33 #define isb()                           \
  34         ({asm volatile(                 \
  35         "isb" : : : "memory");          \
  36         })
  37
  38 #define wfi()                           \
  39         ({asm volatile(                 \
  40         "wfi" : : : "memory");          \
  41         })
  42
  43 static inline unsigned int current_el(void)
  44 {
  45         unsigned int el;
  46         asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
  47         return el >> 2;
  48 }
  49
  50 static inline unsigned int get_sctlr(void)
  51 {
  52         unsigned int el, val;
  53
  54         el = current_el();
  55         if (el == 1)
  56                 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
  57         else if (el == 2)
  58                 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
  59         else
  60                 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
  61
  62         return val;
  63 }
  64
  65 static inline void set_sctlr(unsigned int val)
  66 {
  67         unsigned int el;
  68
  69         el = current_el();
  70         if (el == 1)
  71                 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
  72         else if (el == 2)
  73                 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
  74         else
  75                 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
  76
  77         asm volatile("isb");
  78 }
  79
  80 static inline unsigned long read_mpidr(void)
  81 {
  82         unsigned long val;
  83
  84         asm volatile("mrs %0, mpidr_el1" : "=r" (val));
  85
  86         return val;
  87 }
  88
  89 #define BSP_COREID      0
  90
  91 void __asm_flush_dcache_all(void);
  92 void __asm_invalidate_dcache_all(void);
  93 void __asm_flush_dcache_range(u64 start, u64 end);
  94 void __asm_invalidate_tlb_all(void);
  95 void __asm_invalidate_icache_all(void);
  96 int __asm_flush_l3_cache(void);
  97
  98 void armv8_switch_to_el2(void);
  99 void armv8_switch_to_el1(void);
 100 void gic_init(void);
 101 void gic_send_sgi(unsigned long sgino);
 102 void wait_for_wakeup(void);
 103 void protect_secure_region(void);
 104 void smp_kick_all_cpus(void);
 105
 106 void flush_l3_cache(void);
 107
 108 #endif  /* __ASSEMBLY__ */
 109
 110 #else /* CONFIG_ARM64 */
 111
 112 #ifdef __KERNEL__
 113
 114 #define CPU_ARCH_UNKNOWN        0
 115 #define CPU_ARCH_ARMv3          1
 116 #define CPU_ARCH_ARMv4          2
 117 #define CPU_ARCH_ARMv4T         3
 118 #define CPU_ARCH_ARMv5          4
 119 #define CPU_ARCH_ARMv5T         5
 120 #define CPU_ARCH_ARMv5TE        6
 121 #define CPU_ARCH_ARMv5TEJ       7
 122 #define CPU_ARCH_ARMv6          8
 123 #define CPU_ARCH_ARMv7          9
 124
 125 /*
 126  * CR1 bits (CP#15 CR1)
 127  */
 128 #define CR_M    (1 << 0)        /* MMU enable                           */
 129 #define CR_A    (1 << 1)        /* Alignment abort enable               */
 130 #define CR_C    (1 << 2)        /* Dcache enable                        */
 131 #define CR_W    (1 << 3)        /* Write buffer enable                  */
 132 #define CR_P    (1 << 4)        /* 32-bit exception handler             */
 133 #define CR_D    (1 << 5)        /* 32-bit data address range            */
 134 #define CR_L    (1 << 6)        /* Implementation defined               */
 135 #define CR_B    (1 << 7)        /* Big endian                           */
 136 #define CR_S    (1 << 8)        /* System MMU protection                */
 137 #define CR_R    (1 << 9)        /* ROM MMU protection                   */
 138 #define CR_F    (1 << 10)       /* Implementation defined               */
 139 #define CR_Z    (1 << 11)       /* Implementation defined               */
 140 #define CR_I    (1 << 12)       /* Icache enable                        */
 141 #define CR_V    (1 << 13)       /* Vectors relocated to 0xffff0000      */
 142 #define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
 143 #define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
 144 #define CR_DT   (1 << 16)
 145 #define CR_IT   (1 << 18)
 146 #define CR_ST   (1 << 19)
 147 #define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
 148 #define CR_U    (1 << 22)       /* Unaligned access operation           */
 149 #define CR_XP   (1 << 23)       /* Extended page tables                 */
 150 #define CR_VE   (1 << 24)       /* Vectored interrupts                  */
 151 #define CR_EE   (1 << 25)       /* Exception (Big) Endian               */
 152 #define CR_TRE  (1 << 28)       /* TEX remap enable                     */
 153 #define CR_AFE  (1 << 29)       /* Access flag enable                   */
 154 #define CR_TE   (1 << 30)       /* Thumb exception enable               */
 155
 156 #ifndef PGTABLE_SIZE
 157 #define PGTABLE_SIZE            (4096 * 4)
 158 #endif
 159
 160 /*
 161  * This is used to ensure the compiler did actually allocate the register we
 162  * asked it for some inline assembly sequences.  Apparently we can't trust
 163  * the compiler from one version to another so a bit of paranoia won't hurt.
 164  * This string is meant to be concatenated with the inline asm string and
 165  * will cause compilation to stop on mismatch.
 166  * (for details, see gcc PR 15089)
 167  */
 168 #define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
 169
 170 #ifndef __ASSEMBLY__
 171
 172 /**
 173  * save_boot_params() - Save boot parameters before starting reset sequence
 174  *
 175  * If you provide this function it will be called immediately U-Boot starts,
 176  * both for SPL and U-Boot proper.
 177  *
 178  * All registers are unchanged from U-Boot entry. No registers need be
 179  * preserved.
 180  *
 181  * This is not a normal C function. There is no stack. Return by branching to
 182  * save_boot_params_ret.
 183  *
 184  * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
 185  */
 186
 187 /**
 188  * save_boot_params_ret() - Return from save_boot_params()
 189  *
 190  * If you provide save_boot_params(), then you should jump back to this
 191  * function when done. Try to preserve all registers.
 192  *
 193  * If your implementation of save_boot_params() is in C then it is acceptable
 194  * to simply call save_boot_params_ret() at the end of your function. Since
 195  * there is no link register set up, you cannot just exit the function. U-Boot
 196  * will return to the (initialised) value of lr, and likely crash/hang.
 197  *
 198  * If your implementation of save_boot_params() is in assembler then you
 199  * should use 'b' or 'bx' to return to save_boot_params_ret.
 200  */
 201 void save_boot_params_ret(void);
 202
 203 #define isb() __asm__ __volatile__ ("" : : : "memory")
 204
 205 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 206
 207 #ifdef __ARM_ARCH_7A__
 208 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
 209 #else
 210 #define wfi()
 211 #endif
 212
 213 static inline unsigned int get_cr(void)
 214 {
 215         unsigned int val;
 216         asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
 217         return val;
 218 }
 219
 220 static inline void set_cr(unsigned int val)
 221 {
 222         asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
 223           : : "r" (val) : "cc");
 224         isb();
 225 }
 226
 227 static inline unsigned int get_dacr(void)
 228 {
 229         unsigned int val;
 230         asm("mrc p15, 0, %0, c3, c0, 0  @ get DACR" : "=r" (val) : : "cc");
 231         return val;
 232 }
 233
 234 static inline void set_dacr(unsigned int val)
 235 {
 236         asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
 237           : : "r" (val) : "cc");
 238         isb();
 239 }
 240
 241 #ifdef CONFIG_ARMV7
 242 /* Short-Descriptor Translation Table Level 1 Bits */
 243 #define TTB_SECT_NS_MASK        (1 << 19)
 244 #define TTB_SECT_NG_MASK        (1 << 17)
 245 #define TTB_SECT_S_MASK         (1 << 16)
 246 /* Note: TTB AP bits are set elsewhere */
 247 #define TTB_SECT_TEX(x)         ((x & 0x7) << 12)
 248 #define TTB_SECT_DOMAIN(x)      ((x & 0xf) << 5)
 249 #define TTB_SECT_XN_MASK        (1 << 4)
 250 #define TTB_SECT_C_MASK         (1 << 3)
 251 #define TTB_SECT_B_MASK         (1 << 2)
 252 #define TTB_SECT                        (2 << 0)
 253
 254 /* options available for data cache on each page */
 255 enum dcache_option {
 256         DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
 257                                         TTB_SECT_XN_MASK | TTB_SECT,
 258         DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
 259         DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
 260         DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
 261 };
 262 #else
 263 /* options available for data cache on each page */
 264 enum dcache_option {
 265         DCACHE_OFF = 0x12,
 266         DCACHE_WRITETHROUGH = 0x1a,
 267         DCACHE_WRITEBACK = 0x1e,
 268         DCACHE_WRITEALLOC = 0x16,
 269 };
 270 #endif
 271
 272 /* Size of an MMU section */
 273 enum {
 274         MMU_SECTION_SHIFT       = 20,
 275         MMU_SECTION_SIZE        = 1 << MMU_SECTION_SHIFT,
 276 };
 277
 278 #ifdef CONFIG_ARMV7
 279 /* TTBR0 bits */
 280 #define TTBR0_BASE_ADDR_MASK    0xFFFFC000
 281 #define TTBR0_RGN_NC                    (0 << 3)
 282 #define TTBR0_RGN_WBWA                  (1 << 3)
 283 #define TTBR0_RGN_WT                    (2 << 3)
 284 #define TTBR0_RGN_WB                    (3 << 3)
 285 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
 286 #define TTBR0_IRGN_NC                   (0 << 0 | 0 << 6)
 287 #define TTBR0_IRGN_WBWA                 (0 << 0 | 1 << 6)
 288 #define TTBR0_IRGN_WT                   (1 << 0 | 0 << 6)
 289 #define TTBR0_IRGN_WB                   (1 << 0 | 1 << 6)
 290 #endif
 291
 292 /**
 293  * Register an update to the page tables, and flush the TLB
 294  *
 295  * \param start         start address of update in page table
 296  * \param stop          stop address of update in page table
 297  */
 298 void mmu_page_table_flush(unsigned long start, unsigned long stop);
 299
 300 #endif /* __ASSEMBLY__ */
 301
 302 #define arch_align_stack(x) (x)
 303
 304 #endif /* __KERNEL__ */
 305
 306 #endif /* CONFIG_ARM64 */
 307
 308 #ifndef __ASSEMBLY__
 309 /**
 310  * Change the cache settings for a region.
 311  *
 312  * \param start         start address of memory region to change
 313  * \param size          size of memory region to change
 314  * \param option        dcache option to select
 315  */
 316 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 317                                      enum dcache_option option);
 318
 319 #ifdef CONFIG_SYS_NONCACHED_MEMORY
 320 void noncached_init(void);
 321 phys_addr_t noncached_alloc(size_t size, size_t align);
 322 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
 323
 324 #endif /* __ASSEMBLY__ */
 325
 326 #endif