2 * Copyright (C) 2012-2020 ASPEED Technology Inc.
4 * Copyright 2016 Google, Inc
6 * SPDX-License-Identifier: GPL-2.0
16 #include <asm/arch/scu_ast2500.h>
17 #include <asm/arch/sdram_ast2500.h>
18 #include <asm/arch/wdt.h>
19 #include <linux/err.h>
20 #include <linux/kernel.h>
21 #include <dt-bindings/clock/ast2500-scu.h>
23 /* These configuration parameters are taken from Aspeed SDK */
24 #define DDR4_MR46_MODE 0x08000000
25 #define DDR4_MR5_MODE 0x400
26 #define DDR4_MR13_MODE 0x101
27 #define DDR4_MR02_MODE 0x410
28 #define DDR4_TRFC 0x45457188
30 #define PHY_CFG_SIZE 15
32 static const u32 ddr4_ac_timing
[3] = {0x63604e37, 0xe97afa99, 0x00019000};
34 u32 index
[PHY_CFG_SIZE
];
35 u32 value
[PHY_CFG_SIZE
];
37 .index
= {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50},
39 0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24,
40 0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607,
41 0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e,
45 #define SDRAM_MAX_SIZE (1024 * 1024 * 1024)
46 #define SDRAM_MIN_SIZE (128 * 1024 * 1024)
48 DECLARE_GLOBAL_DATA_PTR
;
51 * Bandwidth configuration parameters for different SDRAM requests.
52 * These are hardcoded settings taken from Aspeed SDK.
54 static const u32 ddr_max_grant_params
[4] = {
55 0x88448844, 0x24422288, 0x22222222, 0x22222222
59 * These registers are not documented by Aspeed at all.
60 * All writes and reads are taken pretty much as is from SDK.
62 struct ast2500_ddr_phy
{
69 struct ast2500_sdrammc_regs
*regs
;
70 struct ast2500_scu
*scu
;
71 struct ast2500_ddr_phy
*phy
;
75 static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy
*phy
)
77 writel(0, &phy
->phy
[2]);
78 writel(0, &phy
->phy
[6]);
79 writel(0, &phy
->phy
[8]);
80 writel(0, &phy
->phy
[10]);
81 writel(0, &phy
->phy
[12]);
82 writel(0, &phy
->phy
[42]);
83 writel(0, &phy
->phy
[44]);
85 writel(0x86000000, &phy
->phy
[16]);
86 writel(0x00008600, &phy
->phy
[17]);
87 writel(0x80000000, &phy
->phy
[18]);
88 writel(0x80808080, &phy
->phy
[19]);
93 static void ast2500_ddr_phy_init_process(struct dram_info
*info
)
95 struct ast2500_sdrammc_regs
*regs
= info
->regs
;
97 writel(0, ®s
->phy_ctrl
[0]);
98 writel(0x4040, &info
->phy
->phy
[51]);
100 writel(SDRAM_PHYCTRL0_NRST
| SDRAM_PHYCTRL0_INIT
, ®s
->phy_ctrl
[0]);
101 while ((readl(®s
->phy_ctrl
[0]) & SDRAM_PHYCTRL0_INIT
))
103 writel(SDRAM_PHYCTRL0_NRST
| SDRAM_PHYCTRL0_AUTO_UPDATE
,
107 static void ast2500_sdrammc_set_vref(struct dram_info
*info
, u32 vref
)
109 writel(0, &info
->regs
->phy_ctrl
[0]);
110 writel((vref
<< 8) | 0x6, &info
->phy
->phy
[48]);
111 ast2500_ddr_phy_init_process(info
);
114 static int ast2500_ddr_cbr_test(struct dram_info
*info
)
116 struct ast2500_sdrammc_regs
*regs
= info
->regs
;
118 const u32 test_params
= SDRAM_TEST_EN
120 | SDRAM_TEST_TWO_MODES
;
123 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT
) |
124 (0x5c << SDRAM_REFRESH_PERIOD_SHIFT
), ®s
->refresh_timing
);
125 writel((0xfff << SDRAM_TEST_LEN_SHIFT
), ®s
->test_addr
);
126 writel(0xff00ff00, ®s
->test_init_val
);
127 writel(SDRAM_TEST_EN
| (SDRAM_TEST_MODE_RW
<< SDRAM_TEST_MODE_SHIFT
) |
128 SDRAM_TEST_ERRSTOP
, ®s
->ecc_test_ctrl
);
130 while (!(readl(®s
->ecc_test_ctrl
) & SDRAM_TEST_DONE
))
133 if (readl(®s
->ecc_test_ctrl
) & SDRAM_TEST_FAIL
) {
136 for (i
= 0; i
<= SDRAM_TEST_GEN_MODE_MASK
; ++i
) {
137 writel((i
<< SDRAM_TEST_GEN_MODE_SHIFT
) | test_params
,
138 ®s
->ecc_test_ctrl
);
139 while (!(readl(®s
->ecc_test_ctrl
) & SDRAM_TEST_DONE
))
141 if (readl(®s
->ecc_test_ctrl
) & SDRAM_TEST_FAIL
) {
148 writel(0, ®s
->refresh_timing
);
149 writel(0, ®s
->ecc_test_ctrl
);
154 static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info
*info
)
161 for (i
= 1; i
< 0x40; ++i
) {
164 ast2500_sdrammc_set_vref(info
, i
);
165 res
= ast2500_ddr_cbr_test(info
);
171 vref_min
= min(vref_min
, i
);
172 vref_max
= max(vref_max
, i
);
176 /* Pick average setting */
177 ast2500_sdrammc_set_vref(info
, (vref_min
+ vref_max
+ 1) / 2);
182 static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info
*info
)
184 size_t vga_mem_size_base
= 8 * 1024 * 1024;
185 u32 vga_hwconf
= (readl(&info
->scu
->hwstrap
)
186 >> SCU_HWSTRAP_VGAMEM_SHIFT
)
187 & SCU_HWSTRAP_VGAMEM_MASK
;
189 return vga_mem_size_base
<< vga_hwconf
;
193 * Find out RAM size and save it in dram_info
195 * The procedure is taken from Aspeed SDK
197 static void ast2500_sdrammc_calc_size(struct dram_info
*info
)
199 /* The controller supports 128/256/512/1024 MB ram */
200 size_t ram_size
= SDRAM_MIN_SIZE
;
201 const int write_test_offset
= 0x100000;
202 u32 test_pattern
= 0xdeadbeef;
203 u32 cap_param
= SDRAM_CONF_CAP_1024M
;
204 u32 refresh_timing_param
= DDR4_TRFC
;
205 const u32 write_addr_base
= CONFIG_SYS_SDRAM_BASE
+ write_test_offset
;
207 for (ram_size
= SDRAM_MAX_SIZE
; ram_size
> SDRAM_MIN_SIZE
;
209 writel(test_pattern
, write_addr_base
+ (ram_size
>> 1));
210 test_pattern
= (test_pattern
>> 4) | (test_pattern
<< 28);
213 /* One last write to overwrite all wrapped values */
214 writel(test_pattern
, write_addr_base
);
216 /* Reset the pattern and see which value was really written */
217 test_pattern
= 0xdeadbeef;
218 for (ram_size
= SDRAM_MAX_SIZE
; ram_size
> SDRAM_MIN_SIZE
;
220 if (readl(write_addr_base
+ (ram_size
>> 1)) == test_pattern
)
224 refresh_timing_param
>>= 8;
225 test_pattern
= (test_pattern
>> 4) | (test_pattern
<< 28);
228 clrsetbits_le32(&info
->regs
->ac_timing
[1],
229 (SDRAM_AC_TRFC_MASK
<< SDRAM_AC_TRFC_SHIFT
),
230 ((refresh_timing_param
& SDRAM_AC_TRFC_MASK
)
231 << SDRAM_AC_TRFC_SHIFT
));
233 info
->info
.base
= CONFIG_SYS_SDRAM_BASE
;
234 info
->info
.size
= ram_size
- ast2500_sdrammc_get_vga_mem_size(info
);
235 clrsetbits_le32(&info
->regs
->config
,
236 (SDRAM_CONF_CAP_MASK
<< SDRAM_CONF_CAP_SHIFT
),
237 ((cap_param
& SDRAM_CONF_CAP_MASK
)
238 << SDRAM_CONF_CAP_SHIFT
));
241 static int ast2500_sdrammc_init_ddr4(struct dram_info
*info
)
244 const u32 power_control
= SDRAM_PCR_CKE_EN
245 | (1 << SDRAM_PCR_CKE_DELAY_SHIFT
)
246 | (2 << SDRAM_PCR_TCKE_PW_SHIFT
)
247 | SDRAM_PCR_RESETN_DIS
248 | SDRAM_PCR_RGAP_CTRL_EN
| SDRAM_PCR_ODT_EN
| SDRAM_PCR_ODT_EXT_EN
;
249 const u32 conf
= (SDRAM_CONF_CAP_1024M
<< SDRAM_CONF_CAP_SHIFT
)
250 #ifdef CONFIG_DUALX8_RAM
253 | SDRAM_CONF_SCRAMBLE
| SDRAM_CONF_SCRAMBLE_PAT2
| SDRAM_CONF_DDR4
;
256 writel(conf
, &info
->regs
->config
);
257 for (i
= 0; i
< ARRAY_SIZE(ddr4_ac_timing
); ++i
)
258 writel(ddr4_ac_timing
[i
], &info
->regs
->ac_timing
[i
]);
260 writel(DDR4_MR46_MODE
, &info
->regs
->mr46_mode_setting
);
261 writel(DDR4_MR5_MODE
, &info
->regs
->mr5_mode_setting
);
262 writel(DDR4_MR02_MODE
, &info
->regs
->mr02_mode_setting
);
263 writel(DDR4_MR13_MODE
, &info
->regs
->mr13_mode_setting
);
265 for (i
= 0; i
< PHY_CFG_SIZE
; ++i
) {
266 writel(ddr4_phy_config
.value
[i
],
267 &info
->phy
->phy
[ddr4_phy_config
.index
[i
]]);
270 writel(power_control
, &info
->regs
->power_control
);
272 ast2500_ddr_phy_init_process(info
);
274 ret
= ast2500_sdrammc_ddr4_calibrate_vref(info
);
276 debug("Vref calibration failed!\n");
280 writel((1 << SDRAM_REFRESH_CYCLES_SHIFT
)
281 | SDRAM_REFRESH_ZQCS_EN
| (0x2f << SDRAM_REFRESH_PERIOD_SHIFT
),
282 &info
->regs
->refresh_timing
);
284 setbits_le32(&info
->regs
->power_control
,
285 SDRAM_PCR_AUTOPWRDN_EN
| SDRAM_PCR_ODT_AUTO_ON
);
287 ast2500_sdrammc_calc_size(info
);
289 setbits_le32(&info
->regs
->config
, SDRAM_CONF_CACHE_INIT_EN
);
290 while (!(readl(&info
->regs
->config
) & SDRAM_CONF_CACHE_INIT_DONE
))
292 setbits_le32(&info
->regs
->config
, SDRAM_CONF_CACHE_EN
);
294 writel(SDRAM_MISC_DDR4_TREFRESH
, &info
->regs
->misc_control
);
296 /* Enable all requests except video & display */
297 writel(SDRAM_REQ_USB20_EHCI1
298 | SDRAM_REQ_USB20_EHCI2
306 | SDRAM_REQ_ENCRYPTION
307 | SDRAM_REQ_VIDEO_FLAG
308 | SDRAM_REQ_VIDEO_LOW_PRI_WRITE
310 | SDRAM_REQ_MEMCHECK
, &info
->regs
->req_limit_mask
);
315 static void ast2500_sdrammc_unlock(struct dram_info
*info
)
317 writel(SDRAM_UNLOCK_KEY
, &info
->regs
->protection_key
);
318 while (!readl(&info
->regs
->protection_key
))
322 static void ast2500_sdrammc_lock(struct dram_info
*info
)
324 writel(~SDRAM_UNLOCK_KEY
, &info
->regs
->protection_key
);
325 while (readl(&info
->regs
->protection_key
))
329 static int ast2500_sdrammc_probe(struct udevice
*dev
)
331 struct dram_info
*priv
= (struct dram_info
*)dev_get_priv(dev
);
332 struct ast2500_sdrammc_regs
*regs
= priv
->regs
;
334 int ret
= clk_get_by_index(dev
, 0, &priv
->ddr_clk
);
337 debug("DDR:No CLK\n");
341 priv
->scu
= ast_get_scu();
342 if (IS_ERR(priv
->scu
)) {
343 debug("%s(): can't get SCU\n", __func__
);
344 return PTR_ERR(priv
->scu
);
347 clk_set_rate(&priv
->ddr_clk
, priv
->clock_rate
);
348 ret
= ast_wdt_reset_masked(ast_get_wdt(0), WDT_RESET_SDRAM
);
350 debug("%s(): SDRAM reset failed\n", __func__
);
354 ast2500_sdrammc_unlock(priv
);
356 writel(SDRAM_PCR_MREQI_DIS
| SDRAM_PCR_RESETN_DIS
,
357 ®s
->power_control
);
358 writel(SDRAM_VIDEO_UNLOCK_KEY
, ®s
->gm_protection_key
);
360 /* Mask all requests except CPU and AHB during PHY init */
361 writel(~(SDRAM_REQ_CPU
| SDRAM_REQ_AHB
), ®s
->req_limit_mask
);
363 for (i
= 0; i
< ARRAY_SIZE(ddr_max_grant_params
); ++i
)
364 writel(ddr_max_grant_params
[i
], ®s
->max_grant_len
[i
]);
366 setbits_le32(®s
->intr_ctrl
, SDRAM_ICR_RESET_ALL
);
368 ast2500_sdrammc_init_phy(priv
->phy
);
369 if (readl(&priv
->scu
->hwstrap
) & SCU_HWSTRAP_DDR4
) {
370 ast2500_sdrammc_init_ddr4(priv
);
372 debug("Unsupported DRAM3\n");
376 clrbits_le32(®s
->intr_ctrl
, SDRAM_ICR_RESET_ALL
);
377 ast2500_sdrammc_lock(priv
);
382 static int ast2500_sdrammc_ofdata_to_platdata(struct udevice
*dev
)
384 struct dram_info
*priv
= dev_get_priv(dev
);
388 ret
= regmap_init_mem(dev
, &map
);
392 priv
->regs
= regmap_get_range(map
, 0);
393 priv
->phy
= regmap_get_range(map
, 1);
395 priv
->clock_rate
= fdtdec_get_int(gd
->fdt_blob
, dev_of_offset(dev
),
396 "clock-frequency", 0);
398 if (!priv
->clock_rate
) {
399 debug("DDR Clock Rate not defined\n");
406 static int ast2500_sdrammc_get_info(struct udevice
*dev
, struct ram_info
*info
)
408 struct dram_info
*priv
= dev_get_priv(dev
);
415 static struct ram_ops ast2500_sdrammc_ops
= {
416 .get_info
= ast2500_sdrammc_get_info
,
419 static const struct udevice_id ast2500_sdrammc_ids
[] = {
420 { .compatible
= "aspeed,ast2500-sdrammc" },
424 U_BOOT_DRIVER(sdrammc_ast2500
) = {
425 .name
= "aspeed_ast2500_sdrammc",
427 .of_match
= ast2500_sdrammc_ids
,
428 .ops
= &ast2500_sdrammc_ops
,
429 .ofdata_to_platdata
= ast2500_sdrammc_ofdata_to_platdata
,
430 .probe
= ast2500_sdrammc_probe
,
431 .priv_auto_alloc_size
= sizeof(struct dram_info
),