arch/arm/mach-at91/arm926ejs/timer.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/hardware.h>
  12 #include <asm/arch/at91_pit.h>
  13 #include <asm/arch/at91_pmc.h>
  14 #include <asm/arch/clk.h>
  15 #include <div64.h>
  16
  17 #if !defined(CONFIG_AT91FAMILY)
  18 # error You need to define CONFIG_AT91FAMILY in your board config!
  19 #endif
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 /*
  24  * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
  25  * setting the 20 bit counter period to its maximum (0xfffff).
  26  * (See the relevant data sheets to understand that this really works)
  27  *
  28  * We do also mimic the typical powerpc way of incrementing
  29  * two 32 bit registers called tbl and tbu.
  30  *
  31  * Those registers increment at 1/16 the main clock rate.
  32  */
  33
  34 #define TIMER_LOAD_VAL  0xfffff
  35
  36 /*
  37  * Use the PITC in full 32 bit incrementing mode
  38  */
  39 int timer_init(void)
  40 {
  41         at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  42         at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
  43
  44         /* Enable PITC Clock */
  45         writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  46
  47         /* Enable PITC */
  48         writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
  49
  50         gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
  51
  52         return 0;
  53 }
  54
  55 /*
  56  * Return the number of timer ticks per second.
  57  */
  58 ulong get_tbclk(void)
  59 {
  60         return gd->arch.timer_rate_hz;
  61 }