arch/arm/mach-mvebu/include/mach/soc.h

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * Header file for the Marvell's Feroceon CPU core.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef _MVEBU_SOC_H
  12 #define _MVEBU_SOC_H
  13
  14 #define SOC_MV78230_ID          0x7823
  15 #define SOC_MV78260_ID          0x7826
  16 #define SOC_MV78460_ID          0x7846
  17 #define SOC_88F6810_ID          0x6810
  18 #define SOC_88F6820_ID          0x6820
  19 #define SOC_88F6828_ID          0x6828
  20
  21 /* A38x revisions */
  22 #define MV_88F68XX_Z1_ID        0x0
  23 #define MV_88F68XX_A0_ID        0x4
  24
  25 /* TCLK Core Clock definition */
  26 #ifndef CONFIG_SYS_TCLK
  27 #define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  28 #endif
  29
  30 /* Armada XP PLL frequency (used for NAND clock generation) */
  31 #define CONFIG_SYS_MVEBU_PLL_CLOCK      2000000000
  32
  33 /* SOC specific definations */
  34 #define INTREG_BASE             0xd0000000
  35 #define INTREG_BASE_ADDR_REG    (INTREG_BASE + 0x20080)
  36 #if defined(CONFIG_SPL_BUILD)
  37 /*
  38  * The SPL U-Boot version still runs with the default
  39  * address for the internal registers, configured by
  40  * the BootROM. Only the main U-Boot version uses the
  41  * new internal register base address, that also is
  42  * required for the Linux kernel.
  43  */
  44 #define SOC_REGS_PHY_BASE       0xd0000000
  45 #else
  46 #define SOC_REGS_PHY_BASE       0xf1000000
  47 #endif
  48 #define MVEBU_REGISTER(x)       (SOC_REGS_PHY_BASE + x)
  49
  50 #define MVEBU_SDRAM_SCRATCH     (MVEBU_REGISTER(0x01504))
  51 #define MVEBU_L2_CACHE_BASE     (MVEBU_REGISTER(0x08000))
  52 #define CONFIG_SYS_PL310_BASE   MVEBU_L2_CACHE_BASE
  53 #define MVEBU_TWSI_BASE         (MVEBU_REGISTER(0x11000))
  54 #define MVEBU_MPP_BASE          (MVEBU_REGISTER(0x18000))
  55 #define MVEBU_GPIO0_BASE        (MVEBU_REGISTER(0x18100))
  56 #define MVEBU_GPIO1_BASE        (MVEBU_REGISTER(0x18140))
  57 #define MVEBU_GPIO2_BASE        (MVEBU_REGISTER(0x18180))
  58 #define MVEBU_SYSTEM_REG_BASE   (MVEBU_REGISTER(0x18200))
  59 #define MVEBU_CLOCK_BASE        (MVEBU_REGISTER(0x18700))
  60 #define MVEBU_CPU_WIN_BASE      (MVEBU_REGISTER(0x20000))
  61 #define MVEBU_SDRAM_BASE        (MVEBU_REGISTER(0x20180))
  62 #define MVEBU_TIMER_BASE        (MVEBU_REGISTER(0x20300))
  63 #define MVEBU_REG_PCIE_BASE     (MVEBU_REGISTER(0x40000))
  64 #define MVEBU_AXP_USB_BASE      (MVEBU_REGISTER(0x50000))
  65 #define MVEBU_USB20_BASE        (MVEBU_REGISTER(0x58000))
  66 #define MVEBU_AXP_SATA_BASE     (MVEBU_REGISTER(0xa0000))
  67 #define MVEBU_SATA0_BASE        (MVEBU_REGISTER(0xa8000))
  68 #define MVEBU_NAND_BASE         (MVEBU_REGISTER(0xd0000))
  69 #define MVEBU_SDIO_BASE         (MVEBU_REGISTER(0xd8000))
  70
  71 #define SOC_COHERENCY_FABRIC_CTRL_REG   (MVEBU_REGISTER(0x20200))
  72 #define MBUS_ERR_PROP_EN        (1 << 8)
  73
  74 #define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
  75 #define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
  76
  77 #define MVEBU_SOC_DEV_MUX_REG   (MVEBU_SYSTEM_REG_BASE + 0x08)
  78 #define NAND_EN                 BIT(0)
  79 #define NAND_ARBITER_EN         BIT(27)
  80
  81 #define ARMADA_XP_PUP_ENABLE    (MVEBU_SYSTEM_REG_BASE + 0x44c)
  82 #define GE0_PUP_EN              BIT(0)
  83 #define GE1_PUP_EN              BIT(1)
  84 #define LCD_PUP_EN              BIT(2)
  85 #define NAND_PUP_EN             BIT(4)
  86 #define SPI_PUP_EN              BIT(5)
  87
  88 #define MVEBU_CORE_DIV_CLK_CTRL(i)      (MVEBU_CLOCK_BASE + ((i) * 0x8))
  89 #define NAND_ECC_DIVCKL_RATIO_OFFS      8
  90 #define NAND_ECC_DIVCKL_RATIO_MASK      (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
  91
  92 #define SDRAM_MAX_CS            4
  93 #define SDRAM_ADDR_MASK         0xFF000000
  94
  95 /* MVEBU CPU memory windows */
  96 #define MVCPU_WIN_CTRL_DATA     CPU_WIN_CTRL_DATA
  97 #define MVCPU_WIN_ENABLE        CPU_WIN_ENABLE
  98 #define MVCPU_WIN_DISABLE       CPU_WIN_DISABLE
  99
 100 #define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
 101
 102 /* BootROM error register (also includes some status infos) */
 103 #define CONFIG_BOOTROM_ERR_REG  (MVEBU_REGISTER(0x182d0))
 104 #define BOOTROM_ERR_MODE_OFFS   28
 105 #define BOOTROM_ERR_MODE_MASK   (0xf << BOOTROM_ERR_MODE_OFFS)
 106 #define BOOTROM_ERR_MODE_UART   0x6
 107
 108 #if defined(CONFIG_ARMADA_38X)
 109 /* SAR values for Armada 38x */
 110 #define CONFIG_SAR_REG          (MVEBU_REGISTER(0x18600))
 111
 112 #define SAR_CPU_FREQ_OFFS       10
 113 #define SAR_CPU_FREQ_MASK       (0x1f << SAR_CPU_FREQ_OFFS)
 114 #define SAR_BOOT_DEVICE_OFFS    4
 115 #define SAR_BOOT_DEVICE_MASK    (0x1f << SAR_BOOT_DEVICE_OFFS)
 116
 117 #define BOOT_DEV_SEL_OFFS       4
 118 #define BOOT_DEV_SEL_MASK       (0x3f << BOOT_DEV_SEL_OFFS)
 119
 120 #define BOOT_FROM_UART          0x28
 121 #define BOOT_FROM_SPI           0x32
 122 #define BOOT_FROM_MMC           0x30
 123 #define BOOT_FROM_MMC_ALT       0x31
 124 #else
 125 /* SAR values for Armada XP */
 126 #define CONFIG_SAR_REG          (MVEBU_REGISTER(0x18230))
 127 #define CONFIG_SAR2_REG         (MVEBU_REGISTER(0x18234))
 128
 129 #define SAR_CPU_FREQ_OFFS       21
 130 #define SAR_CPU_FREQ_MASK       (0x7 << SAR_CPU_FREQ_OFFS)
 131 #define SAR_FFC_FREQ_OFFS       24
 132 #define SAR_FFC_FREQ_MASK       (0xf << SAR_FFC_FREQ_OFFS)
 133 #define SAR2_CPU_FREQ_OFFS      20
 134 #define SAR2_CPU_FREQ_MASK      (0x1 << SAR2_CPU_FREQ_OFFS)
 135 #define SAR_BOOT_DEVICE_OFFS    5
 136 #define SAR_BOOT_DEVICE_MASK    (0xf << SAR_BOOT_DEVICE_OFFS)
 137
 138 #define BOOT_DEV_SEL_OFFS       5
 139 #define BOOT_DEV_SEL_MASK       (0xf << BOOT_DEV_SEL_OFFS)
 140
 141 #define BOOT_FROM_UART          0x2
 142 #define BOOT_FROM_SPI           0x3
 143 #endif
 144
 145 #endif /* _MVEBU_SOC_H */