arch/arm/mach-omap2/am33xx/clock_ti816x.c

   1 /*
   2  * clock_ti816x.c
   3  *
   4  * Clocks for TI816X based boards
   5  *
   6  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   7  * Antoine Tenart, <atenart@adeneo-embedded.com>
   8  *
   9  * Based on TI-PSP-04.00.02.14 :
  10  *
  11  * Copyright (C) 2009, Texas Instruments, Incorporated
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  */
  23
  24 #include <common.h>
  25 #include <asm/arch/ddr_defs.h>
  26 #include <asm/arch/cpu.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/hardware.h>
  29 #include <asm/io.h>
  30
  31 #include <asm/emif.h>
  32
  33 #define CM_PLL_BASE             (CTRL_BASE + 0x0400)
  34
  35 /* Main PLL */
  36 #define MAIN_N                  64
  37 #define MAIN_P                  0x1
  38 #define MAIN_INTFREQ1           0x8
  39 #define MAIN_FRACFREQ1          0x800000
  40 #define MAIN_MDIV1              0x2
  41 #define MAIN_INTFREQ2           0xE
  42 #define MAIN_FRACFREQ2          0x0
  43 #define MAIN_MDIV2              0x1
  44 #define MAIN_INTFREQ3           0x8
  45 #define MAIN_FRACFREQ3          0xAAAAB0
  46 #define MAIN_MDIV3              0x3
  47 #define MAIN_INTFREQ4           0x9
  48 #define MAIN_FRACFREQ4          0x55554F
  49 #define MAIN_MDIV4              0x3
  50 #define MAIN_INTFREQ5           0x9
  51 #define MAIN_FRACFREQ5          0x374BC6
  52 #define MAIN_MDIV5              0xC
  53 #define MAIN_MDIV6              0x48
  54 #define MAIN_MDIV7              0x4
  55
  56 /* DDR PLL */
  57 #if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */
  58 #define DDR_N                   59
  59 #define DDR_P                   0x1
  60 #define DDR_MDIV1               0x4
  61 #define DDR_INTFREQ2            0x8
  62 #define DDR_FRACFREQ2           0xD99999
  63 #define DDR_MDIV2               0x1E
  64 #define DDR_INTFREQ3            0x8
  65 #define DDR_FRACFREQ3           0x0
  66 #define DDR_MDIV3               0x4
  67 #define DDR_INTFREQ4            0xE /* Expansion DDR clk */
  68 #define DDR_FRACFREQ4           0x0
  69 #define DDR_MDIV4               0x4
  70 #define DDR_INTFREQ5            0xE /* Expansion DDR clk */
  71 #define DDR_FRACFREQ5           0x0
  72 #define DDR_MDIV5               0x4
  73 #elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */
  74 #define DDR_N                   59
  75 #define DDR_P                   0x1
  76 #define DDR_MDIV1               0x3
  77 #define DDR_INTFREQ2            0x8
  78 #define DDR_FRACFREQ2           0xD99999
  79 #define DDR_MDIV2               0x1E
  80 #define DDR_INTFREQ3            0x8
  81 #define DDR_FRACFREQ3           0x0
  82 #define DDR_MDIV3               0x4
  83 #define DDR_INTFREQ4            0xE /* Expansion DDR clk */
  84 #define DDR_FRACFREQ4           0x0
  85 #define DDR_MDIV4               0x4
  86 #define DDR_INTFREQ5            0xE /* Expansion DDR clk */
  87 #define DDR_FRACFREQ5           0x0
  88 #define DDR_MDIV5               0x4
  89 #elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */
  90 #define DDR_N                   50
  91 #define DDR_P                   0x1
  92 #define DDR_MDIV1               0x2
  93 #define DDR_INTFREQ2            0x9
  94 #define DDR_FRACFREQ2           0x0
  95 #define DDR_MDIV2               0x19
  96 #define DDR_INTFREQ3            0x13
  97 #define DDR_FRACFREQ3           0x800000
  98 #define DDR_MDIV3               0x2
  99 #define DDR_INTFREQ4            0xE /* Expansion DDR clk */
 100 #define DDR_FRACFREQ4           0x0
 101 #define DDR_MDIV4               0x4
 102 #define DDR_INTFREQ5            0xE /* Expansion DDR clk */
 103 #define DDR_FRACFREQ5           0x0
 104 #define DDR_MDIV5               0x4
 105 #elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */
 106 #define DDR_N                   59
 107 #define DDR_P                   0x1
 108 #define DDR_MDIV1               0x2
 109 #define DDR_INTFREQ2            0x8
 110 #define DDR_FRACFREQ2           0xD99999
 111 #define DDR_MDIV2               0x1E
 112 #define DDR_INTFREQ3            0x8
 113 #define DDR_FRACFREQ3           0x0
 114 #define DDR_MDIV3               0x4
 115 #define DDR_INTFREQ4            0xE /* Expansion DDR clk */
 116 #define DDR_FRACFREQ4           0x0
 117 #define DDR_MDIV4               0x4
 118 #define DDR_INTFREQ5            0xE /* Expansion DDR clk */
 119 #define DDR_FRACFREQ5           0x0
 120 #define DDR_MDIV5               0x4
 121 #endif
 122
 123 #define CONTROL_STATUS                  (CTRL_BASE + 0x40)
 124 #define DDR_RCD                         (CTRL_BASE + 0x070C)
 125 #define CM_TIMER1_CLKSEL                (PRCM_BASE + 0x390)
 126 #define DMM_PAT_BASE_ADDR               (DMM_BASE + 0x420)
 127 #define CM_ALWON_CUST_EFUSE_CLKCTRL     (PRCM_BASE + 0x1628)
 128
 129 #define INTCPS_SYSCONFIG        0x48200010
 130 #define CM_SYSCLK10_CLKSEL      0x48180324
 131
 132 struct cm_pll {
 133         unsigned int mainpll_ctrl;      /* offset 0x400 */
 134         unsigned int mainpll_pwd;
 135         unsigned int mainpll_freq1;
 136         unsigned int mainpll_div1;
 137         unsigned int mainpll_freq2;
 138         unsigned int mainpll_div2;
 139         unsigned int mainpll_freq3;
 140         unsigned int mainpll_div3;
 141         unsigned int mainpll_freq4;
 142         unsigned int mainpll_div4;
 143         unsigned int mainpll_freq5;
 144         unsigned int mainpll_div5;
 145         unsigned int resv0[1];
 146         unsigned int mainpll_div6;
 147         unsigned int resv1[1];
 148         unsigned int mainpll_div7;
 149         unsigned int ddrpll_ctrl;       /* offset 0x440 */
 150         unsigned int ddrpll_pwd;
 151         unsigned int resv2[1];
 152         unsigned int ddrpll_div1;
 153         unsigned int ddrpll_freq2;
 154         unsigned int ddrpll_div2;
 155         unsigned int ddrpll_freq3;
 156         unsigned int ddrpll_div3;
 157         unsigned int ddrpll_freq4;
 158         unsigned int ddrpll_div4;
 159         unsigned int ddrpll_freq5;
 160         unsigned int ddrpll_div5;
 161         unsigned int videopll_ctrl;     /* offset 0x470 */
 162         unsigned int videopll_pwd;
 163         unsigned int videopll_freq1;
 164         unsigned int videopll_div1;
 165         unsigned int videopll_freq2;
 166         unsigned int videopll_div2;
 167         unsigned int videopll_freq3;
 168         unsigned int videopll_div3;
 169         unsigned int resv3[4];
 170         unsigned int audiopll_ctrl;     /* offset 0x4A0 */
 171         unsigned int audiopll_pwd;
 172         unsigned int resv4[2];
 173         unsigned int audiopll_freq2;
 174         unsigned int audiopll_div2;
 175         unsigned int audiopll_freq3;
 176         unsigned int audiopll_div3;
 177         unsigned int audiopll_freq4;
 178         unsigned int audiopll_div4;
 179         unsigned int audiopll_freq5;
 180         unsigned int audiopll_div5;
 181 };
 182
 183 const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
 184 const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
 185 const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
 186 const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
 187
 188 void enable_dmm_clocks(void)
 189 {
 190         writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
 191         writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
 192         writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
 193
 194         /* Wait for clocks to be active */
 195         while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
 196                 ;
 197         /* Wait for emif0 to be fully functional, including OCP */
 198         while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
 199                 ;
 200         /* Wait for emif1 to be fully functional, including OCP */
 201         while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
 202                 ;
 203
 204         writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
 205         /* Wait for dmm to be fully functional, including OCP */
 206         while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
 207                 ;
 208
 209         /* Enable Tiled Access */
 210         writel(0x80000000, DMM_PAT_BASE_ADDR);
 211 }
 212
 213 /* assume delay is aprox at least 1us */
 214 static void ddr_delay(int d)
 215 {
 216         int i;
 217
 218         /*
 219          * read a control register.
 220          * this is a bit more delay and cannot be optimized by the compiler
 221          * assuming one read takes 200 cycles and A8 is runing 1 GHz
 222          * somewhat conservative setting
 223          */
 224         for (i = 0; i < 50*d; i++)
 225                 readl(CONTROL_STATUS);
 226 }
 227
 228 static void main_pll_init_ti816x(void)
 229 {
 230         u32 main_pll_ctrl = 0;
 231
 232         /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
 233         main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
 234         main_pll_ctrl &= 0xFFFFFFFB;
 235         main_pll_ctrl |= BIT(2);
 236         writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
 237
 238         /* Enable PLL by setting BIT3 in its ctrl reg */
 239         main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
 240         main_pll_ctrl &= 0xFFFFFFF7;
 241         main_pll_ctrl |= BIT(3);
 242         writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
 243
 244         /* Write the values of N,P in the CTRL reg  */
 245         main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
 246         main_pll_ctrl &= 0xFF;
 247         main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
 248         writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
 249
 250         /* Power up clock1-7 */
 251         writel(0x0, &cmpll->mainpll_pwd);
 252
 253         /* Program the freq and divider values for clock1-7 */
 254         writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
 255                 &cmpll->mainpll_freq1);
 256         writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
 257
 258         writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
 259                 &cmpll->mainpll_freq2);
 260         writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
 261
 262         writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
 263                 &cmpll->mainpll_freq3);
 264         writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
 265
 266         writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
 267                 &cmpll->mainpll_freq4);
 268         writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
 269
 270         writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
 271                 &cmpll->mainpll_freq5);
 272         writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
 273
 274         writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
 275
 276         writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
 277
 278         /* Wait for PLL to lock */
 279         while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
 280                 ;
 281
 282         /* Put the PLL in normal mode, disable bypass */
 283         main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
 284         main_pll_ctrl &= 0xFFFFFFFB;
 285         writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
 286 }
 287
 288 static void ddr_pll_bypass_ti816x(void)
 289 {
 290         u32 ddr_pll_ctrl = 0;
 291
 292         /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
 293         ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
 294         ddr_pll_ctrl &= 0xFFFFFFFB;
 295         ddr_pll_ctrl |= BIT(2);
 296         writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
 297 }
 298
 299 static void ddr_pll_init_ti816x(void)
 300 {
 301         u32 ddr_pll_ctrl = 0;
 302         /* Enable PLL by setting BIT3 in its ctrl reg */
 303         ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
 304         ddr_pll_ctrl &= 0xFFFFFFF7;
 305         ddr_pll_ctrl |= BIT(3);
 306         writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
 307
 308         /* Write the values of N,P in the CTRL reg  */
 309         ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
 310         ddr_pll_ctrl &= 0xFF;
 311         ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
 312         writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
 313
 314         ddr_delay(10);
 315
 316         /* Power up clock1-5 */
 317         writel(0x0, &cmpll->ddrpll_pwd);
 318
 319         /* Program the freq and divider values for clock1-3 */
 320         writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
 321         ddr_delay(1);
 322         writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
 323         writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
 324                 &cmpll->ddrpll_freq2);
 325         writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
 326         writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
 327         ddr_delay(1);
 328         writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
 329         ddr_delay(1);
 330         writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
 331                 &cmpll->ddrpll_freq3);
 332         ddr_delay(1);
 333         writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
 334                 &cmpll->ddrpll_freq3);
 335
 336         ddr_delay(5);
 337
 338         /* Wait for PLL to lock */
 339         while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
 340                 ;
 341
 342         /* Power up RCD */
 343         writel(BIT(0), DDR_RCD);
 344 }
 345
 346 static void peripheral_enable(void)
 347 {
 348         /* Wake-up the l3_slow clock */
 349         writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
 350
 351         /*
 352          * Note on Timers:
 353          * There are 8 timers(0-7) out of which timer 0 is a secure timer.
 354          * Timer 0 mux should not be changed
 355          *
 356          * To access the timer registers we need the to be
 357          * enabled which is what we do in the first step
 358          */
 359
 360         /* Enable timer1 */
 361         writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
 362         /* Select timer1 clock to be CLKIN (27MHz) */
 363         writel(BIT(1), CM_TIMER1_CLKSEL);
 364
 365         /* Wait for timer1 to be ON-ACTIVE */
 366         while (((readl(&cmalwon->l3slowclkstctrl)
 367                                         & (0x80000<<1))>>20) != 1)
 368                 ;
 369         /* Wait for timer1 to be enabled */
 370         while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
 371                 ;
 372         /* Active posted mode */
 373         writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
 374         while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
 375                 ;
 376         /* Start timer1  */
 377         writel(BIT(0), (DM_TIMER1_BASE + 0x38));
 378
 379         /* eFuse */
 380         writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
 381         while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
 382                 ;
 383
 384         /* Enable gpio0 */
 385         writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
 386         while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
 387                 ;
 388         writel((BIT(8)), &cmalwon->gpio0clkctrl);
 389
 390         /* Enable spi */
 391         writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
 392         while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
 393                 ;
 394
 395         /* Enable i2c0 */
 396         writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
 397         while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
 398                 ;
 399
 400         /* Enable ethernet0 */
 401         writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
 402         writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
 403         writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
 404
 405         /* Enable hsmmc */
 406         writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
 407         while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
 408                 ;
 409 }
 410
 411 void setup_clocks_for_console(void)
 412 {
 413         /* Fix ROM code bug - from TI-PSP-04.00.02.14 */
 414         writel(0x0, CM_SYSCLK10_CLKSEL);
 415
 416         ddr_pll_bypass_ti816x();
 417
 418         /* Enable uart0-2 */
 419         writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
 420         while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
 421                 ;
 422         writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
 423         while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
 424                 ;
 425         writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
 426         while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
 427                 ;
 428         while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
 429                 ;
 430 }
 431
 432 void setup_early_clocks(void)
 433 {
 434         setup_clocks_for_console();
 435 }
 436
 437 void prcm_init(void)
 438 {
 439         /* Enable the control */
 440         writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
 441
 442         main_pll_init_ti816x();
 443         ddr_pll_init_ti816x();
 444
 445         /*
 446          * With clk freqs setup to desired values,
 447          * enable the required peripherals
 448          */
 449         peripheral_enable();
 450 }