arch/arm/mach-omap2/omap4/sdram_elpida.c

   1 /*
   2  * Timing and Organization details of the Elpida parts used in OMAP4
   3  * SDPs and Panda
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <asm/emif.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 /*
  17  * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
  18  * SDP and Panda. Since the parts used and geometry are identical for
  19  * SDP and Panda for a given OMAP4 revision, this information is kept
  20  * here instead of being in board directory. However the key functions
  21  * exported are weakly linked so that they can be over-ridden in the board
  22  * directory if there is a OMAP4 board in the future that uses a different
  23  * memory device or geometry.
  24  *
  25  * For any new board with different memory devices over-ride one or more
  26  * of the following functions as per the CONFIG flags you intend to enable:
  27  * - emif_get_reg_dump()
  28  * - emif_get_dmm_regs()
  29  * - emif_get_device_details()
  30  * - emif_get_device_timings()
  31  */
  32
  33 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  34
  35 const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
  36         .sdram_config_init              = 0x80000eb9,
  37         .sdram_config                   = 0x80001ab9,
  38         .ref_ctrl                       = 0x0000030c,
  39         .sdram_tim1                     = 0x08648311,
  40         .sdram_tim2                     = 0x101b06ca,
  41         .sdram_tim3                     = 0x0048a19f,
  42         .read_idle_ctrl                 = 0x000501ff,
  43         .zq_config                      = 0x500b3214,
  44         .temp_alert_config              = 0xd8016893,
  45         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  46         .emif_ddr_phy_ctlr_1            = 0x049ff808
  47 };
  48
  49 const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
  50         .sdram_config_init              = 0x80000eb1,
  51         .sdram_config                   = 0x80001ab1,
  52         .ref_ctrl                       = 0x000005cd,
  53         .sdram_tim1                     = 0x10cb0622,
  54         .sdram_tim2                     = 0x20350d52,
  55         .sdram_tim3                     = 0x00b1431f,
  56         .read_idle_ctrl                 = 0x000501ff,
  57         .zq_config                      = 0x500b3214,
  58         .temp_alert_config              = 0x58016893,
  59         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  60         .emif_ddr_phy_ctlr_1            = 0x049ff418
  61 };
  62
  63 const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
  64         .sdram_config_init              = 0x80800eb2,
  65         .sdram_config                   = 0x80801ab2,
  66         .ref_ctrl                       = 0x00000618,
  67         .sdram_tim1                     = 0x10eb0662,
  68         .sdram_tim2                     = 0x20370dd2,
  69         .sdram_tim3                     = 0x00b1c33f,
  70         .read_idle_ctrl                 = 0x000501ff,
  71         .zq_config                      = 0x500b3215,
  72         .temp_alert_config              = 0x58016893,
  73         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  74         .emif_ddr_phy_ctlr_1            = 0x049ff418
  75 };
  76
  77 const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
  78         .sdram_config_init              = 0x80000eb9,
  79         .sdram_config                   = 0x80001ab9,
  80         .ref_ctrl                       = 0x00000618,
  81         .sdram_tim1                     = 0x10eb0662,
  82         .sdram_tim2                     = 0x20370dd2,
  83         .sdram_tim3                     = 0x00b1c33f,
  84         .read_idle_ctrl                 = 0x000501ff,
  85         .zq_config                      = 0xd00b3214,
  86         .temp_alert_config              = 0xd8016893,
  87         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  88         .emif_ddr_phy_ctlr_1            = 0x049ff418
  89 };
  90
  91 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
  92         .dmm_lisa_map_0 = 0xFF020100,
  93         .dmm_lisa_map_1 = 0,
  94         .dmm_lisa_map_2 = 0,
  95         .dmm_lisa_map_3 = 0x80540300,
  96         .is_ma_present  = 0x0
  97 };
  98
  99 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 100         .dmm_lisa_map_0 = 0xFF020100,
 101         .dmm_lisa_map_1 = 0,
 102         .dmm_lisa_map_2 = 0,
 103         .dmm_lisa_map_3 = 0x80640300,
 104         .is_ma_present  = 0x0
 105 };
 106
 107 const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
 108         .dmm_lisa_map_0 = 0xFF020100,
 109         .dmm_lisa_map_1 = 0,
 110         .dmm_lisa_map_2 = 0,
 111         .dmm_lisa_map_3 = 0x80640300,
 112         .is_ma_present  = 0x1
 113 };
 114
 115 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 116 {
 117         u32 omap4_rev = omap_revision();
 118
 119         /* Same devices and geometry on both EMIFs */
 120         if (omap4_rev == OMAP4430_ES1_0)
 121                 *regs = &emif_regs_elpida_380_mhz_1cs;
 122         else if (omap4_rev == OMAP4430_ES2_0)
 123                 *regs = &emif_regs_elpida_200_mhz_2cs;
 124         else if (omap4_rev < OMAP4470_ES1_0)
 125                 *regs = &emif_regs_elpida_400_mhz_2cs;
 126         else
 127                 *regs = &emif_regs_elpida_400_mhz_1cs;
 128 }
 129 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 130         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 131
 132 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 133                                                 **dmm_lisa_regs)
 134 {
 135         u32 omap_rev = omap_revision();
 136
 137         if (omap_rev == OMAP4430_ES1_0)
 138                 *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
 139         else if (omap_rev < OMAP4460_ES1_0)
 140                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
 141         else
 142                 *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
 143 }
 144
 145 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 146         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 147
 148 #else
 149
 150 const struct lpddr2_device_details elpida_2G_S4_details = {
 151         .type           = LPDDR2_TYPE_S4,
 152         .density        = LPDDR2_DENSITY_2Gb,
 153         .io_width       = LPDDR2_IO_WIDTH_32,
 154         .manufacturer   = LPDDR2_MANUFACTURER_ELPIDA
 155 };
 156
 157 const struct lpddr2_device_details elpida_4G_S4_details = {
 158         .type           = LPDDR2_TYPE_S4,
 159         .density        = LPDDR2_DENSITY_4Gb,
 160         .io_width       = LPDDR2_IO_WIDTH_32,
 161         .manufacturer   = LPDDR2_MANUFACTURER_ELPIDA
 162 };
 163
 164 struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
 165                         struct lpddr2_device_details *lpddr2_dev_details)
 166 {
 167         u32 omap_rev = omap_revision();
 168
 169         /* EMIF1 & EMIF2 have identical configuration */
 170         if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
 171                 && (cs == CS1)) {
 172                 /* Nothing connected on CS1 for 4430/4470 ES1.0 */
 173                 return NULL;
 174         } else if (omap_rev < OMAP4470_ES1_0) {
 175                 /* In all other 4430/4460 cases Elpida 2G device */
 176                 *lpddr2_dev_details = elpida_2G_S4_details;
 177         } else {
 178                 /* 4470: 4G device */
 179                 *lpddr2_dev_details = elpida_4G_S4_details;
 180         }
 181         return lpddr2_dev_details;
 182 }
 183
 184 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
 185                         struct lpddr2_device_details *lpddr2_dev_details)
 186         __attribute__((weak, alias("emif_get_device_details_sdp")));
 187
 188 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 189
 190 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 191 static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
 192         .max_freq       = 400000000,
 193         .RL             = 6,
 194         .tRPab          = 21,
 195         .tRCD           = 18,
 196         .tWR            = 15,
 197         .tRASmin        = 42,
 198         .tRRD           = 10,
 199         .tWTRx2         = 15,
 200         .tXSR           = 140,
 201         .tXPx2          = 15,
 202         .tRFCab         = 130,
 203         .tRTPx2         = 15,
 204         .tCKE           = 3,
 205         .tCKESR         = 15,
 206         .tZQCS          = 90,
 207         .tZQCL          = 360,
 208         .tZQINIT        = 1000,
 209         .tDQSCKMAXx2    = 11,
 210         .tRASmax        = 70,
 211         .tFAW           = 50
 212 };
 213
 214 static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
 215         .max_freq       = 333000000,
 216         .RL             = 5,
 217         .tRPab          = 21,
 218         .tRCD           = 18,
 219         .tWR            = 15,
 220         .tRASmin        = 42,
 221         .tRRD           = 10,
 222         .tWTRx2         = 15,
 223         .tXSR           = 140,
 224         .tXPx2          = 15,
 225         .tRFCab         = 130,
 226         .tRTPx2         = 15,
 227         .tCKE           = 3,
 228         .tCKESR         = 15,
 229         .tZQCS          = 90,
 230         .tZQCL          = 360,
 231         .tZQINIT        = 1000,
 232         .tDQSCKMAXx2    = 11,
 233         .tRASmax        = 70,
 234         .tFAW           = 50
 235 };
 236
 237 static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
 238         .max_freq       = 200000000,
 239         .RL             = 3,
 240         .tRPab          = 21,
 241         .tRCD           = 18,
 242         .tWR            = 15,
 243         .tRASmin        = 42,
 244         .tRRD           = 10,
 245         .tWTRx2         = 20,
 246         .tXSR           = 140,
 247         .tXPx2          = 15,
 248         .tRFCab         = 130,
 249         .tRTPx2         = 15,
 250         .tCKE           = 3,
 251         .tCKESR         = 15,
 252         .tZQCS          = 90,
 253         .tZQCL          = 360,
 254         .tZQINIT        = 1000,
 255         .tDQSCKMAXx2    = 11,
 256         .tRASmax        = 70,
 257         .tFAW           = 50
 258 };
 259
 260 static const struct lpddr2_min_tck min_tck_elpida = {
 261         .tRL            = 3,
 262         .tRP_AB         = 3,
 263         .tRCD           = 3,
 264         .tWR            = 3,
 265         .tRAS_MIN       = 3,
 266         .tRRD           = 2,
 267         .tWTR           = 2,
 268         .tXP            = 2,
 269         .tRTP           = 2,
 270         .tCKE           = 3,
 271         .tCKESR         = 3,
 272         .tFAW           = 8
 273 };
 274
 275 static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
 276                 &timings_elpida_200_mhz,
 277                 &timings_elpida_333_mhz,
 278                 &timings_elpida_400_mhz
 279 };
 280
 281 const struct lpddr2_device_timings elpida_2G_S4_timings = {
 282         .ac_timings     = elpida_ac_timings,
 283         .min_tck        = &min_tck_elpida,
 284 };
 285
 286 void emif_get_device_timings_sdp(u32 emif_nr,
 287                 const struct lpddr2_device_timings **cs0_device_timings,
 288                 const struct lpddr2_device_timings **cs1_device_timings)
 289 {
 290         u32 omap_rev = omap_revision();
 291
 292         /* Identical devices on EMIF1 & EMIF2 */
 293         *cs0_device_timings = &elpida_2G_S4_timings;
 294
 295         if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
 296                 *cs1_device_timings = NULL;
 297         else
 298                 *cs1_device_timings = &elpida_2G_S4_timings;
 299 }
 300
 301 void emif_get_device_timings(u32 emif_nr,
 302                 const struct lpddr2_device_timings **cs0_device_timings,
 303                 const struct lpddr2_device_timings **cs1_device_timings)
 304         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 305
 306 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
 307
 308 const struct lpddr2_mr_regs mr_regs = {
 309         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
 310         .mr2    = 0x4,
 311         .mr3    = -1,
 312         .mr10   = MR10_ZQ_ZQINIT,
 313         .mr16   = MR16_REF_FULL_ARRAY
 314 };
 315
 316 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 317 {
 318         *regs = &mr_regs;
 319 }
 320
 321 __weak const struct read_write_regs *get_bug_regs(u32 *iterations)
 322 {
 323         return 0;
 324 }