3 * Functions for omap5 based boards.
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 * Sricharan <r.sricharan@ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/armv7.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/clock.h>
21 #include <linux/sizes.h>
22 #include <asm/utils.h>
23 #include <asm/arch/gpio.h>
25 #include <asm/omap_common.h>
27 DECLARE_GLOBAL_DATA_PTR
;
29 u32
*const omap_si_rev
= (u32
*)OMAP_SRAM_SCRATCH_OMAP_REV
;
31 #ifndef CONFIG_DM_GPIO
32 static struct gpio_bank gpio_bank_54xx
[8] = {
33 { (void *)OMAP54XX_GPIO1_BASE
},
34 { (void *)OMAP54XX_GPIO2_BASE
},
35 { (void *)OMAP54XX_GPIO3_BASE
},
36 { (void *)OMAP54XX_GPIO4_BASE
},
37 { (void *)OMAP54XX_GPIO5_BASE
},
38 { (void *)OMAP54XX_GPIO6_BASE
},
39 { (void *)OMAP54XX_GPIO7_BASE
},
40 { (void *)OMAP54XX_GPIO8_BASE
},
43 const struct gpio_bank
*const omap_gpio_bank
= gpio_bank_54xx
;
46 void do_set_mux32(u32 base
, struct pad_conf_entry
const *array
, int size
)
49 struct pad_conf_entry
*pad
= (struct pad_conf_entry
*)array
;
51 for (i
= 0; i
< size
; i
++, pad
++)
52 writel(pad
->val
, base
+ pad
->offset
);
55 #ifdef CONFIG_SPL_BUILD
56 /* LPDDR2 specific IO settings */
57 static void io_settings_lpddr2(void)
59 const struct ctrl_ioregs
*ioregs
;
62 writel(ioregs
->ctrl_ddrch
, (*ctrl
)->control_ddrch1_0
);
63 writel(ioregs
->ctrl_ddrch
, (*ctrl
)->control_ddrch1_1
);
64 writel(ioregs
->ctrl_ddrch
, (*ctrl
)->control_ddrch2_0
);
65 writel(ioregs
->ctrl_ddrch
, (*ctrl
)->control_ddrch2_1
);
66 writel(ioregs
->ctrl_lpddr2ch
, (*ctrl
)->control_lpddr2ch1_0
);
67 writel(ioregs
->ctrl_lpddr2ch
, (*ctrl
)->control_lpddr2ch1_1
);
68 writel(ioregs
->ctrl_ddrio_0
, (*ctrl
)->control_ddrio_0
);
69 writel(ioregs
->ctrl_ddrio_1
, (*ctrl
)->control_ddrio_1
);
70 writel(ioregs
->ctrl_ddrio_2
, (*ctrl
)->control_ddrio_2
);
73 /* DDR3 specific IO settings */
74 static void io_settings_ddr3(void)
77 const struct ctrl_ioregs
*ioregs
;
80 writel(ioregs
->ctrl_ddr3ch
, (*ctrl
)->control_ddr3ch1_0
);
81 writel(ioregs
->ctrl_ddrch
, (*ctrl
)->control_ddrch1_0
);
82 writel(ioregs
->ctrl_ddrch
, (*ctrl
)->control_ddrch1_1
);
84 writel(ioregs
->ctrl_ddr3ch
, (*ctrl
)->control_ddr3ch2_0
);
85 writel(ioregs
->ctrl_ddrch
, (*ctrl
)->control_ddrch2_0
);
86 writel(ioregs
->ctrl_ddrch
, (*ctrl
)->control_ddrch2_1
);
88 writel(ioregs
->ctrl_ddrio_0
, (*ctrl
)->control_ddrio_0
);
89 writel(ioregs
->ctrl_ddrio_1
, (*ctrl
)->control_ddrio_1
);
92 writel(ioregs
->ctrl_ddrio_2
, (*ctrl
)->control_ddrio_2
);
93 writel(ioregs
->ctrl_lpddr2ch
, (*ctrl
)->control_lpddr2ch1_1
);
96 /* omap5432 does not use lpddr2 */
97 writel(ioregs
->ctrl_lpddr2ch
, (*ctrl
)->control_lpddr2ch1_0
);
99 writel(ioregs
->ctrl_emif_sdram_config_ext
,
100 (*ctrl
)->control_emif1_sdram_config_ext
);
102 writel(ioregs
->ctrl_emif_sdram_config_ext
,
103 (*ctrl
)->control_emif2_sdram_config_ext
);
106 /* Disable DLL select */
107 io_settings
= (readl((*ctrl
)->control_port_emif1_sdram_config
)
110 (*ctrl
)->control_port_emif1_sdram_config
);
112 io_settings
= (readl((*ctrl
)->control_port_emif2_sdram_config
)
115 (*ctrl
)->control_port_emif2_sdram_config
);
117 writel(ioregs
->ctrl_ddr_ctrl_ext_0
,
118 (*ctrl
)->control_ddr_control_ext_0
);
123 * Some tuning of IOs for optimal power and performance
125 void do_io_settings(void)
127 u32 io_settings
= 0, mask
= 0;
128 struct emif_reg_struct
*emif
= (struct emif_reg_struct
*)EMIF1_BASE
;
130 /* Impedance settings EMMC, C2C 1,2, hsi2 */
131 mask
= (ds_mask
<< 2) | (ds_mask
<< 8) |
132 (ds_mask
<< 16) | (ds_mask
<< 18);
133 io_settings
= readl((*ctrl
)->control_smart1io_padconf_0
) &
135 io_settings
|= (ds_60_ohm
<< 8) | (ds_45_ohm
<< 16) |
136 (ds_45_ohm
<< 18) | (ds_60_ohm
<< 2);
137 writel(io_settings
, (*ctrl
)->control_smart1io_padconf_0
);
139 /* Impedance settings Mcspi2 */
140 mask
= (ds_mask
<< 30);
141 io_settings
= readl((*ctrl
)->control_smart1io_padconf_1
) &
143 io_settings
|= (ds_60_ohm
<< 30);
144 writel(io_settings
, (*ctrl
)->control_smart1io_padconf_1
);
146 /* Impedance settings C2C 3,4 */
147 mask
= (ds_mask
<< 14) | (ds_mask
<< 16);
148 io_settings
= readl((*ctrl
)->control_smart1io_padconf_2
) &
150 io_settings
|= (ds_45_ohm
<< 14) | (ds_45_ohm
<< 16);
151 writel(io_settings
, (*ctrl
)->control_smart1io_padconf_2
);
153 /* Slew rate settings EMMC, C2C 1,2 */
154 mask
= (sc_mask
<< 8) | (sc_mask
<< 16) | (sc_mask
<< 18);
155 io_settings
= readl((*ctrl
)->control_smart2io_padconf_0
) &
157 io_settings
|= (sc_fast
<< 8) | (sc_na
<< 16) | (sc_na
<< 18);
158 writel(io_settings
, (*ctrl
)->control_smart2io_padconf_0
);
160 /* Slew rate settings hsi2, Mcspi2 */
161 mask
= (sc_mask
<< 24) | (sc_mask
<< 28);
162 io_settings
= readl((*ctrl
)->control_smart2io_padconf_1
) &
164 io_settings
|= (sc_fast
<< 28) | (sc_fast
<< 24);
165 writel(io_settings
, (*ctrl
)->control_smart2io_padconf_1
);
167 /* Slew rate settings C2C 3,4 */
168 mask
= (sc_mask
<< 16) | (sc_mask
<< 18);
169 io_settings
= readl((*ctrl
)->control_smart2io_padconf_2
) &
171 io_settings
|= (sc_na
<< 16) | (sc_na
<< 18);
172 writel(io_settings
, (*ctrl
)->control_smart2io_padconf_2
);
174 /* impedance and slew rate settings for usb */
175 mask
= (usb_i_mask
<< 29) | (usb_i_mask
<< 26) | (usb_i_mask
<< 23) |
176 (usb_i_mask
<< 20) | (usb_i_mask
<< 17) | (usb_i_mask
<< 14);
177 io_settings
= readl((*ctrl
)->control_smart3io_padconf_1
) &
179 io_settings
|= (ds_60_ohm
<< 29) | (ds_60_ohm
<< 26) |
180 (ds_60_ohm
<< 23) | (sc_fast
<< 20) |
181 (sc_fast
<< 17) | (sc_fast
<< 14);
182 writel(io_settings
, (*ctrl
)->control_smart3io_padconf_1
);
184 if (emif_sdram_type(emif
->emif_sdram_config
) == EMIF_SDRAM_TYPE_LPDDR2
)
185 io_settings_lpddr2();
190 static const struct srcomp_params srcomp_parameters
[NUM_SYS_CLKS
] = {
191 {0x45, 0x1}, /* 12 MHz */
192 {-1, -1}, /* 13 MHz */
193 {0x63, 0x2}, /* 16.8 MHz */
194 {0x57, 0x2}, /* 19.2 MHz */
195 {0x20, 0x1}, /* 26 MHz */
196 {-1, -1}, /* 27 MHz */
197 {0x41, 0x3} /* 38.4 MHz */
200 void srcomp_enable(void)
202 u32 srcomp_value
, mul_factor
, div_factor
, clk_val
, i
;
203 u32 sysclk_ind
= get_sys_clk_index();
204 u32 omap_rev
= omap_revision();
209 mul_factor
= srcomp_parameters
[sysclk_ind
].multiply_factor
;
210 div_factor
= srcomp_parameters
[sysclk_ind
].divide_factor
;
212 for (i
= 0; i
< 4; i
++) {
213 srcomp_value
= readl((*ctrl
)->control_srcomp_north_side
+ i
*4);
215 ~(MULTIPLY_FACTOR_XS_MASK
| DIVIDE_FACTOR_XS_MASK
);
216 srcomp_value
|= (mul_factor
<< MULTIPLY_FACTOR_XS_SHIFT
) |
217 (div_factor
<< DIVIDE_FACTOR_XS_SHIFT
);
218 writel(srcomp_value
, (*ctrl
)->control_srcomp_north_side
+ i
*4);
221 if ((omap_rev
== OMAP5430_ES1_0
) || (omap_rev
== OMAP5432_ES1_0
)) {
222 clk_val
= readl((*prcm
)->cm_coreaon_io_srcomp_clkctrl
);
223 clk_val
|= OPTFCLKEN_SRCOMP_FCLK_MASK
;
224 writel(clk_val
, (*prcm
)->cm_coreaon_io_srcomp_clkctrl
);
226 for (i
= 0; i
< 4; i
++) {
228 readl((*ctrl
)->control_srcomp_north_side
+ i
*4);
229 srcomp_value
&= ~PWRDWN_XS_MASK
;
231 (*ctrl
)->control_srcomp_north_side
+ i
*4);
233 while (((readl((*ctrl
)->control_srcomp_north_side
+ i
*4)
234 & SRCODE_READ_XS_MASK
) >>
235 SRCODE_READ_XS_SHIFT
) == 0)
239 readl((*ctrl
)->control_srcomp_north_side
+ i
*4);
240 srcomp_value
&= ~OVERRIDE_XS_MASK
;
242 (*ctrl
)->control_srcomp_north_side
+ i
*4);
245 srcomp_value
= readl((*ctrl
)->control_srcomp_east_side_wkup
);
246 srcomp_value
&= ~(MULTIPLY_FACTOR_XS_MASK
|
247 DIVIDE_FACTOR_XS_MASK
);
248 srcomp_value
|= (mul_factor
<< MULTIPLY_FACTOR_XS_SHIFT
) |
249 (div_factor
<< DIVIDE_FACTOR_XS_SHIFT
);
250 writel(srcomp_value
, (*ctrl
)->control_srcomp_east_side_wkup
);
252 for (i
= 0; i
< 4; i
++) {
254 readl((*ctrl
)->control_srcomp_north_side
+ i
*4);
255 srcomp_value
|= SRCODE_OVERRIDE_SEL_XS_MASK
;
257 (*ctrl
)->control_srcomp_north_side
+ i
*4);
260 readl((*ctrl
)->control_srcomp_north_side
+ i
*4);
261 srcomp_value
&= ~OVERRIDE_XS_MASK
;
263 (*ctrl
)->control_srcomp_north_side
+ i
*4);
267 readl((*ctrl
)->control_srcomp_east_side_wkup
);
268 srcomp_value
|= SRCODE_OVERRIDE_SEL_XS_MASK
;
269 writel(srcomp_value
, (*ctrl
)->control_srcomp_east_side_wkup
);
272 readl((*ctrl
)->control_srcomp_east_side_wkup
);
273 srcomp_value
&= ~OVERRIDE_XS_MASK
;
274 writel(srcomp_value
, (*ctrl
)->control_srcomp_east_side_wkup
);
276 clk_val
= readl((*prcm
)->cm_coreaon_io_srcomp_clkctrl
);
277 clk_val
|= OPTFCLKEN_SRCOMP_FCLK_MASK
;
278 writel(clk_val
, (*prcm
)->cm_coreaon_io_srcomp_clkctrl
);
280 clk_val
= readl((*prcm
)->cm_wkupaon_io_srcomp_clkctrl
);
281 clk_val
|= OPTFCLKEN_SRCOMP_FCLK_MASK
;
282 writel(clk_val
, (*prcm
)->cm_wkupaon_io_srcomp_clkctrl
);
284 for (i
= 0; i
< 4; i
++) {
285 while (((readl((*ctrl
)->control_srcomp_north_side
+ i
*4)
286 & SRCODE_READ_XS_MASK
) >>
287 SRCODE_READ_XS_SHIFT
) == 0)
291 readl((*ctrl
)->control_srcomp_north_side
+ i
*4);
292 srcomp_value
&= ~SRCODE_OVERRIDE_SEL_XS_MASK
;
294 (*ctrl
)->control_srcomp_north_side
+ i
*4);
297 while (((readl((*ctrl
)->control_srcomp_east_side_wkup
) &
298 SRCODE_READ_XS_MASK
) >> SRCODE_READ_XS_SHIFT
) == 0)
302 readl((*ctrl
)->control_srcomp_east_side_wkup
);
303 srcomp_value
&= ~SRCODE_OVERRIDE_SEL_XS_MASK
;
304 writel(srcomp_value
, (*ctrl
)->control_srcomp_east_side_wkup
);
309 void config_data_eye_leveling_samples(u32 emif_base
)
311 const struct ctrl_ioregs
*ioregs
;
315 /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
316 if (emif_base
== EMIF1_BASE
)
317 writel(ioregs
->ctrl_emif_sdram_config_ext_final
,
318 (*ctrl
)->control_emif1_sdram_config_ext
);
319 else if (emif_base
== EMIF2_BASE
)
320 writel(ioregs
->ctrl_emif_sdram_config_ext_final
,
321 (*ctrl
)->control_emif2_sdram_config_ext
);
324 void init_cpu_configuration(void)
328 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr
));
330 * L2ACTLR: Ensure to enable the following:
331 * 3: Disable clean/evict push to external
332 * 4: Disable WriteUnique and WriteLineUnique transactions from master
333 * 8: Disable DVM/CMO message broadcast
336 omap_smc1(OMAP5_SERVICE_L2ACTLR_SET
, l2actlr
);
339 void init_omap_revision(void)
342 * For some of the ES2/ES1 boards ID_CODE is not reliable:
343 * Also, ES1 and ES2 have different ARM revisions
344 * So use ARM revision for identification
346 unsigned int rev
= cortex_rev();
348 switch (readl(CONTROL_ID_CODE
)) {
349 case OMAP5430_CONTROL_ID_CODE_ES1_0
:
350 *omap_si_rev
= OMAP5430_ES1_0
;
351 if (rev
== MIDR_CORTEX_A15_R2P2
)
352 *omap_si_rev
= OMAP5430_ES2_0
;
354 case OMAP5432_CONTROL_ID_CODE_ES1_0
:
355 *omap_si_rev
= OMAP5432_ES1_0
;
356 if (rev
== MIDR_CORTEX_A15_R2P2
)
357 *omap_si_rev
= OMAP5432_ES2_0
;
359 case OMAP5430_CONTROL_ID_CODE_ES2_0
:
360 *omap_si_rev
= OMAP5430_ES2_0
;
362 case OMAP5432_CONTROL_ID_CODE_ES2_0
:
363 *omap_si_rev
= OMAP5432_ES2_0
;
365 case DRA752_CONTROL_ID_CODE_ES1_0
:
366 *omap_si_rev
= DRA752_ES1_0
;
368 case DRA752_CONTROL_ID_CODE_ES1_1
:
369 *omap_si_rev
= DRA752_ES1_1
;
371 case DRA752_CONTROL_ID_CODE_ES2_0
:
372 *omap_si_rev
= DRA752_ES2_0
;
374 case DRA722_CONTROL_ID_CODE_ES1_0
:
375 *omap_si_rev
= DRA722_ES1_0
;
377 case DRA722_CONTROL_ID_CODE_ES2_0
:
378 *omap_si_rev
= DRA722_ES2_0
;
381 *omap_si_rev
= OMAP5430_SILICON_ID_INVALID
;
383 init_cpu_configuration();
386 void omap_die_id(unsigned int *die_id
)
388 die_id
[0] = readl((*ctrl
)->control_std_fuse_die_id_0
);
389 die_id
[1] = readl((*ctrl
)->control_std_fuse_die_id_1
);
390 die_id
[2] = readl((*ctrl
)->control_std_fuse_die_id_2
);
391 die_id
[3] = readl((*ctrl
)->control_std_fuse_die_id_3
);
394 void reset_cpu(ulong ignored
)
396 u32 omap_rev
= omap_revision();
399 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
400 * So use cold reset in case instead.
402 if (omap_rev
== OMAP5430_ES1_0
)
403 writel(PRM_RSTCTRL_RESET
<< 0x1, (*prcm
)->prm_rstctrl
);
405 writel(PRM_RSTCTRL_RESET
, (*prcm
)->prm_rstctrl
);
410 return readl((*prcm
)->prm_rstst
) & PRM_RSTST_WARM_RESET_MASK
;
413 void setup_warmreset_time(void)
415 u32 rst_time
, rst_val
;
417 #ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
418 rst_time
= CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC
;
420 rst_time
= CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
;
422 rst_time
= usec_to_32k(rst_time
) << RSTTIME1_SHIFT
;
424 if (rst_time
> RSTTIME1_MASK
)
425 rst_time
= RSTTIME1_MASK
;
427 rst_val
= readl((*prcm
)->prm_rsttime
) & ~RSTTIME1_MASK
;
429 writel(rst_val
, (*prcm
)->prm_rsttime
);
432 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl
, u32 cpu_midr
,
433 u32 cpu_rev_comb
, u32 cpu_variant
,
436 omap_smc1(OMAP5_SERVICE_L2ACTLR_SET
, l2auxctrl
);
439 void v7_arch_cp15_set_acr(u32 acr
, u32 cpu_midr
, u32 cpu_rev_comb
,
440 u32 cpu_variant
, u32 cpu_rev
)
443 #ifdef CONFIG_ARM_ERRATA_801819
445 * DRA72x processors are uniprocessors and DONOT have
446 * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
447 * Extensions) Hence the erratum workaround is not applicable for
451 acr
&= ~((0x3 << 23) | (0x3 << 25));
453 omap_smc1(OMAP5_SERVICE_ACR_SET
, acr
);
456 #if defined(CONFIG_PALMAS_POWER)
457 void vmmc_pbias_config(uint voltage
)
460 struct vcores_data
const *vcores
= *omap_vcores
;
462 value
= readl((*ctrl
)->control_pbias
);
463 value
&= ~SDCARD_PWRDNZ
;
464 writel(value
, (*ctrl
)->control_pbias
);
465 udelay(10); /* wait 10 us */
466 value
&= ~SDCARD_BIAS_PWRDNZ
;
467 writel(value
, (*ctrl
)->control_pbias
);
469 if (vcores
->core
.pmic
->i2c_slave_addr
== 0x60) {
470 if (voltage
== LDO_VOLT_3V0
)
472 else if (voltage
== LDO_VOLT_1V8
)
474 lp873x_mmc1_poweron_ldo(voltage
);
476 palmas_mmc1_poweron_ldo(voltage
);
479 value
= readl((*ctrl
)->control_pbias
);
480 value
|= SDCARD_BIAS_PWRDNZ
;
481 writel(value
, (*ctrl
)->control_pbias
);
482 udelay(150); /* wait 150 us */
483 value
|= SDCARD_PWRDNZ
;
484 writel(value
, (*ctrl
)->control_pbias
);
485 udelay(150); /* wait 150 us */