arch/arm/mach-sunxi/Kconfig

   1 if ARCH_SUNXI
   2
   3 config IDENT_STRING
   4         default " Allwinner Technology"
   5
   6 config SUNXI_HIGH_SRAM
   7         bool
   8         default n
   9         ---help---
  10         Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
  11         with the first SRAM region being located at address 0.
  12         Some newer SoCs map the boot ROM at address 0 instead and move the
  13         SRAM to 64KB, just behind the mask ROM.
  14         Chips using the latter setup are supposed to select this option to
  15         adjust the addresses accordingly.
  16
  17 # Note only one of these may be selected at a time! But hidden choices are
  18 # not supported by Kconfig
  19 config SUNXI_GEN_SUN4I
  20         bool
  21         ---help---
  22         Select this for sunxi SoCs which have resets and clocks set up
  23         as the original A10 (mach-sun4i).
  24
  25 config SUNXI_GEN_SUN6I
  26         bool
  27         ---help---
  28         Select this for sunxi SoCs which have sun6i like periphery, like
  29         separate ahb reset control registers, custom pmic bus, new style
  30         watchdog, etc.
  31
  32
  33 config MACH_SUNXI_H3_H5
  34         bool
  35         select DM_I2C
  36         select SUNXI_DE2
  37         select SUNXI_GEN_SUN6I
  38         select SUPPORT_SPL
  39
  40 choice
  41         prompt "Sunxi SoC Variant"
  42         optional
  43
  44 config MACH_SUN4I
  45         bool "sun4i (Allwinner A10)"
  46         select CPU_V7
  47         select ARM_CORTEX_CPU_IS_UP
  48         select SUNXI_GEN_SUN4I
  49         select SUPPORT_SPL
  50
  51 config MACH_SUN5I
  52         bool "sun5i (Allwinner A13)"
  53         select CPU_V7
  54         select ARM_CORTEX_CPU_IS_UP
  55         select SUNXI_GEN_SUN4I
  56         select SUPPORT_SPL
  57
  58 config MACH_SUN6I
  59         bool "sun6i (Allwinner A31)"
  60         select CPU_V7
  61         select CPU_V7_HAS_NONSEC
  62         select CPU_V7_HAS_VIRT
  63         select ARCH_SUPPORT_PSCI
  64         select SUNXI_GEN_SUN6I
  65         select SUPPORT_SPL
  66         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  67
  68 config MACH_SUN7I
  69         bool "sun7i (Allwinner A20)"
  70         select CPU_V7
  71         select CPU_V7_HAS_NONSEC
  72         select CPU_V7_HAS_VIRT
  73         select ARCH_SUPPORT_PSCI
  74         select SUNXI_GEN_SUN4I
  75         select SUPPORT_SPL
  76         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  77
  78 config MACH_SUN8I_A23
  79         bool "sun8i (Allwinner A23)"
  80         select CPU_V7
  81         select CPU_V7_HAS_NONSEC
  82         select CPU_V7_HAS_VIRT
  83         select ARCH_SUPPORT_PSCI
  84         select SUNXI_GEN_SUN6I
  85         select SUPPORT_SPL
  86         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  87
  88 config MACH_SUN8I_A33
  89         bool "sun8i (Allwinner A33)"
  90         select CPU_V7
  91         select CPU_V7_HAS_NONSEC
  92         select CPU_V7_HAS_VIRT
  93         select ARCH_SUPPORT_PSCI
  94         select SUNXI_GEN_SUN6I
  95         select SUPPORT_SPL
  96         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  97
  98 config MACH_SUN8I_A83T
  99         bool "sun8i (Allwinner A83T)"
 100         select CPU_V7
 101         select SUNXI_GEN_SUN6I
 102         select SUPPORT_SPL
 103
 104 config MACH_SUN8I_H3
 105         bool "sun8i (Allwinner H3)"
 106         select CPU_V7
 107         select CPU_V7_HAS_NONSEC
 108         select CPU_V7_HAS_VIRT
 109         select ARCH_SUPPORT_PSCI
 110         select MACH_SUNXI_H3_H5
 111         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 112
 113 config MACH_SUN8I_R40
 114         bool "sun8i (Allwinner R40)"
 115         select CPU_V7
 116         select CPU_V7_HAS_NONSEC
 117         select CPU_V7_HAS_VIRT
 118         select ARCH_SUPPORT_PSCI
 119         select SUNXI_GEN_SUN6I
 120         select SUPPORT_SPL
 121
 122 config MACH_SUN8I_V3S
 123         bool "sun8i (Allwinner V3s)"
 124         select CPU_V7
 125         select CPU_V7_HAS_NONSEC
 126         select CPU_V7_HAS_VIRT
 127         select ARCH_SUPPORT_PSCI
 128         select SUNXI_GEN_SUN6I
 129         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 130
 131 config MACH_SUN9I
 132         bool "sun9i (Allwinner A80)"
 133         select CPU_V7
 134         select SUNXI_HIGH_SRAM
 135         select SUNXI_GEN_SUN6I
 136         select SUPPORT_SPL
 137
 138 config MACH_SUN50I
 139         bool "sun50i (Allwinner A64)"
 140         select ARM64
 141         select DM_I2C
 142         select SUNXI_DE2
 143         select SUNXI_GEN_SUN6I
 144         select SUNXI_HIGH_SRAM
 145         select SUPPORT_SPL
 146         select FIT
 147         select SPL_LOAD_FIT
 148
 149 config MACH_SUN50I_H5
 150         bool "sun50i (Allwinner H5)"
 151         select ARM64
 152         select MACH_SUNXI_H3_H5
 153         select SUNXI_HIGH_SRAM
 154         select FIT
 155         select SPL_LOAD_FIT
 156
 157 endchoice
 158
 159 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
 160 config MACH_SUN8I
 161         bool
 162         default y if MACH_SUN8I_A23
 163         default y if MACH_SUN8I_A33
 164         default y if MACH_SUN8I_A83T
 165         default y if MACH_SUNXI_H3_H5
 166         default y if MACH_SUN8I_R40
 167         default y if MACH_SUN8I_V3S
 168
 169 config RESERVE_ALLWINNER_BOOT0_HEADER
 170         bool "reserve space for Allwinner boot0 header"
 171         select ENABLE_ARM_SOC_BOOT0_HOOK
 172         ---help---
 173         Prepend a 1536 byte (empty) header to the U-Boot image file, to be
 174         filled with magic values post build. The Allwinner provided boot0
 175         blob relies on this information to load and execute U-Boot.
 176         Only needed on 64-bit Allwinner boards so far when using boot0.
 177
 178 config ARM_BOOT_HOOK_RMR
 179         bool
 180         depends on ARM64
 181         default y
 182         select ENABLE_ARM_SOC_BOOT0_HOOK
 183         ---help---
 184         Insert some ARM32 code at the very beginning of the U-Boot binary
 185         which uses an RMR register write to bring the core into AArch64 mode.
 186         The very first instruction acts as a switch, since it's carefully
 187         chosen to be a NOP in one mode and a branch in the other, so the
 188         code would only be executed if not already in AArch64.
 189         This allows both the SPL and the U-Boot proper to be entered in
 190         either mode and switch to AArch64 if needed.
 191
 192 config DRAM_TYPE
 193         int "sunxi dram type"
 194         depends on MACH_SUN8I_A83T
 195         default 3
 196         ---help---
 197         Set the dram type, 3: DDR3, 7: LPDDR3
 198
 199 config DRAM_CLK
 200         int "sunxi dram clock speed"
 201         default 792 if MACH_SUN9I
 202         default 648 if MACH_SUN8I_R40
 203         default 312 if MACH_SUN6I || MACH_SUN8I
 204         default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 205         default 672 if MACH_SUN50I
 206         ---help---
 207         Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
 208         must be a multiple of 24. For the sun9i (A80), the tested values
 209         (for DDR3-1600) are 312 to 792.
 210
 211 if MACH_SUN5I || MACH_SUN7I
 212 config DRAM_MBUS_CLK
 213         int "sunxi mbus clock speed"
 214         default 300
 215         ---help---
 216         Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
 217
 218 endif
 219
 220 config DRAM_ZQ
 221         int "sunxi dram zq value"
 222         default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
 223         default 127 if MACH_SUN7I
 224         default 3881979 if MACH_SUN8I_R40
 225         default 4145117 if MACH_SUN9I
 226         default 3881915 if MACH_SUN50I
 227         ---help---
 228         Set the dram zq value.
 229
 230 config DRAM_ODT_EN
 231         bool "sunxi dram odt enable"
 232         default n if !MACH_SUN8I_A23
 233         default y if MACH_SUN8I_A23
 234         default y if MACH_SUN8I_R40
 235         default y if MACH_SUN50I
 236         ---help---
 237         Select this to enable dram odt (on die termination).
 238
 239 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 240 config DRAM_EMR1
 241         int "sunxi dram emr1 value"
 242         default 0 if MACH_SUN4I
 243         default 4 if MACH_SUN5I || MACH_SUN7I
 244         ---help---
 245         Set the dram controller emr1 value.
 246
 247 config DRAM_TPR3
 248         hex "sunxi dram tpr3 value"
 249         default 0
 250         ---help---
 251         Set the dram controller tpr3 parameter. This parameter configures
 252         the delay on the command lane and also phase shifts, which are
 253         applied for sampling incoming read data. The default value 0
 254         means that no phase/delay adjustments are necessary. Properly
 255         configuring this parameter increases reliability at high DRAM
 256         clock speeds.
 257
 258 config DRAM_DQS_GATING_DELAY
 259         hex "sunxi dram dqs_gating_delay value"
 260         default 0
 261         ---help---
 262         Set the dram controller dqs_gating_delay parmeter. Each byte
 263         encodes the DQS gating delay for each byte lane. The delay
 264         granularity is 1/4 cycle. For example, the value 0x05060606
 265         means that the delay is 5 quarter-cycles for one lane (1.25
 266         cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
 267         The default value 0 means autodetection. The results of hardware
 268         autodetection are not very reliable and depend on the chip
 269         temperature (sometimes producing different results on cold start
 270         and warm reboot). But the accuracy of hardware autodetection
 271         is usually good enough, unless running at really high DRAM
 272         clocks speeds (up to 600MHz). If unsure, keep as 0.
 273
 274 choice
 275         prompt "sunxi dram timings"
 276         default DRAM_TIMINGS_VENDOR_MAGIC
 277         ---help---
 278         Select the timings of the DDR3 chips.
 279
 280 config DRAM_TIMINGS_VENDOR_MAGIC
 281         bool "Magic vendor timings from Android"
 282         ---help---
 283         The same DRAM timings as in the Allwinner boot0 bootloader.
 284
 285 config DRAM_TIMINGS_DDR3_1066F_1333H
 286         bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
 287         ---help---
 288         Use the timings of the standard JEDEC DDR3-1066F speed bin for
 289         DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
 290         for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
 291         used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
 292         or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
 293         that down binning to DDR3-1066F is supported (because DDR3-1066F
 294         uses a bit faster timings than DDR3-1333H).
 295
 296 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
 297         bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
 298         ---help---
 299         Use the timings of the slowest possible JEDEC speed bin for the
 300         selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
 301         DDR3-800E, DDR3-1066G or DDR3-1333J.
 302
 303 endchoice
 304
 305 endif
 306
 307 if MACH_SUN8I_A23
 308 config DRAM_ODT_CORRECTION
 309         int "sunxi dram odt correction value"
 310         default 0
 311         ---help---
 312         Set the dram odt correction value (range -255 - 255). In allwinner
 313         fex files, this option is found in bits 8-15 of the u32 odt_en variable
 314         in the [dram] section. When bit 31 of the odt_en variable is set
 315         then the correction is negative. Usually the value for this is 0.
 316 endif
 317
 318 config SYS_CLK_FREQ
 319         default 1008000000 if MACH_SUN4I
 320         default 1008000000 if MACH_SUN5I
 321         default 1008000000 if MACH_SUN6I
 322         default 912000000 if MACH_SUN7I
 323         default 1008000000 if MACH_SUN8I
 324         default 1008000000 if MACH_SUN9I
 325         default 816000000 if MACH_SUN50I
 326
 327 config SYS_CONFIG_NAME
 328         default "sun4i" if MACH_SUN4I
 329         default "sun5i" if MACH_SUN5I
 330         default "sun6i" if MACH_SUN6I
 331         default "sun7i" if MACH_SUN7I
 332         default "sun8i" if MACH_SUN8I
 333         default "sun9i" if MACH_SUN9I
 334         default "sun50i" if MACH_SUN50I
 335
 336 config SYS_BOARD
 337         default "sunxi"
 338
 339 config SYS_SOC
 340         default "sunxi"
 341
 342 config UART0_PORT_F
 343         bool "UART0 on MicroSD breakout board"
 344         default n
 345         ---help---
 346         Repurpose the SD card slot for getting access to the UART0 serial
 347         console. Primarily useful only for low level u-boot debugging on
 348         tablets, where normal UART0 is difficult to access and requires
 349         device disassembly and/or soldering. As the SD card can't be used
 350         at the same time, the system can be only booted in the FEL mode.
 351         Only enable this if you really know what you are doing.
 352
 353 config OLD_SUNXI_KERNEL_COMPAT
 354         bool "Enable workarounds for booting old kernels"
 355         default n
 356         ---help---
 357         Set this to enable various workarounds for old kernels, this results in
 358         sub-optimal settings for newer kernels, only enable if needed.
 359
 360 config MACPWR
 361         string "MAC power pin"
 362         default ""
 363         help
 364           Set the pin used to power the MAC. This takes a string in the format
 365           understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 366
 367 config MMC0_CD_PIN
 368         string "Card detect pin for mmc0"
 369         default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
 370         default ""
 371         ---help---
 372         Set the card detect pin for mmc0, leave empty to not use cd. This
 373         takes a string in the format understood by sunxi_name_to_gpio, e.g.
 374         PH1 for pin 1 of port H.
 375
 376 config MMC1_CD_PIN
 377         string "Card detect pin for mmc1"
 378         default ""
 379         ---help---
 380         See MMC0_CD_PIN help text.
 381
 382 config MMC2_CD_PIN
 383         string "Card detect pin for mmc2"
 384         default ""
 385         ---help---
 386         See MMC0_CD_PIN help text.
 387
 388 config MMC3_CD_PIN
 389         string "Card detect pin for mmc3"
 390         default ""
 391         ---help---
 392         See MMC0_CD_PIN help text.
 393
 394 config MMC1_PINS
 395         string "Pins for mmc1"
 396         default ""
 397         ---help---
 398         Set the pins used for mmc1, when applicable. This takes a string in the
 399         format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
 400
 401 config MMC2_PINS
 402         string "Pins for mmc2"
 403         default ""
 404         ---help---
 405         See MMC1_PINS help text.
 406
 407 config MMC3_PINS
 408         string "Pins for mmc3"
 409         default ""
 410         ---help---
 411         See MMC1_PINS help text.
 412
 413 config MMC_SUNXI_SLOT_EXTRA
 414         int "mmc extra slot number"
 415         default -1
 416         ---help---
 417         sunxi builds always enable mmc0, some boards also have a second sdcard
 418         slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 419         support for this.
 420
 421 config INITIAL_USB_SCAN_DELAY
 422         int "delay initial usb scan by x ms to allow builtin devices to init"
 423         default 0
 424         ---help---
 425         Some boards have on board usb devices which need longer than the
 426         USB spec's 1 second to connect from board powerup. Set this config
 427         option to a non 0 value to add an extra delay before the first usb
 428         bus scan.
 429
 430 config USB0_VBUS_PIN
 431         string "Vbus enable pin for usb0 (otg)"
 432         default ""
 433         ---help---
 434         Set the Vbus enable pin for usb0 (otg). This takes a string in the
 435         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 436
 437 config USB0_VBUS_DET
 438         string "Vbus detect pin for usb0 (otg)"
 439         default ""
 440         ---help---
 441         Set the Vbus detect pin for usb0 (otg). This takes a string in the
 442         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 443
 444 config USB0_ID_DET
 445         string "ID detect pin for usb0 (otg)"
 446         default ""
 447         ---help---
 448         Set the ID detect pin for usb0 (otg). This takes a string in the
 449         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 450
 451 config USB1_VBUS_PIN
 452         string "Vbus enable pin for usb1 (ehci0)"
 453         default "PH6" if MACH_SUN4I || MACH_SUN7I
 454         default "PH27" if MACH_SUN6I
 455         ---help---
 456         Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
 457         a string in the format understood by sunxi_name_to_gpio, e.g.
 458         PH1 for pin 1 of port H.
 459
 460 config USB2_VBUS_PIN
 461         string "Vbus enable pin for usb2 (ehci1)"
 462         default "PH3" if MACH_SUN4I || MACH_SUN7I
 463         default "PH24" if MACH_SUN6I
 464         ---help---
 465         See USB1_VBUS_PIN help text.
 466
 467 config USB3_VBUS_PIN
 468         string "Vbus enable pin for usb3 (ehci2)"
 469         default ""
 470         ---help---
 471         See USB1_VBUS_PIN help text.
 472
 473 config I2C0_ENABLE
 474         bool "Enable I2C/TWI controller 0"
 475         default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
 476         default n if MACH_SUN6I || MACH_SUN8I
 477         select CMD_I2C
 478         ---help---
 479         This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
 480         its clock and setting up the bus. This is especially useful on devices
 481         with slaves connected to the bus or with pins exposed through e.g. an
 482         expansion port/header.
 483
 484 config I2C1_ENABLE
 485         bool "Enable I2C/TWI controller 1"
 486         default n
 487         select CMD_I2C
 488         ---help---
 489         See I2C0_ENABLE help text.
 490
 491 config I2C2_ENABLE
 492         bool "Enable I2C/TWI controller 2"
 493         default n
 494         select CMD_I2C
 495         ---help---
 496         See I2C0_ENABLE help text.
 497
 498 if MACH_SUN6I || MACH_SUN7I
 499 config I2C3_ENABLE
 500         bool "Enable I2C/TWI controller 3"
 501         default n
 502         select CMD_I2C
 503         ---help---
 504         See I2C0_ENABLE help text.
 505 endif
 506
 507 if SUNXI_GEN_SUN6I
 508 config R_I2C_ENABLE
 509         bool "Enable the PRCM I2C/TWI controller"
 510         # This is used for the pmic on H3
 511         default y if SY8106A_POWER
 512         select CMD_I2C
 513         ---help---
 514         Set this to y to enable the I2C controller which is part of the PRCM.
 515 endif
 516
 517 if MACH_SUN7I
 518 config I2C4_ENABLE
 519         bool "Enable I2C/TWI controller 4"
 520         default n
 521         select CMD_I2C
 522         ---help---
 523         See I2C0_ENABLE help text.
 524 endif
 525
 526 config AXP_GPIO
 527         bool "Enable support for gpio-s on axp PMICs"
 528         default n
 529         ---help---
 530         Say Y here to enable support for the gpio pins of the axp PMIC ICs.
 531
 532 config VIDEO
 533         bool "Enable graphical uboot console on HDMI, LCD or VGA"
 534         depends on !MACH_SUN8I_A83T
 535         depends on !MACH_SUNXI_H3_H5
 536         depends on !MACH_SUN8I_R40
 537         depends on !MACH_SUN8I_V3S
 538         depends on !MACH_SUN9I
 539         depends on !MACH_SUN50I
 540         default y
 541         ---help---
 542         Say Y here to add support for using a cfb console on the HDMI, LCD
 543         or VGA output found on most sunxi devices. See doc/README.video for
 544         info on how to select the video output and mode.
 545
 546 config VIDEO_HDMI
 547         bool "HDMI output support"
 548         depends on VIDEO && !MACH_SUN8I
 549         default y
 550         ---help---
 551         Say Y here to add support for outputting video over HDMI.
 552
 553 config VIDEO_VGA
 554         bool "VGA output support"
 555         depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
 556         default n
 557         ---help---
 558         Say Y here to add support for outputting video over VGA.
 559
 560 config VIDEO_VGA_VIA_LCD
 561         bool "VGA via LCD controller support"
 562         depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
 563         default n
 564         ---help---
 565         Say Y here to add support for external DACs connected to the parallel
 566         LCD interface driving a VGA connector, such as found on the
 567         Olimex A13 boards.
 568
 569 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
 570         bool "Force sync active high for VGA via LCD controller support"
 571         depends on VIDEO_VGA_VIA_LCD
 572         default n
 573         ---help---
 574         Say Y here if you've a board which uses opendrain drivers for the vga
 575         hsync and vsync signals. Opendrain drivers cannot generate steep enough
 576         positive edges for a stable video output, so on boards with opendrain
 577         drivers the sync signals must always be active high.
 578
 579 config VIDEO_VGA_EXTERNAL_DAC_EN
 580         string "LCD panel power enable pin"
 581         depends on VIDEO_VGA_VIA_LCD
 582         default ""
 583         ---help---
 584         Set the enable pin for the external VGA DAC. This takes a string in the
 585         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 586
 587 config VIDEO_COMPOSITE
 588         bool "Composite video output support"
 589         depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
 590         default n
 591         ---help---
 592         Say Y here to add support for outputting composite video.
 593
 594 config VIDEO_LCD_MODE
 595         string "LCD panel timing details"
 596         depends on VIDEO
 597         default ""
 598         ---help---
 599         LCD panel timing details string, leave empty if there is no LCD panel.
 600         This is in drivers/video/videomodes.c: video_get_params() format, e.g.
 601         x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
 602         Also see: http://linux-sunxi.org/LCD
 603
 604 config VIDEO_LCD_DCLK_PHASE
 605         int "LCD panel display clock phase"
 606         depends on VIDEO
 607         default 1
 608         ---help---
 609         Select LCD panel display clock phase shift, range 0-3.
 610
 611 config VIDEO_LCD_POWER
 612         string "LCD panel power enable pin"
 613         depends on VIDEO
 614         default ""
 615         ---help---
 616         Set the power enable pin for the LCD panel. This takes a string in the
 617         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 618
 619 config VIDEO_LCD_RESET
 620         string "LCD panel reset pin"
 621         depends on VIDEO
 622         default ""
 623         ---help---
 624         Set the reset pin for the LCD panel. This takes a string in the format
 625         understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 626
 627 config VIDEO_LCD_BL_EN
 628         string "LCD panel backlight enable pin"
 629         depends on VIDEO
 630         default ""
 631         ---help---
 632         Set the backlight enable pin for the LCD panel. This takes a string in the
 633         the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
 634         port H.
 635
 636 config VIDEO_LCD_BL_PWM
 637         string "LCD panel backlight pwm pin"
 638         depends on VIDEO
 639         default ""
 640         ---help---
 641         Set the backlight pwm pin for the LCD panel. This takes a string in the
 642         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 643
 644 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
 645         bool "LCD panel backlight pwm is inverted"
 646         depends on VIDEO
 647         default y
 648         ---help---
 649         Set this if the backlight pwm output is active low.
 650
 651 config VIDEO_LCD_PANEL_I2C
 652         bool "LCD panel needs to be configured via i2c"
 653         depends on VIDEO
 654         default n
 655         select CMD_I2C
 656         ---help---
 657         Say y here if the LCD panel needs to be configured via i2c. This
 658         will add a bitbang i2c controller using gpios to talk to the LCD.
 659
 660 config VIDEO_LCD_PANEL_I2C_SDA
 661         string "LCD panel i2c interface SDA pin"
 662         depends on VIDEO_LCD_PANEL_I2C
 663         default "PG12"
 664         ---help---
 665         Set the SDA pin for the LCD i2c interface. This takes a string in the
 666         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 667
 668 config VIDEO_LCD_PANEL_I2C_SCL
 669         string "LCD panel i2c interface SCL pin"
 670         depends on VIDEO_LCD_PANEL_I2C
 671         default "PG10"
 672         ---help---
 673         Set the SCL pin for the LCD i2c interface. This takes a string in the
 674         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 675
 676
 677 # Note only one of these may be selected at a time! But hidden choices are
 678 # not supported by Kconfig
 679 config VIDEO_LCD_IF_PARALLEL
 680         bool
 681
 682 config VIDEO_LCD_IF_LVDS
 683         bool
 684
 685 config SUNXI_DE2
 686         bool
 687         default n
 688
 689 config VIDEO_DE2
 690         bool "Display Engine 2 video driver"
 691         depends on SUNXI_DE2
 692         select DM_VIDEO
 693         select DISPLAY
 694         default y
 695         ---help---
 696         Say y here if you want to build DE2 video driver which is present on
 697         newer SoCs. Currently only HDMI output is supported.
 698
 699
 700 choice
 701         prompt "LCD panel support"
 702         depends on VIDEO
 703         ---help---
 704         Select which type of LCD panel to support.
 705
 706 config VIDEO_LCD_PANEL_PARALLEL
 707         bool "Generic parallel interface LCD panel"
 708         select VIDEO_LCD_IF_PARALLEL
 709
 710 config VIDEO_LCD_PANEL_LVDS
 711         bool "Generic lvds interface LCD panel"
 712         select VIDEO_LCD_IF_LVDS
 713
 714 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
 715         bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
 716         select VIDEO_LCD_SSD2828
 717         select VIDEO_LCD_IF_PARALLEL
 718         ---help---
 719         7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
 720
 721 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
 722         bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
 723         select VIDEO_LCD_ANX9804
 724         select VIDEO_LCD_IF_PARALLEL
 725         select VIDEO_LCD_PANEL_I2C
 726         ---help---
 727         Select this for eDP LCD panels with 4 lanes running at 1.62G,
 728         connected via an ANX9804 bridge chip.
 729
 730 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
 731         bool "Hitachi tx18d42vm LCD panel"
 732         select VIDEO_LCD_HITACHI_TX18D42VM
 733         select VIDEO_LCD_IF_LVDS
 734         ---help---
 735         7.85" 1024x768 Hitachi tx18d42vm LCD panel support
 736
 737 config VIDEO_LCD_TL059WV5C0
 738         bool "tl059wv5c0 LCD panel"
 739         select VIDEO_LCD_PANEL_I2C
 740         select VIDEO_LCD_IF_PARALLEL
 741         ---help---
 742         6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
 743         Aigo M60/M608/M606 tablets.
 744
 745 endchoice
 746
 747 config SATAPWR
 748         string "SATA power pin"
 749         default ""
 750         help
 751           Set the pins used to power the SATA. This takes a string in the
 752           format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
 753           port H.
 754
 755 config GMAC_TX_DELAY
 756         int "GMAC Transmit Clock Delay Chain"
 757         default 0
 758         ---help---
 759         Set the GMAC Transmit Clock Delay Chain value.
 760
 761 config SPL_STACK_R_ADDR
 762         default 0x4fe00000 if MACH_SUN4I
 763         default 0x4fe00000 if MACH_SUN5I
 764         default 0x4fe00000 if MACH_SUN6I
 765         default 0x4fe00000 if MACH_SUN7I
 766         default 0x4fe00000 if MACH_SUN8I
 767         default 0x2fe00000 if MACH_SUN9I
 768         default 0x4fe00000 if MACH_SUN50I
 769
 770 endif