arch/arm/mach-sunxi/clock_sun8i_a83t.c

   1 /*
   2  * A83 specific clock code
   3  *
   4  * (C) Copyright 2007-2012
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/prcm.h>
  17 #include <asm/arch/sys_proto.h>
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 void clock_init_safe(void)
  21 {
  22         struct sunxi_ccm_reg * const ccm =
  23                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  24
  25         clock_set_pll1(408000000);
  26         /* enable pll_hsic, default is 480M */
  27         writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg);
  28         writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg);
  29         while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {}
  30
  31         /* switch to default 24MHz before changing to hsic */
  32         writel(0x0, &ccm->cci400_cfg);
  33         sdelay(50);
  34         writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg);
  35         sdelay(100);
  36
  37         /* switch before changing pll6 */
  38         clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK,
  39                         AHB1_CLK_SRC_OSC24M);
  40         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  41         while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {}
  42
  43         writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
  44         writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset);
  45         writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg);
  46
  47         /* timestamp */
  48         writel(1, 0x01720000);
  49 }
  50 #endif
  51
  52 void clock_init_uart(void)
  53 {
  54         struct sunxi_ccm_reg *const ccm =
  55                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  56
  57         /* uart clock source is apb2 */
  58         writel(APB2_CLK_SRC_OSC24M|
  59                APB2_CLK_RATE_N_1|
  60                APB2_CLK_RATE_M(1),
  61                &ccm->apb2_div);
  62
  63         /* open the clock for uart */
  64         setbits_le32(&ccm->apb2_gate,
  65                      CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
  66                                        CONFIG_CONS_INDEX - 1));
  67
  68         /* deassert uart reset */
  69         setbits_le32(&ccm->apb2_reset_cfg,
  70                      1 << (APB2_RESET_UART_SHIFT +
  71                            CONFIG_CONS_INDEX - 1));
  72 }
  73
  74 #ifdef CONFIG_SPL_BUILD
  75 void clock_set_pll1(unsigned int clk)
  76 {
  77         struct sunxi_ccm_reg * const ccm =
  78                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  79         const int p = 0;
  80
  81         /* Switch to 24MHz clock while changing PLL1 */
  82         writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
  83                 AXI_DIV_2 << AXI1_DIV_SHIFT |
  84                 CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT |
  85                 CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT,
  86                &ccm->cpu_axi_cfg);
  87
  88         /* clk = 24*n/p, p is ignored if clock is >288MHz */
  89         writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
  90                 CCM_PLL1_CTRL_N(clk / 24000000),
  91                 &ccm->pll1_c0_cfg);
  92         while (!(readl(&ccm->pll_stable_status) & 0x01)) {}
  93
  94         writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
  95                 CCM_PLL1_CTRL_N(clk / (24000000)),
  96                 &ccm->pll1_c1_cfg);
  97         while (!(readl(&ccm->pll_stable_status) & 0x02)) {}
  98
  99         /* Switch CPU to PLL1 */
 100         writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
 101                 AXI_DIV_2 << AXI1_DIV_SHIFT |
 102                 CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT |
 103                 CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT,
 104                &ccm->cpu_axi_cfg);
 105 }
 106 #endif
 107
 108 void clock_set_pll5(unsigned int clk)
 109 {
 110         struct sunxi_ccm_reg * const ccm =
 111                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 112         unsigned int div1 = 0, div2 = 0;
 113
 114         /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */
 115         writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
 116                         CCM_PLL5_CTRL_N(clk / (24000000)) |
 117                         div2 << CCM_PLL5_DIV2_SHIFT |
 118                         div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg);
 119
 120         udelay(5500);
 121 }
 122
 123
 124 unsigned int clock_get_pll6(void)
 125 {
 126         struct sunxi_ccm_reg *const ccm =
 127                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 128
 129         uint32_t rval = readl(&ccm->pll6_cfg);
 130         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
 131         int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
 132                         CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
 133         int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
 134                         CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
 135         return 24000000 * n / div1 / div2;
 136 }