2 * (C) Copyright 2010-2015
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra AP (Application Processor) code */
11 #include <linux/bug.h>
13 #include <asm/arch/gp_padctrl.h>
14 #include <asm/arch/mc.h>
15 #include <asm/arch-tegra/ap.h>
16 #include <asm/arch-tegra/clock.h>
17 #include <asm/arch-tegra/fuse.h>
18 #include <asm/arch-tegra/pmc.h>
19 #include <asm/arch-tegra/scu.h>
20 #include <asm/arch-tegra/tegra.h>
21 #include <asm/arch-tegra/warmboot.h>
23 int tegra_get_chip(void)
26 struct apb_misc_gp_ctlr
*gp
=
27 (struct apb_misc_gp_ctlr
*)NV_PA_APB_MISC_GP_BASE
;
30 * This is undocumented, Chip ID is bits 15:8 of the register
31 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
32 * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
34 rev
= (readl(&gp
->hidrev
) & HIDREV_CHIPID_MASK
) >> HIDREV_CHIPID_SHIFT
;
35 debug("%s: CHIPID is 0x%02X\n", __func__
, rev
);
40 int tegra_get_sku_info(void)
43 struct fuse_regs
*fuse
= (struct fuse_regs
*)NV_PA_FUSE_BASE
;
45 sku_id
= readl(&fuse
->sku_info
) & 0xff;
46 debug("%s: SKU info byte is 0x%02X\n", __func__
, sku_id
);
51 int tegra_get_chip_sku(void)
55 chip_id
= tegra_get_chip();
56 sku_id
= tegra_get_sku_info();
76 case SKU_ID_TM30MQS_P_A3
:
86 return TEGRA_SOC_T114
;
93 return TEGRA_SOC_T124
;
100 return TEGRA_SOC_T210
;
105 /* unknown chip/sku id */
106 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
107 __func__
, chip_id
, sku_id
);
108 return TEGRA_SOC_UNKNOWN
;
112 static void enable_scu(void)
114 struct scu_ctlr
*scu
= (struct scu_ctlr
*)NV_PA_ARM_PERIPHBASE
;
117 /* Only enable the SCU on T20/T25 */
118 if (tegra_get_chip() != CHIPID_TEGRA20
)
121 /* If SCU already setup/enabled, return */
122 if (readl(&scu
->scu_ctrl
) & SCU_CTRL_ENABLE
)
125 /* Invalidate all ways for all processors */
126 writel(0xFFFF, &scu
->scu_inv_all
);
128 /* Enable SCU - bit 0 */
129 reg
= readl(&scu
->scu_ctrl
);
130 reg
|= SCU_CTRL_ENABLE
;
131 writel(reg
, &scu
->scu_ctrl
);
134 static u32
get_odmdata(void)
137 * ODMDATA is stored in the BCT in IRAM by the BootROM.
138 * The BCT start and size are stored in the BIT in IRAM.
139 * Read the data @ bct_start + (bct_size - 12). This works
140 * on BCTs for currently supported SoCs, which are locked down.
141 * If this changes in new chips, we can revisit this algorithm.
143 unsigned long bct_start
;
146 bct_start
= readl(NV_PA_BASE_SRAM
+ NVBOOTINFOTABLE_BCTPTR
);
147 odmdata
= readl(bct_start
+ BCT_ODMDATA_OFFSET
);
152 static void init_pmc_scratch(void)
154 struct pmc_ctlr
*const pmc
= (struct pmc_ctlr
*)NV_PA_PMC_BASE
;
158 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
159 for (i
= 0; i
< 23; i
++)
160 writel(0, &pmc
->pmc_scratch1
+i
);
162 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
163 odmdata
= get_odmdata();
164 writel(odmdata
, &pmc
->pmc_scratch20
);
167 #ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
168 void protect_secure_section(void)
170 struct mc_ctlr
*mc
= (struct mc_ctlr
*)NV_PA_MC_BASE
;
172 /* Must be MB aligned */
173 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE
& 0xFFFFF);
174 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE
& 0xFFFFF);
176 writel(CONFIG_ARMV7_SECURE_BASE
, &mc
->mc_security_cfg0
);
177 writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE
>> 20, &mc
->mc_security_cfg1
);
181 #if defined(CONFIG_ARMV7_NONSEC)
182 static void smmu_flush(struct mc_ctlr
*mc
)
184 (void)readl(&mc
->mc_smmu_config
);
187 static void smmu_enable(void)
189 struct mc_ctlr
*mc
= (struct mc_ctlr
*)NV_PA_MC_BASE
;
193 * Enable translation for all clients since access to this register
194 * is restricted to TrustZone-secured requestors. The kernel will use
195 * the per-SWGROUP enable bits to enable or disable translations.
197 writel(0xffffffff, &mc
->mc_smmu_translation_enable_0
);
198 writel(0xffffffff, &mc
->mc_smmu_translation_enable_1
);
199 writel(0xffffffff, &mc
->mc_smmu_translation_enable_2
);
200 writel(0xffffffff, &mc
->mc_smmu_translation_enable_3
);
203 * Enable SMMU globally since access to this register is restricted
204 * to TrustZone-secured requestors.
206 value
= readl(&mc
->mc_smmu_config
);
207 value
|= TEGRA_MC_SMMU_CONFIG_ENABLE
;
208 writel(value
, &mc
->mc_smmu_config
);
213 static void smmu_enable(void)
220 /* Init PMC scratch memory */