2 * (C) Copyright 2013-2015
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra210 Clock control functions */
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sysctr.h>
15 #include <asm/arch/tegra.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
22 * Clock types that we can use as a source. The Tegra210 has muxes for the
23 * peripheral clocks, and in most cases there are four options for the clock
24 * source. This gives us a clock 'type' and exploits what commonality exists
27 * Letters are obvious, except for T which means CLK_M, and S which means the
28 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
29 * datasheet) and PLL_M are different things. The former is the basic
30 * clock supplied to the SOC from an external oscillator. The latter is the
33 * See definitions in clock_id in the header file.
36 CLOCK_TYPE_AXPT
, /* PLL_A, PLL_X, PLL_P, CLK_M */
37 CLOCK_TYPE_MCPA
, /* and so on */
51 CLOCK_TYPE_PC2CC3M_T16
, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
54 CLOCK_TYPE_MCPTM2C2C3
,
56 CLOCK_TYPE_AC2CC3P_TS2
,
57 CLOCK_TYPE_PC01C00_C42C41TC40
,
60 CLOCK_TYPE_NONE
= -1, /* invalid clock type */
64 CLOCK_MAX_MUX
= 8 /* number of source options for each clock */
68 * Clock source mux for each clock type. This just converts our enum into
69 * a list of mux sources for use by the code.
72 * The extra column in each clock source array is used to store the mask
73 * bits in its register for the source.
75 #define CLK(x) CLOCK_ID_ ## x
76 static enum clock_id clock_source
[CLOCK_TYPE_COUNT
][CLOCK_MAX_MUX
+1] = {
77 { CLK(AUDIO
), CLK(XCPU
), CLK(PERIPH
), CLK(OSC
),
78 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
80 { CLK(MEMORY
), CLK(CGENERAL
), CLK(PERIPH
), CLK(AUDIO
),
81 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
83 { CLK(MEMORY
), CLK(CGENERAL
), CLK(PERIPH
), CLK(OSC
),
84 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
86 { CLK(PERIPH
), CLK(CGENERAL
), CLK(MEMORY
), CLK(NONE
),
87 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
89 { CLK(PERIPH
), CLK(CGENERAL
), CLK(MEMORY
), CLK(OSC
),
90 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
92 { CLK(PERIPH
), CLK(DISPLAY
), CLK(CGENERAL
), CLK(OSC
),
93 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
95 { CLK(AUDIO
), CLK(CGENERAL
), CLK(PERIPH
), CLK(OSC
),
96 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
98 { CLK(AUDIO
), CLK(SFROM32KHZ
), CLK(PERIPH
), CLK(OSC
),
99 CLK(EPCI
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
101 { CLK(PERIPH
), CLK(MEMORY
), CLK(DISPLAY
), CLK(AUDIO
),
102 CLK(CGENERAL
), CLK(DISPLAY2
), CLK(OSC
), CLK(NONE
),
104 { CLK(PERIPH
), CLK(CGENERAL
), CLK(SFROM32KHZ
), CLK(OSC
),
105 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
108 { CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
109 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
112 /* Additional clock types on Tegra114+ */
113 /* CLOCK_TYPE_PC2CC3M */
114 { CLK(PERIPH
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
115 CLK(MEMORY
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
117 /* CLOCK_TYPE_PC2CC3S_T */
118 { CLK(PERIPH
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
119 CLK(SFROM32KHZ
), CLK(NONE
), CLK(OSC
), CLK(NONE
),
121 /* CLOCK_TYPE_PC2CC3M_T */
122 { CLK(PERIPH
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
123 CLK(MEMORY
), CLK(NONE
), CLK(OSC
), CLK(NONE
),
125 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
126 { CLK(PERIPH
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
127 CLK(MEMORY
), CLK(NONE
), CLK(OSC
), CLK(NONE
),
129 /* CLOCK_TYPE_MC2CC3P_A */
130 { CLK(MEMORY
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
131 CLK(PERIPH
), CLK(NONE
), CLK(AUDIO
), CLK(NONE
),
134 { CLK(MEMORY
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
135 CLK(NONE
), CLK(NONE
), CLK(NONE
), CLK(NONE
),
137 /* CLOCK_TYPE_MCPTM2C2C3 */
138 { CLK(MEMORY
), CLK(CGENERAL
), CLK(PERIPH
), CLK(OSC
),
139 CLK(MEMORY2
), CLK(CGENERAL2
), CLK(CGENERAL3
), CLK(NONE
),
141 /* CLOCK_TYPE_PC2CC3T_S */
142 { CLK(PERIPH
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
143 CLK(OSC
), CLK(NONE
), CLK(SFROM32KHZ
), CLK(NONE
),
145 /* CLOCK_TYPE_AC2CC3P_TS2 */
146 { CLK(AUDIO
), CLK(CGENERAL2
), CLK(CGENERAL
), CLK(CGENERAL3
),
147 CLK(PERIPH
), CLK(NONE
), CLK(OSC
), CLK(SRC2
),
149 /* CLOCK_TYPE_PC01C00_C42C41TC40 */
150 { CLK(PERIPH
), CLK(CGENERAL_1
), CLK(CGENERAL_0
), CLK(NONE
),
151 CLK(CGENERAL4_2
), CLK(CGENERAL4_1
), CLK(OSC
), CLK(CGENERAL4_0
),
156 * Clock type for each peripheral clock source. We put the name in each
157 * record just so it is easy to match things up
159 #define TYPE(name, type) type
160 static enum clock_type_id clock_periph_type
[PERIPHC_COUNT
] = {
162 TYPE(PERIPHC_I2S2
, CLOCK_TYPE_AXPT
),
163 TYPE(PERIPHC_I2S3
, CLOCK_TYPE_AXPT
),
164 TYPE(PERIPHC_SPDIF_OUT
, CLOCK_TYPE_AXPT
),
165 TYPE(PERIPHC_SPDIF_IN
, CLOCK_TYPE_PC2CC3M
),
166 TYPE(PERIPHC_PWM
, CLOCK_TYPE_PC2CC3S_T
),
167 TYPE(PERIPHC_05h
, CLOCK_TYPE_NONE
),
168 TYPE(PERIPHC_SBC2
, CLOCK_TYPE_PC2CC3M_T
),
169 TYPE(PERIPHC_SBC3
, CLOCK_TYPE_PC2CC3M_T
),
172 TYPE(PERIPHC_08h
, CLOCK_TYPE_NONE
),
173 TYPE(PERIPHC_I2C1
, CLOCK_TYPE_PC2CC3M_T16
),
174 TYPE(PERIPHC_I2C5
, CLOCK_TYPE_PC2CC3M_T16
),
175 TYPE(PERIPHC_0bh
, CLOCK_TYPE_NONE
),
176 TYPE(PERIPHC_0ch
, CLOCK_TYPE_NONE
),
177 TYPE(PERIPHC_SBC1
, CLOCK_TYPE_PC2CC3M_T
),
178 TYPE(PERIPHC_DISP1
, CLOCK_TYPE_PMDACD2T
),
179 TYPE(PERIPHC_DISP2
, CLOCK_TYPE_PMDACD2T
),
182 TYPE(PERIPHC_10h
, CLOCK_TYPE_NONE
),
183 TYPE(PERIPHC_11h
, CLOCK_TYPE_NONE
),
184 TYPE(PERIPHC_VI
, CLOCK_TYPE_MC2CC3P_A
),
185 TYPE(PERIPHC_13h
, CLOCK_TYPE_NONE
),
186 TYPE(PERIPHC_SDMMC1
, CLOCK_TYPE_PC2CC3M_T
),
187 TYPE(PERIPHC_SDMMC2
, CLOCK_TYPE_PC2CC3M_T
),
188 TYPE(PERIPHC_16h
, CLOCK_TYPE_NONE
),
189 TYPE(PERIPHC_17h
, CLOCK_TYPE_NONE
),
192 TYPE(PERIPHC_18h
, CLOCK_TYPE_NONE
),
193 TYPE(PERIPHC_SDMMC4
, CLOCK_TYPE_PC2CC3M_T
),
194 TYPE(PERIPHC_VFIR
, CLOCK_TYPE_PC2CC3M_T
),
195 TYPE(PERIPHC_1Bh
, CLOCK_TYPE_NONE
),
196 TYPE(PERIPHC_1Ch
, CLOCK_TYPE_NONE
),
197 TYPE(PERIPHC_HSI
, CLOCK_TYPE_PC2CC3M_T
),
198 TYPE(PERIPHC_UART1
, CLOCK_TYPE_PC2CC3M_T
),
199 TYPE(PERIPHC_UART2
, CLOCK_TYPE_PC2CC3M_T
),
202 TYPE(PERIPHC_HOST1X
, CLOCK_TYPE_MC2CC3P_A
),
203 TYPE(PERIPHC_21h
, CLOCK_TYPE_NONE
),
204 TYPE(PERIPHC_22h
, CLOCK_TYPE_NONE
),
205 TYPE(PERIPHC_23h
, CLOCK_TYPE_NONE
),
206 TYPE(PERIPHC_24h
, CLOCK_TYPE_NONE
),
207 TYPE(PERIPHC_25h
, CLOCK_TYPE_NONE
),
208 TYPE(PERIPHC_I2C2
, CLOCK_TYPE_PC2CC3M_T16
),
209 TYPE(PERIPHC_EMC
, CLOCK_TYPE_MCPTM2C2C3
),
212 TYPE(PERIPHC_UART3
, CLOCK_TYPE_PC2CC3M_T
),
213 TYPE(PERIPHC_29h
, CLOCK_TYPE_NONE
),
214 TYPE(PERIPHC_VI_SENSOR
, CLOCK_TYPE_MC2CC3P_A
),
215 TYPE(PERIPHC_2bh
, CLOCK_TYPE_NONE
),
216 TYPE(PERIPHC_2ch
, CLOCK_TYPE_NONE
),
217 TYPE(PERIPHC_SBC4
, CLOCK_TYPE_PC2CC3M_T
),
218 TYPE(PERIPHC_I2C3
, CLOCK_TYPE_PC2CC3M_T16
),
219 TYPE(PERIPHC_SDMMC3
, CLOCK_TYPE_PC2CC3M_T
),
222 TYPE(PERIPHC_UART4
, CLOCK_TYPE_PC2CC3M_T
),
223 TYPE(PERIPHC_UART5
, CLOCK_TYPE_PC2CC3M_T
),
224 TYPE(PERIPHC_VDE
, CLOCK_TYPE_PC2CC3M_T
),
225 TYPE(PERIPHC_OWR
, CLOCK_TYPE_PC2CC3M_T
),
226 TYPE(PERIPHC_NOR
, CLOCK_TYPE_PC2CC3M_T
),
227 TYPE(PERIPHC_CSITE
, CLOCK_TYPE_PC2CC3M_T
),
228 TYPE(PERIPHC_I2S1
, CLOCK_TYPE_AXPT
),
229 TYPE(PERIPHC_DTV
, CLOCK_TYPE_NONE
),
232 TYPE(PERIPHC_38h
, CLOCK_TYPE_NONE
),
233 TYPE(PERIPHC_39h
, CLOCK_TYPE_NONE
),
234 TYPE(PERIPHC_3ah
, CLOCK_TYPE_NONE
),
235 TYPE(PERIPHC_3bh
, CLOCK_TYPE_NONE
),
236 TYPE(PERIPHC_MSENC
, CLOCK_TYPE_MC2CC3P_A
),
237 TYPE(PERIPHC_TSEC
, CLOCK_TYPE_PC2CC3M_T
),
238 TYPE(PERIPHC_3eh
, CLOCK_TYPE_NONE
),
239 TYPE(PERIPHC_OSC
, CLOCK_TYPE_NONE
),
242 TYPE(PERIPHC_40h
, CLOCK_TYPE_NONE
), /* start with 0x3b0 */
243 TYPE(PERIPHC_MSELECT
, CLOCK_TYPE_PC2CC3M_T
),
244 TYPE(PERIPHC_TSENSOR
, CLOCK_TYPE_PC2CC3T_S
),
245 TYPE(PERIPHC_I2S4
, CLOCK_TYPE_AXPT
),
246 TYPE(PERIPHC_I2S5
, CLOCK_TYPE_AXPT
),
247 TYPE(PERIPHC_I2C4
, CLOCK_TYPE_PC2CC3M_T16
),
248 TYPE(PERIPHC_SBC5
, CLOCK_TYPE_PC2CC3M_T
),
249 TYPE(PERIPHC_SBC6
, CLOCK_TYPE_PC2CC3M_T
),
252 TYPE(PERIPHC_AUDIO
, CLOCK_TYPE_AC2CC3P_TS2
),
253 TYPE(PERIPHC_49h
, CLOCK_TYPE_NONE
),
254 TYPE(PERIPHC_4ah
, CLOCK_TYPE_NONE
),
255 TYPE(PERIPHC_4bh
, CLOCK_TYPE_NONE
),
256 TYPE(PERIPHC_4ch
, CLOCK_TYPE_NONE
),
257 TYPE(PERIPHC_HDA2CODEC2X
, CLOCK_TYPE_PC2CC3M_T
),
258 TYPE(PERIPHC_ACTMON
, CLOCK_TYPE_PC2CC3S_T
),
259 TYPE(PERIPHC_EXTPERIPH1
, CLOCK_TYPE_ASPTE
),
262 TYPE(PERIPHC_EXTPERIPH2
, CLOCK_TYPE_ASPTE
),
263 TYPE(PERIPHC_EXTPERIPH3
, CLOCK_TYPE_ASPTE
),
264 TYPE(PERIPHC_52h
, CLOCK_TYPE_NONE
),
265 TYPE(PERIPHC_I2CSLOW
, CLOCK_TYPE_PC2CC3S_T
),
266 TYPE(PERIPHC_SYS
, CLOCK_TYPE_NONE
),
267 TYPE(PERIPHC_55h
, CLOCK_TYPE_NONE
),
268 TYPE(PERIPHC_56h
, CLOCK_TYPE_NONE
),
269 TYPE(PERIPHC_57h
, CLOCK_TYPE_NONE
),
272 TYPE(PERIPHC_58h
, CLOCK_TYPE_NONE
),
273 TYPE(PERIPHC_59h
, CLOCK_TYPE_NONE
),
274 TYPE(PERIPHC_5ah
, CLOCK_TYPE_NONE
),
275 TYPE(PERIPHC_5bh
, CLOCK_TYPE_NONE
),
276 TYPE(PERIPHC_SATAOOB
, CLOCK_TYPE_PCMT
),
277 TYPE(PERIPHC_SATA
, CLOCK_TYPE_PCMT
),
278 TYPE(PERIPHC_HDA
, CLOCK_TYPE_PC2CC3M_T
),
279 TYPE(PERIPHC_5fh
, CLOCK_TYPE_NONE
),
282 TYPE(PERIPHC_XUSB_CORE_HOST
, CLOCK_TYPE_NONE
),
283 TYPE(PERIPHC_XUSB_FALCON
, CLOCK_TYPE_NONE
),
284 TYPE(PERIPHC_XUSB_FS
, CLOCK_TYPE_NONE
),
285 TYPE(PERIPHC_XUSB_CORE_DEV
, CLOCK_TYPE_NONE
),
286 TYPE(PERIPHC_XUSB_SS
, CLOCK_TYPE_NONE
),
287 TYPE(PERIPHC_CILAB
, CLOCK_TYPE_NONE
),
288 TYPE(PERIPHC_CILCD
, CLOCK_TYPE_NONE
),
289 TYPE(PERIPHC_CILE
, CLOCK_TYPE_NONE
),
292 TYPE(PERIPHC_DSIA_LP
, CLOCK_TYPE_NONE
),
293 TYPE(PERIPHC_DSIB_LP
, CLOCK_TYPE_NONE
),
294 TYPE(PERIPHC_ENTROPY
, CLOCK_TYPE_NONE
),
295 TYPE(PERIPHC_DVFS_REF
, CLOCK_TYPE_NONE
),
296 TYPE(PERIPHC_DVFS_SOC
, CLOCK_TYPE_NONE
),
297 TYPE(PERIPHC_TRACECLKIN
, CLOCK_TYPE_NONE
),
298 TYPE(PERIPHC_6eh
, CLOCK_TYPE_NONE
),
299 TYPE(PERIPHC_6fh
, CLOCK_TYPE_NONE
),
302 TYPE(PERIPHC_EMC_LATENCY
, CLOCK_TYPE_NONE
),
303 TYPE(PERIPHC_SOC_THERM
, CLOCK_TYPE_NONE
),
304 TYPE(PERIPHC_72h
, CLOCK_TYPE_NONE
),
305 TYPE(PERIPHC_73h
, CLOCK_TYPE_NONE
),
306 TYPE(PERIPHC_74h
, CLOCK_TYPE_NONE
),
307 TYPE(PERIPHC_75h
, CLOCK_TYPE_NONE
),
308 TYPE(PERIPHC_VI_SENSOR2
, CLOCK_TYPE_NONE
),
309 TYPE(PERIPHC_I2C6
, CLOCK_TYPE_PC2CC3M_T16
),
312 TYPE(PERIPHC_78h
, CLOCK_TYPE_NONE
),
313 TYPE(PERIPHC_EMC_DLL
, CLOCK_TYPE_MCPTM2C2C3
),
314 TYPE(PERIPHC_7ah
, CLOCK_TYPE_NONE
),
315 TYPE(PERIPHC_CLK72MHZ
, CLOCK_TYPE_NONE
),
316 TYPE(PERIPHC_7ch
, CLOCK_TYPE_NONE
),
317 TYPE(PERIPHC_7dh
, CLOCK_TYPE_NONE
),
318 TYPE(PERIPHC_VIC
, CLOCK_TYPE_NONE
),
319 TYPE(PERIPHC_7Fh
, CLOCK_TYPE_NONE
),
322 TYPE(PERIPHC_SDMMC_LEGACY_TM
, CLOCK_TYPE_NONE
),
323 TYPE(PERIPHC_NVDEC
, CLOCK_TYPE_NONE
),
324 TYPE(PERIPHC_NVJPG
, CLOCK_TYPE_NONE
),
325 TYPE(PERIPHC_NVENC
, CLOCK_TYPE_NONE
),
326 TYPE(PERIPHC_84h
, CLOCK_TYPE_NONE
),
327 TYPE(PERIPHC_85h
, CLOCK_TYPE_NONE
),
328 TYPE(PERIPHC_86h
, CLOCK_TYPE_NONE
),
329 TYPE(PERIPHC_87h
, CLOCK_TYPE_NONE
),
332 TYPE(PERIPHC_88h
, CLOCK_TYPE_NONE
),
333 TYPE(PERIPHC_89h
, CLOCK_TYPE_NONE
),
334 TYPE(PERIPHC_DMIC3
, CLOCK_TYPE_NONE
),
335 TYPE(PERIPHC_APE
, CLOCK_TYPE_NONE
),
336 TYPE(PERIPHC_QSPI
, CLOCK_TYPE_PC01C00_C42C41TC40
),
337 TYPE(PERIPHC_VI_I2C
, CLOCK_TYPE_NONE
),
338 TYPE(PERIPHC_USB2_HSIC_TRK
, CLOCK_TYPE_NONE
),
339 TYPE(PERIPHC_PEX_SATA_USB_RX_BYP
, CLOCK_TYPE_NONE
),
342 TYPE(PERIPHC_MAUD
, CLOCK_TYPE_NONE
),
343 TYPE(PERIPHC_TSECB
, CLOCK_TYPE_NONE
),
347 * This array translates a periph_id to a periphc_internal_id
349 * Not present/matched up:
350 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
351 * SPDIF - which is both 0x08 and 0x0c
354 #define NONE(name) (-1)
355 #define OFFSET(name, value) PERIPHC_ ## name
356 #define INTERNAL_ID(id) (id & 0x000000ff)
357 static s8 periph_id_to_internal_id
[PERIPH_ID_COUNT
] = {
366 PERIPHC_UART2
, /* and vfir 0x68 */
398 /* Middle word: 63:32 */
410 PERIPHC_SBC1
, /* SBCx = SPIx */
438 /* Upper word 95:64 */
598 /* Y: 192 (192 - 223) */
600 PERIPHC_SDMMC_LEGACY_TM
,
604 PERIPHC_DMIC3
, /* 197 */
605 PERIPHC_APE
, /* 198 */
619 PERIPHC_VI_I2C
, /* 208 */
622 PERIPHC_QSPI
, /* 211 */
632 PERIPHC_NVENC
, /* 219 */
640 * PLL divider shift/mask tables for all PLL IDs.
642 struct clk_pll_info tegra_pll_info_table
[CLOCK_ID_PLL_COUNT
] = {
644 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLC, etc.)
645 * If lock_ena or lock_det are >31, they're not used in that PLL (PLLC, etc.)
647 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 10, .n_mask
= 0xFF, .p_shift
= 20, .p_mask
= 0x1F,
648 .lock_ena
= 32, .lock_det
= 27, .kcp_shift
= 0, .kcp_mask
= 0, .kvco_shift
= 0, .kvco_mask
= 0 }, /* PLLC */
649 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 8, .n_mask
= 0xFF, .p_shift
= 20, .p_mask
= 0x1F,
650 .lock_ena
= 4, .lock_det
= 27, .kcp_shift
= 1, .kcp_mask
= 3, .kvco_shift
= 0, .kvco_mask
= 1 }, /* PLLM */
651 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 10, .n_mask
= 0xFF, .p_shift
= 20, .p_mask
= 0x1F,
652 .lock_ena
= 18, .lock_det
= 27, .kcp_shift
= 0, .kcp_mask
= 3, .kvco_shift
= 2, .kvco_mask
= 1 }, /* PLLP */
653 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 8, .n_mask
= 0xFF, .p_shift
= 20, .p_mask
= 0x1F,
654 .lock_ena
= 28, .lock_det
= 27, .kcp_shift
= 25, .kcp_mask
= 3, .kvco_shift
= 24, .kvco_mask
= 1 }, /* PLLA */
655 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 8, .n_mask
= 0xFF, .p_shift
= 16, .p_mask
= 0x1F,
656 .lock_ena
= 29, .lock_det
= 27, .kcp_shift
= 25, .kcp_mask
= 3, .kvco_shift
= 24, .kvco_mask
= 1 }, /* PLLU */
657 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 11, .n_mask
= 0xFF, .p_shift
= 20, .p_mask
= 0x07,
658 .lock_ena
= 18, .lock_det
= 27, .kcp_shift
= 23, .kcp_mask
= 3, .kvco_shift
= 22, .kvco_mask
= 1 }, /* PLLD */
659 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 8, .n_mask
= 0xFF, .p_shift
= 20, .p_mask
= 0x1F,
660 .lock_ena
= 18, .lock_det
= 27, .kcp_shift
= 1, .kcp_mask
= 3, .kvco_shift
= 0, .kvco_mask
= 1 }, /* PLLX */
661 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 8, .n_mask
= 0xFF, .p_shift
= 0, .p_mask
= 0,
662 .lock_ena
= 9, .lock_det
= 11, .kcp_shift
= 6, .kcp_mask
= 3, .kvco_shift
= 0, .kvco_mask
= 1 }, /* PLLE */
663 { .m_shift
= 0, .m_mask
= 0, .n_shift
= 0, .n_mask
= 0, .p_shift
= 0, .p_mask
= 0,
664 .lock_ena
= 0, .lock_det
= 0, .kcp_shift
= 0, .kcp_mask
= 0, .kvco_shift
= 0, .kvco_mask
= 0 }, /* PLLS (gone)*/
665 { .m_shift
= 0, .m_mask
= 0xFF, .n_shift
= 8, .n_mask
= 0xFF, .p_shift
= 19, .p_mask
= 0x1F,
666 .lock_ena
= 30, .lock_det
= 27, .kcp_shift
= 25, .kcp_mask
= 3, .kvco_shift
= 24, .kvco_mask
= 1 }, /* PLLDP */
670 * Get the oscillator frequency, from the corresponding hardware configuration
671 * field. Note that Tegra30+ support 3 new higher freqs, but we map back
672 * to the old T20 freqs. Support for the higher oscillators is TBD.
674 enum clock_osc_freq
clock_get_osc_freq(void)
676 struct clk_rst_ctlr
*clkrst
=
677 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
680 reg
= readl(&clkrst
->crc_osc_ctrl
);
681 reg
= (reg
& OSC_FREQ_MASK
) >> OSC_FREQ_SHIFT
;
683 * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz,
684 * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz
687 debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg
);
688 /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */
693 * Map to most common (T20) freqs (except 38.4, handled above):
694 * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3
699 /* Returns a pointer to the clock source register for a peripheral */
700 u32
*get_periph_source_reg(enum periph_id periph_id
)
702 struct clk_rst_ctlr
*clkrst
=
703 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
704 enum periphc_internal_id internal_id
;
706 /* Coresight is a special case */
707 if (periph_id
== PERIPH_ID_CSI
)
708 return &clkrst
->crc_clk_src
[PERIPH_ID_CSI
+1];
710 assert(periph_id
>= PERIPH_ID_FIRST
&& periph_id
< PERIPH_ID_COUNT
);
711 internal_id
= INTERNAL_ID(periph_id_to_internal_id
[periph_id
]);
712 assert(internal_id
!= -1);
714 if (internal_id
< PERIPHC_VW_FIRST
)
716 return &clkrst
->crc_clk_src
[internal_id
];
718 if (internal_id
< PERIPHC_X_FIRST
) {
720 internal_id
-= PERIPHC_VW_FIRST
;
721 return &clkrst
->crc_clk_src_vw
[internal_id
];
724 if (internal_id
< PERIPHC_Y_FIRST
) {
726 internal_id
-= PERIPHC_X_FIRST
;
727 return &clkrst
->crc_clk_src_x
[internal_id
];
731 internal_id
-= PERIPHC_Y_FIRST
;
732 return &clkrst
->crc_clk_src_y
[internal_id
];
736 * Given a peripheral ID and the required source clock, this returns which
737 * value should be programmed into the source mux for that peripheral.
739 * There is special code here to handle the one source type with 5 sources.
741 * @param periph_id peripheral to start
742 * @param source PLL id of required parent clock
743 * @param mux_bits Set to number of bits in mux register: 2 or 4
744 * @param divider_bits Set to number of divider bits (8 or 16)
745 * @return mux value (0-4, or -1 if not found)
747 int get_periph_clock_source(enum periph_id periph_id
,
748 enum clock_id parent
, int *mux_bits
, int *divider_bits
)
750 enum clock_type_id type
;
751 enum periphc_internal_id internal_id
;
754 assert(clock_periph_id_isvalid(periph_id
));
756 internal_id
= INTERNAL_ID(periph_id_to_internal_id
[periph_id
]);
757 assert(periphc_internal_id_isvalid(internal_id
));
759 type
= clock_periph_type
[internal_id
];
760 assert(clock_type_id_isvalid(type
));
762 *mux_bits
= clock_source
[type
][CLOCK_MAX_MUX
];
764 if (type
== CLOCK_TYPE_PC2CC3M_T16
)
769 for (mux
= 0; mux
< CLOCK_MAX_MUX
; mux
++)
770 if (clock_source
[type
][mux
] == parent
)
773 /* if we get here, either us or the caller has made a mistake */
774 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id
,
779 void clock_set_enable(enum periph_id periph_id
, int enable
)
781 struct clk_rst_ctlr
*clkrst
=
782 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
786 /* Enable/disable the clock to this peripheral */
787 assert(clock_periph_id_isvalid(periph_id
));
788 if ((int)periph_id
< (int)PERIPH_ID_VW_FIRST
)
789 clk
= &clkrst
->crc_clk_out_enb
[PERIPH_REG(periph_id
)];
790 else if ((int)periph_id
< (int)PERIPH_ID_X_FIRST
)
791 clk
= &clkrst
->crc_clk_out_enb_vw
[PERIPH_REG(periph_id
)];
792 else if ((int)periph_id
< (int)PERIPH_ID_Y_FIRST
)
793 clk
= &clkrst
->crc_clk_out_enb_x
;
795 clk
= &clkrst
->crc_clk_out_enb_y
;
799 reg
|= PERIPH_MASK(periph_id
);
801 reg
&= ~PERIPH_MASK(periph_id
);
805 void reset_set_enable(enum periph_id periph_id
, int enable
)
807 struct clk_rst_ctlr
*clkrst
=
808 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
812 /* Enable/disable reset to the peripheral */
813 assert(clock_periph_id_isvalid(periph_id
));
814 if (periph_id
< PERIPH_ID_VW_FIRST
)
815 reset
= &clkrst
->crc_rst_dev
[PERIPH_REG(periph_id
)];
816 else if ((int)periph_id
< (int)PERIPH_ID_X_FIRST
)
817 reset
= &clkrst
->crc_rst_dev_vw
[PERIPH_REG(periph_id
)];
818 else if ((int)periph_id
< (int)PERIPH_ID_Y_FIRST
)
819 reset
= &clkrst
->crc_rst_devices_x
;
821 reset
= &clkrst
->crc_rst_devices_y
;
825 reg
|= PERIPH_MASK(periph_id
);
827 reg
&= ~PERIPH_MASK(periph_id
);
831 #ifdef CONFIG_OF_CONTROL
833 * Convert a device tree clock ID to our peripheral ID. They are mostly
834 * the same but we are very cautious so we check that a valid clock ID is
837 * @param clk_id Clock ID according to tegra210 device tree binding
838 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
840 enum periph_id
clk_id_to_periph_id(int clk_id
)
842 if (clk_id
> PERIPH_ID_COUNT
)
843 return PERIPH_ID_NONE
;
846 case PERIPH_ID_RESERVED4
:
847 case PERIPH_ID_RESERVED25
:
848 case PERIPH_ID_RESERVED35
:
849 case PERIPH_ID_RESERVED36
:
850 case PERIPH_ID_RESERVED38
:
851 case PERIPH_ID_RESERVED43
:
852 case PERIPH_ID_RESERVED49
:
853 case PERIPH_ID_RESERVED53
:
854 case PERIPH_ID_RESERVED64
:
855 case PERIPH_ID_RESERVED84
:
856 case PERIPH_ID_RESERVED85
:
857 case PERIPH_ID_RESERVED86
:
858 case PERIPH_ID_RESERVED88
:
859 case PERIPH_ID_RESERVED90
:
860 case PERIPH_ID_RESERVED92
:
861 case PERIPH_ID_RESERVED93
:
862 case PERIPH_ID_RESERVED94
:
863 case PERIPH_ID_V_RESERVED2
:
864 case PERIPH_ID_V_RESERVED4
:
865 case PERIPH_ID_V_RESERVED17
:
866 case PERIPH_ID_V_RESERVED18
:
867 case PERIPH_ID_V_RESERVED19
:
868 case PERIPH_ID_V_RESERVED20
:
869 case PERIPH_ID_V_RESERVED21
:
870 case PERIPH_ID_V_RESERVED22
:
871 case PERIPH_ID_W_RESERVED2
:
872 case PERIPH_ID_W_RESERVED3
:
873 case PERIPH_ID_W_RESERVED4
:
874 case PERIPH_ID_W_RESERVED5
:
875 case PERIPH_ID_W_RESERVED6
:
876 case PERIPH_ID_W_RESERVED7
:
877 case PERIPH_ID_W_RESERVED9
:
878 case PERIPH_ID_W_RESERVED10
:
879 case PERIPH_ID_W_RESERVED11
:
880 case PERIPH_ID_W_RESERVED12
:
881 case PERIPH_ID_W_RESERVED13
:
882 case PERIPH_ID_W_RESERVED15
:
883 case PERIPH_ID_W_RESERVED16
:
884 case PERIPH_ID_W_RESERVED17
:
885 case PERIPH_ID_W_RESERVED18
:
886 case PERIPH_ID_W_RESERVED19
:
887 case PERIPH_ID_W_RESERVED20
:
888 case PERIPH_ID_W_RESERVED23
:
889 case PERIPH_ID_W_RESERVED29
:
890 case PERIPH_ID_W_RESERVED30
:
891 case PERIPH_ID_W_RESERVED31
:
892 return PERIPH_ID_NONE
;
897 #endif /* CONFIG_OF_CONTROL */
900 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
901 * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM.
903 void tegra210_setup_pllp(void)
905 struct clk_rst_ctlr
*clkrst
= (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
908 /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */
911 /* Assert RSTN before enable */
912 reg
= PLLP_OUT1_RSTN_EN
;
913 writel(reg
, &clkrst
->crc_pll
[CLOCK_ID_PERIPH
].pll_out
[0]);
914 /* Set divisor and reenable */
915 reg
= (IN_408_OUT_9_6_DIVISOR
<< PLLP_OUT1_RATIO
)
916 | PLLP_OUT1_OVR
| PLLP_OUT1_CLKEN
| PLLP_OUT1_RSTN_DIS
;
917 writel(reg
, &clkrst
->crc_pll
[CLOCK_ID_PERIPH
].pll_out
[0]);
920 /* Assert RSTN before enable */
921 reg
= PLLP_OUT4_RSTN_EN
| PLLP_OUT3_RSTN_EN
;
922 writel(reg
, &clkrst
->crc_pll
[CLOCK_ID_PERIPH
].pll_out
[1]);
923 /* Set divisor and reenable */
924 reg
= (IN_408_OUT_204_DIVISOR
<< PLLP_OUT4_RATIO
)
925 | PLLP_OUT4_OVR
| PLLP_OUT4_CLKEN
| PLLP_OUT4_RSTN_DIS
926 | (IN_408_OUT_102_DIVISOR
<< PLLP_OUT3_RATIO
)
927 | PLLP_OUT3_OVR
| PLLP_OUT3_CLKEN
| PLLP_OUT3_RSTN_DIS
;
928 writel(reg
, &clkrst
->crc_pll
[CLOCK_ID_PERIPH
].pll_out
[1]);
931 * NOTE: If you want to change PLLP_OUT2 away from 204MHz,
932 * you can change PLLP_BASE DIVP here. Currently defaults
933 * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz.
934 * See Table 13 in section 5.1.4 in T210 TRM for more info.
938 void clock_early_init(void)
940 struct clk_rst_ctlr
*clkrst
=
941 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
942 struct clk_pll_info
*pllinfo
= &tegra_pll_info_table
[CLOCK_ID_DISPLAY
];
945 tegra210_setup_pllp();
948 * PLLC output frequency set to 600Mhz
949 * PLLD output frequency set to 925Mhz
951 switch (clock_get_osc_freq()) {
952 case CLOCK_OSC_FREQ_12_0
: /* OSC is 12Mhz */
953 clock_set_rate(CLOCK_ID_CGENERAL
, 600, 12, 0, 8);
954 clock_set_rate(CLOCK_ID_DISPLAY
, 925, 12, 0, 12);
957 case CLOCK_OSC_FREQ_26_0
: /* OSC is 26Mhz */
958 clock_set_rate(CLOCK_ID_CGENERAL
, 600, 26, 0, 8);
959 clock_set_rate(CLOCK_ID_DISPLAY
, 925, 26, 0, 12);
962 case CLOCK_OSC_FREQ_13_0
: /* OSC is 13Mhz */
963 clock_set_rate(CLOCK_ID_CGENERAL
, 600, 13, 0, 8);
964 clock_set_rate(CLOCK_ID_DISPLAY
, 925, 13, 0, 12);
966 case CLOCK_OSC_FREQ_19_2
:
967 clock_set_rate(CLOCK_ID_CGENERAL
, 125, 4, 0, 0);
968 clock_set_rate(CLOCK_ID_DISPLAY
, 96, 2, 0, 12);
970 case CLOCK_OSC_FREQ_38_4
:
971 clock_set_rate(CLOCK_ID_CGENERAL
, 125, 8, 0, 0);
972 clock_set_rate(CLOCK_ID_DISPLAY
, 96, 4, 0, 0);
976 * These are not supported. It is too early to print a
977 * message and the UART likely won't work anyway due to the
978 * oscillator being wrong.
983 /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */
984 clrbits_le32(&clkrst
->crc_pll
[CLOCK_ID_CGENERAL
].pll_misc
,
989 * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps
992 clrbits_le32(&clkrst
->crc_pll
[CLOCK_ID_CGENERAL
].pll_out
[1],
996 /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */
997 data
= (1 << PLLD_ENABLE_CLK
) | (1 << pllinfo
->lock_ena
);
998 writel(data
, &clkrst
->crc_pll
[CLOCK_ID_DISPLAY
].pll_misc
);
1002 unsigned int clk_m_get_rate(unsigned parent_rate
)
1004 struct clk_rst_ctlr
*clkrst
= (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
1007 value
= readl(&clkrst
->crc_spare_reg0
);
1008 div
= ((value
>> 2) & 0x3) + 1;
1010 return parent_rate
/ div
;
1013 void arch_timer_init(void)
1015 struct sysctr_ctlr
*sysctr
= (struct sysctr_ctlr
*)NV_PA_TSC_BASE
;
1018 freq
= clock_get_rate(CLOCK_ID_CLK_M
);
1019 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__
, freq
, freq
);
1021 if (current_el() == 3)
1022 asm("msr cntfrq_el0, %0\n" : : "r" (freq
));
1024 /* Only Tegra114+ has the System Counter regs */
1025 debug("%s: setting CNTFID0 to 0x%08X\n", __func__
, freq
);
1026 writel(freq
, &sysctr
->cntfid0
);
1028 val
= readl(&sysctr
->cntcr
);
1029 val
|= TSC_CNTCR_ENABLE
| TSC_CNTCR_HDBG
;
1030 writel(val
, &sysctr
->cntcr
);
1031 debug("%s: TSC CNTCR = 0x%08X\n", __func__
, val
);
1034 #define PLLREFE_MISC 0x4c8
1035 #define PLLREFE_MISC_LOCK BIT(27)
1036 #define PLLREFE_MISC_IDDQ BIT(24)
1038 #define PLLREFE_BASE 0x4c4
1039 #define PLLREFE_BASE_BYPASS BIT(31)
1040 #define PLLREFE_BASE_ENABLE BIT(30)
1041 #define PLLREFE_BASE_REF_DIS BIT(29)
1042 #define PLLREFE_BASE_KCP(kcp) (((kcp) & 0x3) << 27)
1043 #define PLLREFE_BASE_KVCO BIT(26)
1044 #define PLLREFE_BASE_DIVP(p) (((p) & 0x1f) << 16)
1045 #define PLLREFE_BASE_DIVN(n) (((n) & 0xff) << 8)
1046 #define PLLREFE_BASE_DIVM(m) (((m) & 0xff) << 0)
1048 static int tegra_pllref_enable(void)
1051 unsigned long start
;
1054 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
1055 * Recovery Mode or Boot from USB", sub-section "PLLREFE".
1058 value
= readl(NV_PA_CLK_RST_BASE
+ PLLREFE_MISC
);
1059 value
&= ~PLLREFE_MISC_IDDQ
;
1060 writel(value
, NV_PA_CLK_RST_BASE
+ PLLREFE_MISC
);
1064 value
= PLLREFE_BASE_ENABLE
|
1065 PLLREFE_BASE_KCP(0) |
1066 PLLREFE_BASE_DIVP(0) |
1067 PLLREFE_BASE_DIVN(0x41) |
1068 PLLREFE_BASE_DIVM(4);
1069 writel(value
, NV_PA_CLK_RST_BASE
+ PLLREFE_BASE
);
1071 debug("waiting for pllrefe lock\n");
1072 start
= get_timer(0);
1073 while (get_timer(start
) < 250) {
1074 value
= readl(NV_PA_CLK_RST_BASE
+ PLLREFE_MISC
);
1075 if (value
& PLLREFE_MISC_LOCK
)
1078 if (!(value
& PLLREFE_MISC_LOCK
)) {
1079 debug(" timeout\n");
1087 #define PLLE_SS_CNTL 0x68
1088 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
1089 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
1090 #define PLLE_SS_CNTL_SSCINVERT (1 << 15)
1091 #define PLLE_SS_CNTL_SSCCENTER (1 << 14)
1092 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
1093 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
1094 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
1095 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
1097 #define PLLE_BASE 0x0e8
1098 #define PLLE_BASE_ENABLE (1 << 31)
1099 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0x1f) << 24)
1100 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
1101 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
1103 #define PLLE_MISC 0x0ec
1104 #define PLLE_MISC_IDDQ_SWCTL (1 << 14)
1105 #define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13)
1106 #define PLLE_MISC_LOCK (1 << 11)
1107 #define PLLE_PTS (1 << 8)
1108 #define PLLE_MISC_KCP(x) (((x) & 0x3) << 6)
1109 #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
1110 #define PLLE_MISC_KVCO (1 << 0)
1112 #define PLLE_AUX 0x48c
1113 #define PLLE_AUX_SS_SEQ_INCLUDE (1 << 31)
1114 #define PLLE_AUX_REF_SEL_PLLREFE (1 << 28)
1115 #define PLLE_AUX_SEQ_ENABLE (1 << 24)
1116 #define PLLE_AUX_SS_SWCTL (1 << 6)
1117 #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
1118 #define PLLE_AUX_USE_LOCKDET (1 << 3)
1120 int tegra_plle_enable(void)
1123 unsigned long start
;
1125 /* PLLREF feeds PLLE */
1126 tegra_pllref_enable();
1129 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
1130 * Recovery Mode or Boot from USB", sub-section "PLLEs".
1133 /* 1. Select XTAL as the source */
1135 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_AUX
);
1136 value
&= ~PLLE_AUX_REF_SEL_PLLREFE
;
1137 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_AUX
);
1139 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_MISC
);
1140 value
&= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE
;
1141 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_MISC
);
1147 * 3. Program the following registers to generate a low jitter 100MHz
1151 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_BASE
);
1152 value
&= ~PLLE_BASE_PLDIV_CML(0x1f);
1153 value
&= ~PLLE_BASE_NDIV(0xff);
1154 value
&= ~PLLE_BASE_MDIV(0xff);
1155 value
|= PLLE_BASE_PLDIV_CML(0xe);
1156 value
|= PLLE_BASE_NDIV(0x7d);
1157 value
|= PLLE_BASE_MDIV(2);
1158 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_BASE
);
1160 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_MISC
);
1162 value
&= ~PLLE_MISC_KCP(3);
1163 value
&= ~PLLE_MISC_VREG_CTRL(3);
1164 value
&= ~PLLE_MISC_KVCO
;
1165 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_MISC
);
1167 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_BASE
);
1168 value
|= PLLE_BASE_ENABLE
;
1169 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_BASE
);
1171 /* 4. Wait for LOCK */
1173 debug("waiting for plle lock\n");
1174 start
= get_timer(0);
1175 while (get_timer(start
) < 250) {
1176 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_MISC
);
1177 if (value
& PLLE_MISC_LOCK
)
1180 if (!(value
& PLLE_MISC_LOCK
)) {
1181 debug(" timeout\n");
1188 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_SS_CNTL
);
1189 value
&= ~PLLE_SS_CNTL_SSCINC(0xff);
1190 value
|= PLLE_SS_CNTL_SSCINC(1);
1191 value
&= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
1192 value
|= PLLE_SS_CNTL_SSCINCINTR(0x23);
1193 value
&= ~PLLE_SS_CNTL_SSCMAX(0x1fff);
1194 value
|= PLLE_SS_CNTL_SSCMAX(0x21);
1195 value
&= ~PLLE_SS_CNTL_SSCINVERT
;
1196 value
&= ~PLLE_SS_CNTL_SSCCENTER
;
1197 value
&= ~PLLE_SS_CNTL_BYPASS_SS
;
1198 value
&= ~PLLE_SS_CNTL_SSCBYP
;
1199 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_SS_CNTL
);
1201 /* 6. Wait 300 ns */
1204 value
&= ~PLLE_SS_CNTL_INTERP_RESET
;
1205 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_SS_CNTL
);
1207 /* 7. Enable HW power sequencer for PLLE */
1209 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_MISC
);
1210 value
&= ~PLLE_MISC_IDDQ_SWCTL
;
1211 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_MISC
);
1213 value
= readl(NV_PA_CLK_RST_BASE
+ PLLE_AUX
);
1214 value
&= ~PLLE_AUX_SS_SWCTL
;
1215 value
&= ~PLLE_AUX_ENABLE_SWCTL
;
1216 value
|= PLLE_AUX_SS_SEQ_INCLUDE
;
1217 value
|= PLLE_AUX_USE_LOCKDET
;
1218 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_AUX
);
1223 value
|= PLLE_AUX_SEQ_ENABLE
;
1224 writel(value
, NV_PA_CLK_RST_BASE
+ PLLE_AUX
);
1229 struct periph_clk_init periph_clk_init_table
[] = {
1230 { PERIPH_ID_SBC1
, CLOCK_ID_PERIPH
},
1231 { PERIPH_ID_SBC2
, CLOCK_ID_PERIPH
},
1232 { PERIPH_ID_SBC3
, CLOCK_ID_PERIPH
},
1233 { PERIPH_ID_SBC4
, CLOCK_ID_PERIPH
},
1234 { PERIPH_ID_SBC5
, CLOCK_ID_PERIPH
},
1235 { PERIPH_ID_SBC6
, CLOCK_ID_PERIPH
},
1236 { PERIPH_ID_HOST1X
, CLOCK_ID_PERIPH
},
1237 { PERIPH_ID_DISP1
, CLOCK_ID_CGENERAL
},
1238 { PERIPH_ID_SDMMC1
, CLOCK_ID_PERIPH
},
1239 { PERIPH_ID_SDMMC2
, CLOCK_ID_PERIPH
},
1240 { PERIPH_ID_SDMMC3
, CLOCK_ID_PERIPH
},
1241 { PERIPH_ID_SDMMC4
, CLOCK_ID_PERIPH
},
1242 { PERIPH_ID_PWM
, CLOCK_ID_SFROM32KHZ
},
1243 { PERIPH_ID_I2C1
, CLOCK_ID_PERIPH
},
1244 { PERIPH_ID_I2C2
, CLOCK_ID_PERIPH
},
1245 { PERIPH_ID_I2C3
, CLOCK_ID_PERIPH
},
1246 { PERIPH_ID_I2C4
, CLOCK_ID_PERIPH
},
1247 { PERIPH_ID_I2C5
, CLOCK_ID_PERIPH
},
1248 { PERIPH_ID_I2C6
, CLOCK_ID_PERIPH
},