arch/arm/mach-tegra/tegra210/xusb-padctl.c

   1 /*
   2  * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * SPDX-License-Identifier: GPL-2.0
   5  */
   6
   7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
   8
   9 #include <common.h>
  10 #include <errno.h>
  11 #include <fdtdec.h>
  12 #include <malloc.h>
  13
  14 #include <asm/io.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch-tegra/xusb-padctl.h>
  18
  19 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  20
  21 struct tegra_xusb_phy_ops {
  22         int (*prepare)(struct tegra_xusb_phy *phy);
  23         int (*enable)(struct tegra_xusb_phy *phy);
  24         int (*disable)(struct tegra_xusb_phy *phy);
  25         int (*unprepare)(struct tegra_xusb_phy *phy);
  26 };
  27
  28 struct tegra_xusb_phy {
  29         const struct tegra_xusb_phy_ops *ops;
  30
  31         struct tegra_xusb_padctl *padctl;
  32 };
  33
  34 struct tegra_xusb_padctl {
  35         struct fdt_resource regs;
  36
  37         unsigned int enable;
  38
  39         struct tegra_xusb_phy phys[2];
  40 };
  41
  42 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
  43                                unsigned long offset)
  44 {
  45         u32 value = readl(padctl->regs.start + offset);
  46         debug("padctl: %08lx > %08x\n", offset, value);
  47         return value;
  48 }
  49
  50 static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
  51                                  u32 value, unsigned long offset)
  52 {
  53         debug("padctl: %08lx < %08x\n", offset, value);
  54         writel(value, padctl->regs.start + offset);
  55 }
  56
  57 #define XUSB_PADCTL_ELPG_PROGRAM 0x024
  58 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
  59 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
  60 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
  61
  62 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
  63 {
  64         u32 value;
  65
  66         if (padctl->enable++ > 0)
  67                 return 0;
  68
  69         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  70         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
  71         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  72
  73         udelay(100);
  74
  75         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  76         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
  77         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  78
  79         udelay(100);
  80
  81         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  82         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
  83         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  84
  85         return 0;
  86 }
  87
  88 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
  89 {
  90         u32 value;
  91
  92         if (padctl->enable == 0) {
  93                 error("unbalanced enable/disable");
  94                 return 0;
  95         }
  96
  97         if (--padctl->enable > 0)
  98                 return 0;
  99
 100         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 101         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
 102         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 103
 104         udelay(100);
 105
 106         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 107         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
 108         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 109
 110         udelay(100);
 111
 112         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 113         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
 114         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 115
 116         return 0;
 117 }
 118
 119 static int phy_prepare(struct tegra_xusb_phy *phy)
 120 {
 121         int err;
 122
 123         err = tegra_xusb_padctl_enable(phy->padctl);
 124         if (err < 0)
 125                 return err;
 126
 127         reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
 128
 129         return 0;
 130 }
 131
 132 static int phy_unprepare(struct tegra_xusb_phy *phy)
 133 {
 134         reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
 135
 136         return tegra_xusb_padctl_disable(phy->padctl);
 137 }
 138
 139 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
 140 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
 141 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
 142 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
 143 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
 144 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
 145 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
 146 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
 147 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
 148 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
 149
 150 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
 151 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
 152 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
 153 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
 154 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
 155 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
 156
 157 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
 158 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
 159 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
 160 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
 161 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
 162 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
 163
 164 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
 165 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
 166 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
 167
 168 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
 169 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
 170 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
 171 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
 172 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
 173
 174 #define CLK_RST_XUSBIO_PLL_CFG0 0x51c
 175 #define  CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
 176 #define  CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
 177 #define  CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
 178 #define  CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
 179 #define  CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
 180
 181 static int pcie_phy_enable(struct tegra_xusb_phy *phy)
 182 {
 183         struct tegra_xusb_padctl *padctl = phy->padctl;
 184         unsigned long start;
 185         u32 value;
 186
 187         debug("> %s(phy=%p)\n", __func__, phy);
 188
 189         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 190         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
 191         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
 192         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 193
 194         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
 195         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
 196         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
 197         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
 198
 199         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 200         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
 201         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 202
 203         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 204         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
 205         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 206
 207         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 208         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
 209         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 210
 211         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 212         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
 213         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
 214         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
 215         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
 216         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 217
 218         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 219         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
 220         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
 221         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
 222         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 223
 224         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 225         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
 226         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 227
 228         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 229         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
 230         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 231
 232         udelay(1);
 233
 234         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 235         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
 236         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 237
 238         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 239         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
 240         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 241
 242         debug("  waiting for calibration\n");
 243
 244         start = get_timer(0);
 245
 246         while (get_timer(start) < 250) {
 247                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 248                 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
 249                         break;
 250         }
 251
 252         debug("  done\n");
 253
 254         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 255         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
 256         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 257
 258         debug("  waiting for calibration to stop\n");
 259
 260         start = get_timer(0);
 261
 262         while (get_timer(start) < 250) {
 263                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 264                 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
 265                         break;
 266         }
 267
 268         debug("  done\n");
 269
 270         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 271         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
 272         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 273
 274         debug("  waiting for PLL to lock...\n");
 275         start = get_timer(0);
 276
 277         while (get_timer(start) < 250) {
 278                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 279                 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
 280                         break;
 281         }
 282
 283         debug("  done\n");
 284
 285         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 286         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
 287         value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
 288         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 289
 290         debug("  waiting for register calibration...\n");
 291         start = get_timer(0);
 292
 293         while (get_timer(start) < 250) {
 294                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 295                 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
 296                         break;
 297         }
 298
 299         debug("  done\n");
 300
 301         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 302         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
 303         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 304
 305         debug("  waiting for register calibration to stop...\n");
 306         start = get_timer(0);
 307
 308         while (get_timer(start) < 250) {
 309                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 310                 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
 311                         break;
 312         }
 313
 314         debug("  done\n");
 315
 316         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 317         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
 318         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 319
 320         value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
 321         value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
 322         value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
 323         value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
 324         value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
 325         writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
 326
 327         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 328         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
 329         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 330
 331         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 332         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
 333         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 334
 335         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 336         value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
 337         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 338
 339         udelay(1);
 340
 341         value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
 342         value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
 343         writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
 344
 345         debug("< %s()\n", __func__);
 346         return 0;
 347 }
 348
 349 static int pcie_phy_disable(struct tegra_xusb_phy *phy)
 350 {
 351         return 0;
 352 }
 353
 354 static const struct tegra_xusb_phy_ops pcie_phy_ops = {
 355         .prepare = phy_prepare,
 356         .enable = pcie_phy_enable,
 357         .disable = pcie_phy_disable,
 358         .unprepare = phy_unprepare,
 359 };
 360
 361 static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
 362         .phys = {
 363                 [0] = {
 364                         .ops = &pcie_phy_ops,
 365                 },
 366         },
 367 };
 368
 369 static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
 370                                       const void *fdt, int node)
 371 {
 372         int err;
 373
 374         err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
 375         if (err < 0) {
 376                 error("registers not found");
 377                 return err;
 378         }
 379
 380         debug("regs: %pa-%pa\n", &padctl->regs.start,
 381               &padctl->regs.end);
 382
 383         return 0;
 384 }
 385
 386 static int process_nodes(const void *fdt, int nodes[], unsigned int count)
 387 {
 388         unsigned int i;
 389         int err;
 390
 391         debug("> %s(fdt=%p, nodes=%p, count=%u)\n", __func__, fdt, nodes,
 392               count);
 393
 394         for (i = 0; i < count; i++) {
 395                 enum fdt_compat_id id;
 396
 397                 if (!fdtdec_get_is_enabled(fdt, nodes[i]))
 398                         continue;
 399
 400                 id = fdtdec_lookup(fdt, nodes[i]);
 401                 switch (id) {
 402                 case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
 403                 case COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL:
 404                         break;
 405
 406                 default:
 407                         error("unsupported compatible: %s",
 408                               fdtdec_get_compatible(id));
 409                         continue;
 410                 }
 411
 412                 err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
 413                 if (err < 0) {
 414                         error("failed to parse DT: %d",
 415                               err);
 416                         continue;
 417                 }
 418
 419                 /* deassert XUSB padctl reset */
 420                 reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
 421
 422                 /* only a single instance is supported */
 423                 break;
 424         }
 425
 426         debug("< %s()\n", __func__);
 427         return 0;
 428 }
 429
 430 struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
 431 {
 432         struct tegra_xusb_phy *phy = NULL;
 433
 434         switch (type) {
 435         case TEGRA_XUSB_PADCTL_PCIE:
 436                 phy = &padctl->phys[0];
 437                 phy->padctl = padctl;
 438                 break;
 439         }
 440
 441         return phy;
 442 }
 443
 444 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
 445 {
 446         if (phy && phy->ops && phy->ops->prepare)
 447                 return phy->ops->prepare(phy);
 448
 449         return phy ? -ENOSYS : -EINVAL;
 450 }
 451
 452 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
 453 {
 454         if (phy && phy->ops && phy->ops->enable)
 455                 return phy->ops->enable(phy);
 456
 457         return phy ? -ENOSYS : -EINVAL;
 458 }
 459
 460 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
 461 {
 462         if (phy && phy->ops && phy->ops->disable)
 463                 return phy->ops->disable(phy);
 464
 465         return phy ? -ENOSYS : -EINVAL;
 466 }
 467
 468 int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
 469 {
 470         if (phy && phy->ops && phy->ops->unprepare)
 471                 return phy->ops->unprepare(phy);
 472
 473         return phy ? -ENOSYS : -EINVAL;
 474 }
 475
 476 void tegra_xusb_padctl_init(const void *fdt)
 477 {
 478         int count, nodes[1];
 479
 480         debug("> %s(fdt=%p)\n", __func__, fdt);
 481
 482         count = fdtdec_find_aliases_for_id(fdt, "padctl",
 483                                            COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
 484                                            nodes, ARRAY_SIZE(nodes));
 485         if (process_nodes(fdt, nodes, count))
 486                 return;
 487
 488         count = fdtdec_find_aliases_for_id(fdt, "padctl",
 489                                            COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
 490                                            nodes, ARRAY_SIZE(nodes));
 491         if (process_nodes(fdt, nodes, count))
 492                 return;
 493
 494         debug("< %s()\n", __func__);
 495 }