arch/arm/mach-uniphier/clk/clk-ld11.c

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <spl.h>
   9 #include <linux/bitops.h>
  10 #include <linux/io.h>
  11
  12 #include "../init.h"
  13 #include "../sc64-regs.h"
  14 #include "../sg-regs.h"
  15
  16 #define SDCTRL_EMMC_HW_RESET    0x59810280
  17
  18 void uniphier_ld11_clk_init(void)
  19 {
  20         /* if booted from a device other than USB, without stand-by MPU */
  21         if ((readl(SG_PINMON0) & BIT(27)) &&
  22             uniphier_boot_device_raw() != BOOT_DEVICE_USB) {
  23                 writel(1, SG_ETPHYPSHUT);
  24                 writel(1, SG_ETPHYCNT);
  25
  26                 udelay(1); /* wait for regulator level 1.1V -> 2.5V */
  27
  28                 writel(3, SG_ETPHYCNT);
  29                 writel(3, SG_ETPHYPSHUT);
  30                 writel(7, SG_ETPHYCNT);
  31         }
  32
  33         /* TODO: use "mmc-pwrseq-emmc" */
  34         writel(1, SDCTRL_EMMC_HW_RESET);
  35
  36 #ifdef CONFIG_USB_EHCI_HCD
  37         {
  38                 /* FIXME: the current clk driver can not handle parents */
  39                 u32 tmp;
  40                 int ch;
  41
  42                 tmp = readl(SC_CLKCTRL4);
  43                 tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
  44                 writel(tmp, SC_CLKCTRL4);
  45
  46                 for (ch = 0; ch < 3; ch++) {
  47                         void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL;
  48
  49                         writel(0x82280600, phyctrl + 8 * ch);
  50                         writel(0x00000106, phyctrl + 8 * ch + 4);
  51                 }
  52         }
  53 #endif
  54 }