arch/m68k/cpu/mcf5227x/cpu_init.c

   1 /*
   2  *
   3  * (C) Copyright 2000-2003
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
   7  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <watchdog.h>
  14
  15 #include <asm/immap.h>
  16 #include <asm/io.h>
  17 #include <asm/rtc.h>
  18 #include <linux/compiler.h>
  19
  20 /*
  21  * Breath some life into the CPU...
  22  *
  23  * Set up the memory map,
  24  * initialize a bunch of registers,
  25  * initialize the UPM's
  26  */
  27 void cpu_init_f(void)
  28 {
  29         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  30         fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
  31
  32 #if !defined(CONFIG_CF_SBF)
  33         scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  34         pll_t *pll = (pll_t *)MMAP_PLL;
  35
  36         /* Workaround, must place before fbcs */
  37         out_be32(&pll->psr, 0x12);
  38
  39         out_be32(&scm1->mpr, 0x77777777);
  40         out_be32(&scm1->pacra, 0);
  41         out_be32(&scm1->pacrb, 0);
  42         out_be32(&scm1->pacrc, 0);
  43         out_be32(&scm1->pacrd, 0);
  44         out_be32(&scm1->pacre, 0);
  45         out_be32(&scm1->pacrf, 0);
  46         out_be32(&scm1->pacrg, 0);
  47         out_be32(&scm1->pacri, 0);
  48
  49 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
  50      && defined(CONFIG_SYS_CS0_CTRL))
  51         out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  52         out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  53         out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  54 #endif
  55 #endif                          /* CONFIG_CF_SBF */
  56
  57 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
  58      && defined(CONFIG_SYS_CS1_CTRL))
  59         out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  60         out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  61         out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  62 #endif
  63
  64 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
  65      && defined(CONFIG_SYS_CS2_CTRL))
  66         out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  67         out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  68         out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  69 #endif
  70
  71 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
  72      && defined(CONFIG_SYS_CS3_CTRL))
  73         out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  74         out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  75         out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  76 #endif
  77
  78 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
  79      && defined(CONFIG_SYS_CS4_CTRL))
  80         out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  81         out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  82         out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  83 #endif
  84
  85 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
  86      && defined(CONFIG_SYS_CS5_CTRL))
  87         out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  88         out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  89         out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  90 #endif
  91
  92 #ifdef CONFIG_FSL_I2C
  93         out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
  94 #endif
  95
  96         icache_enable();
  97 }
  98
  99 /*
 100  * initialize higher level parts of CPU like timers
 101  */
 102 int cpu_init_r(void)
 103 {
 104 #ifdef CONFIG_MCFRTC
 105         rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
 106         rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
 107
 108         out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
 109         out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
 110 #endif
 111
 112         return (0);
 113 }
 114
 115 void uart_port_conf(int port)
 116 {
 117         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 118
 119         /* Setup Ports: */
 120         switch (port) {
 121         case 0:
 122                 clrbits_be16(&gpio->par_uart,
 123                         ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
 124                 setbits_be16(&gpio->par_uart,
 125                         GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
 126                 break;
 127         case 1:
 128                 clrbits_be16(&gpio->par_uart,
 129                         ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
 130                 setbits_be16(&gpio->par_uart,
 131                         GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
 132                 break;
 133         case 2:
 134                 clrbits_8(&gpio->par_dspi,
 135                         ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
 136                 out_8(&gpio->par_dspi,
 137                         GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
 138                 break;
 139         }
 140 }
 141
 142 #ifdef CONFIG_CF_DSPI
 143 void cfspi_port_conf(void)
 144 {
 145         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 146
 147         out_8(&gpio->par_dspi,
 148                 GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
 149                 GPIO_PAR_DSPI_SCK_SCK);
 150 }
 151
 152 int cfspi_claim_bus(uint bus, uint cs)
 153 {
 154         dspi_t *dspi = (dspi_t *) MMAP_DSPI;
 155         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 156
 157         if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
 158                 return -1;
 159
 160         /* Clear FIFO and resume transfer */
 161         clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 162
 163         switch (cs) {
 164         case 0:
 165                 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
 166                 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
 167                 break;
 168         case 2:
 169                 clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
 170                 setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
 171                 break;
 172         }
 173
 174         return 0;
 175 }
 176
 177 void cfspi_release_bus(uint bus, uint cs)
 178 {
 179         dspi_t *dspi = (dspi_t *) MMAP_DSPI;
 180         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 181
 182         /* Clear FIFO */
 183         clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 184
 185         switch (cs) {
 186         case 0:
 187                 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
 188                 break;
 189         case 2:
 190                 clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
 191                 break;
 192         }
 193 }
 194 #endif