arch/m68k/cpu/mcf52x2/speed.c

   1 /*
   2  * (C) Copyright 2003
   3  * Josef Baumgartner <josef.baumgartner@telex.de>
   4  *
   5  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
   6  * Hayden Fraser (Hayden.Fraser@freescale.com)
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/processor.h>
  13 #include <asm/immap.h>
  14 #include <asm/io.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
  19 int get_clocks (void)
  20 {
  21 #if defined(CONFIG_M5208)
  22         pll_t *pll = (pll_t *) MMAP_PLL;
  23
  24         out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
  25         out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
  26 #endif
  27
  28 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
  29         volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
  30         unsigned long pllcr;
  31
  32 #ifndef CONFIG_SYS_PLL_BYPASS
  33
  34 #ifdef CONFIG_M5249
  35         /* Setup the PLL to run at the specified speed */
  36 #ifdef CONFIG_SYS_FAST_CLK
  37         pllcr = 0x925a3100;     /* ~140MHz clock (PLL bypass = 0) */
  38 #else
  39         pllcr = 0x135a4140;     /* ~72MHz clock (PLL bypass = 0) */
  40 #endif
  41 #endif                          /* CONFIG_M5249 */
  42
  43 #ifdef CONFIG_M5253
  44         pllcr = CONFIG_SYS_PLLCR;
  45 #endif                          /* CONFIG_M5253 */
  46
  47         cpll = cpll & 0xfffffffe;       /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
  48         mbar2_writeLong(MCFSIM_PLLCR, cpll);    /* Set the PLL to bypass mode (PSTCLK = crystal) */
  49         mbar2_writeLong(MCFSIM_PLLCR, pllcr);   /* set the clock speed */
  50         pllcr ^= 0x00000001;    /* Set pll bypass to 1 */
  51         mbar2_writeLong(MCFSIM_PLLCR, pllcr);   /* Start locking (pll bypass = 1) */
  52         udelay(0x20);           /* Wait for a lock ... */
  53 #endif                          /* #ifndef CONFIG_SYS_PLL_BYPASS */
  54
  55 #endif                          /* CONFIG_M5249 || CONFIG_M5253 */
  56
  57 #if defined(CONFIG_M5275)
  58         pll_t *pll = (pll_t *)(MMAP_PLL);
  59
  60         /* Setup PLL */
  61         out_be32(&pll->syncr, 0x01080000);
  62         while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
  63                 ;
  64         out_be32(&pll->syncr, 0x01000000);
  65         while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
  66                 ;
  67 #endif
  68
  69         gd->cpu_clk = CONFIG_SYS_CLK;
  70 #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
  71     defined(CONFIG_M5271) || defined(CONFIG_M5275)
  72         gd->bus_clk = gd->cpu_clk / 2;
  73 #else
  74         gd->bus_clk = gd->cpu_clk;
  75 #endif
  76
  77 #ifdef CONFIG_SYS_I2C_FSL
  78         gd->arch.i2c1_clk = gd->bus_clk;
  79 #ifdef CONFIG_SYS_I2C2_FSL_OFFSET
  80         gd->arch.i2c2_clk = gd->bus_clk;
  81 #endif
  82 #endif
  83
  84         return (0);
  85 }