arch/nds32/cpu/n1213/ag101/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 .pic
  10
  11 .text
  12
  13 #include <common.h>
  14 #include <config.h>
  15
  16 #include <asm/macro.h>
  17 #include <generated/asm-offsets.h>
  18
  19 /*
  20  * parameters for the SDRAM controller
  21  */
  22 #define SDMC_TP1_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
  23 #define SDMC_TP2_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
  24 #define SDMC_CR1_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
  25 #define SDMC_CR2_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
  26 #define SDMC_B0_BSR_A           (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
  27 #define SDMC_B1_BSR_A           (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
  28
  29 #define SDMC_TP1_D              CONFIG_SYS_FTSDMC021_TP1
  30 #define SDMC_TP2_D              CONFIG_SYS_FTSDMC021_TP2
  31 #define SDMC_CR1_D              CONFIG_SYS_FTSDMC021_CR1
  32 #define SDMC_CR2_D              CONFIG_SYS_FTSDMC021_CR2
  33
  34 #define SDMC_B0_BSR_D           CONFIG_SYS_FTSDMC021_BANK0_BSR
  35 #define SDMC_B1_BSR_D           CONFIG_SYS_FTSDMC021_BANK1_BSR
  36
  37
  38 /*
  39  * for Orca and Emerald
  40  */
  41 #define BOARD_ID_REG            0x104
  42 #define BOARD_ID_FAMILY_MASK    0xfff000
  43 #define BOARD_ID_FAMILY_V5      0x556000
  44 #define BOARD_ID_FAMILY_K7      0x74b000
  45
  46 /*
  47  * parameters for the static memory controller
  48  */
  49 #define SMC_BANK0_CR_A          (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
  50 #define SMC_BANK0_TPR_A         (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
  51
  52 #define SMC_BANK0_CR_D          FTSMC020_BANK0_LOWLV_CONFIG
  53 #define SMC_BANK0_TPR_D         FTSMC020_BANK0_LOWLV_TIMING
  54
  55 /*
  56  * parameters for the ahbc controller
  57  */
  58 #define AHBC_CR_A               (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
  59 #define AHBC_BSR6_A     (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
  60
  61 /*
  62  * for Orca and Emerald
  63  */
  64 #define AHBC_BSR4_A     (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
  65 #define AHBC_BSR6_D             CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
  66
  67 /*
  68  * parameters for the pmu controoler
  69  */
  70 #define PMU_PDLLCR0_A           (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
  71
  72 /*
  73  * numeric 7 segment display
  74  */
  75 .macro  led, num
  76         write32 CONFIG_DEBUG_LED, \num
  77 .endm
  78
  79 /*
  80  * Waiting for SDRAM to set up
  81  */
  82 .macro  wait_sdram
  83         li      $r0, CONFIG_FTSDMC021_BASE
  84 1:
  85         lwi     $r1, [$r0+FTSDMC021_CR2]
  86         bnez    $r1, 1b
  87 .endm
  88
  89 .globl  mem_init
  90 mem_init:
  91         move    $r11, $lp
  92
  93         /*
  94          * mem_init:
  95          *      There are 2 bank connected to FTSMC020 on AG101
  96          *      BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
  97          *      we need to set onboard SDRAM before remap and relocation.
  98          */
  99         led     0x01
 100
 101   /*
 102    * for Orca and Emerald
 103    * disable write protection and reset bank size
 104    */
 105         li      $r0, SMC_BANK0_CR_A
 106         lwi $r1, [$r0+#0x00]
 107         ori $r1, $r1, 0x8f0
 108         xori $r1, $r1, 0x8f0
 109         /* check board */
 110         li      $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
 111   lwi     $r3, [$r3]
 112   li      $r4, BOARD_ID_FAMILY_MASK
 113   and     $r3, $r3, $r4
 114   li      $r4, BOARD_ID_FAMILY_K7
 115   xor     $r4, $r3, $r4
 116   beqz    $r4, use_flash_16bit_boot
 117         /* 32-bit mode */
 118 use_flash_32bit_boot:
 119         ori     $r1, $r1, 0x50
 120   li      $r2, 0x00151151
 121   j       sdram_b0_cr
 122         /* 16-bit mode */
 123 use_flash_16bit_boot:
 124   ori     $r1, $r1, 0x60
 125   li      $r2, 0x00153153
 126         /* SRAM bank0 config */
 127 sdram_b0_cr:
 128   swi     $r1, [$r0+#0x00]
 129   swi     $r2, [$r0+#0x04]
 130
 131         /* config AHB Controller */
 132         led     0x02
 133
 134         /*
 135          * config PMU controller
 136          */
 137         /* ftpmu010_dlldis_disable, must do it in lowleve_init */
 138         led     0x03
 139         setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS          ! 0x00010000
 140
 141         /*
 142          * config SDRAM controller
 143          */
 144         led     0x04
 145         write32 SDMC_TP1_A, SDMC_TP1_D                          ! 0x00011312
 146         led     0x05
 147         write32 SDMC_TP2_A, SDMC_TP2_D                          ! 0x00480180
 148         led     0x06
 149         write32 SDMC_CR1_A, SDMC_CR1_D                          ! 0x00002326
 150
 151         led     0x07
 152         write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC                 ! 0x00000010
 153         wait_sdram
 154
 155         led     0x08
 156         write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR                  ! 0x00000004
 157         wait_sdram
 158
 159         led     0x09
 160         write32 SDMC_CR2_A, FTSDMC021_CR2_IREF                  ! 0x00000008
 161         wait_sdram
 162
 163         led     0x0a
 164         move    $lp, $r11
 165         ret
 166
 167
 168 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 169
 170 .globl  lowlevel_init
 171 lowlevel_init:
 172         move    $r10, $lp
 173         led     0x10
 174         jal     remap
 175 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
 176         led     0x1f
 177         jal     enable_fpu
 178 #endif
 179         led     0x20
 180         ret     $r10
 181
 182 remap:
 183         move    $r11, $lp
 184 #ifdef __NDS32_N1213_43U1H__    /* NDS32 V0 ISA - AG101 Only */
 185         bal     2f
 186 relo_base:
 187         move    $r0, $lp
 188 #else
 189 relo_base:
 190         mfusr   $r0, $pc
 191 #endif /* __NDS32_N1213_43U1H__ */
 192
 193         /* Remapping */
 194         led     0x1a
 195         write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D            ! 0x00001800
 196         write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D            ! 0x00001880
 197
 198         /* clear empty BSR registers */
 199         led     0x1b
 200         li      $r4, CONFIG_FTSDMC021_BASE
 201         li      $r5, 0x0
 202         swi     $r5, [$r4 + FTSDMC021_BANK2_BSR]
 203         swi     $r5, [$r4 + FTSDMC021_BANK3_BSR]
 204
 205 #ifdef CONFIG_MEM_REMAP
 206         /*
 207          * Copy ROM code to SDRAM base for memory remap layout.
 208          * This is not the real relocation, the real relocation is the function
 209          * relocate_code() is start.S which supports the systems is memory
 210          * remapped or not.
 211          */
 212         /*
 213          * Doing memory remap is essential for preparing some non-OS or RTOS
 214          * applications.
 215          *
 216          * This is also a must on ADP-AG101 board.
 217          * The reason is because the ROM/FLASH circuit on PCB board.
 218          * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
 219          * ROM/FLASH is used to boot.
 220          *
 221          * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
 222          * and the FLASH is connected to BANK1.
 223          * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
 224          * and the FLASH is connected to BANK0.
 225          * It will occur problem when doing flash probing if the flash is at
 226          * BANK0 (0x00000000) while memory remapping was skipped.
 227          *
 228          * Other board like ADP-AG101P may not enable this since there is only
 229          * a FLASH connected to bank0.
 230          */
 231         led     0x11
 232    /*
 233     * for Orca and Emerald
 234     * read sdram base address automatically
 235     */
 236         li      $r5, AHBC_BSR6_A
 237         lwi $r8, [$r5]
 238         li      $r4, 0xfff00000   /* r4 = bank6 base */
 239         and $r4, $r4, $r8
 240
 241         la      $r5, _start@GOTOFF
 242         la  $r6, _end@GOTOFF
 243 1:
 244         lwi.p   $r7, [$r5], #4
 245         swi.p   $r7, [$r4], #4
 246         blt     $r5, $r6, 1b
 247
 248         /* set remap bit */
 249         /*
 250          * MEM remap bit is operational
 251          * - use it to map writeable memory at 0x00000000, in place of flash
 252          * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
 253          * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
 254          */
 255         led     0x1c
 256         write32 SDMC_B0_BSR_A, 0x00001000
 257         write32 SDMC_B1_BSR_A, 0x00001200
 258         li $r5, CONFIG_SYS_TEXT_BASE    /* flash base address */
 259         add $r11, $r11, $r5     /* add flash address offset for ret */
 260         add $r10, $r10, $r5
 261         move $lp, $r11
 262         setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP          ! 0x1
 263
 264   /*
 265    * for Orca and Emerald
 266    * extend sdram size from 256MB to 2GB
 267    */
 268         li      $r5, AHBC_BSR6_A
 269         lwi $r6, [$r5]
 270         li  $r4, 0xfff0ffff
 271         and $r6 ,$r4, $r6
 272         li      $r4, 0x000b0000
 273         or  $r6, $r4, $r6
 274         swi     $r6, [$r5]
 275
 276   /*
 277    * for Orca and Emerald
 278    * extend rom base from 256MB to 2GB
 279    */
 280         li      $r4, AHBC_BSR4_A
 281         lwi $r5, [$r4]
 282         li      $r6, 0xffffff
 283         and $r5, $r5, $r6
 284         li  $r6, 0x80000000
 285         or  $r5, $r5, $r6
 286         swi $r5,        [$r4]
 287 #endif /* #ifdef CONFIG_MEM_REMAP */
 288         move $lp, $r11
 289 2:
 290         ret
 291
 292         /*
 293          * enable_fpu:
 294          *  Some of Andes CPU version support FPU coprocessor, if so,
 295          *  and toolchain support FPU instruction set, we should enable it.
 296          */
 297 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
 298 enable_fpu:
 299         mfsr    $r0, $CPU_VER     /* enable FPU if it exists */
 300         srli    $r0, $r0, 3
 301         andi    $r0, $r0, 1
 302         beqz    $r0, 1f           /* skip if no COP */
 303         mfsr    $r0, $FUCOP_EXIST
 304         srli    $r0, $r0, 31
 305         beqz    $r0, 1f           /* skip if no FPU */
 306         mfsr    $r0, $FUCOP_CTL
 307         ori     $r0, $r0, 1
 308         mtsr    $r0, $FUCOP_CTL
 309 1:
 310         ret
 311 #endif
 312
 313 .globl show_led
 314 show_led:
 315     li      $r8, (CONFIG_DEBUG_LED)
 316     swi     $r7, [$r8]
 317     ret
 318 #endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */