arch/nds32/include/asm/arch-ae3xx/ae3xx.h

   1 /*
   2  * Copyright (C) 2016 Andes Technology Corporation
   3  * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __AE3XX_H
  10 #define __AE3XX_H
  11
  12 /* Hardware register bases */
  13
  14 /* Static Memory Controller (SRAM) */
  15 #define CONFIG_FTSMC020_BASE            0xe0400000
  16 /* DMA Controller */
  17 #define CONFIG_FTDMAC020_BASE           0xf0c00000
  18 /* AHB-to-APB Bridge */
  19 #define CONFIG_FTAPBBRG020S_01_BASE     0xf0000000
  20 /* Reserved */
  21 #define CONFIG_RESERVED_01_BASE         0xe0500000
  22 /* Reserved */
  23 #define CONFIG_RESERVED_02_BASE         0xf0800000
  24 /* Reserved */
  25 #define CONFIG_RESERVED_03_BASE         0xf0900000
  26 /* Ethernet */
  27 #define CONFIG_FTMAC100_BASE            0xe0100000
  28 /* Reserved */
  29 #define CONFIG_RESERVED_04_BASE         0xf1000000
  30
  31 /* APB Device definitions */
  32
  33 /* UART1 */
  34 #define CONFIG_FTUART010_01_BASE        0xf0200000
  35 /* UART2 */
  36 #define CONFIG_FTUART010_02_BASE        0xf0300000
  37 /* Counter/Timers */
  38 #define CONFIG_FTTMR010_BASE            0xf0400000
  39 /* Watchdog Timer */
  40 #define CONFIG_FTWDT010_BASE            0xf0500000
  41 /* Real Time Clock */
  42 #define CONFIG_FTRTC010_BASE            0xf0600000
  43 /* GPIO */
  44 #define CONFIG_FTGPIO010_BASE           0xf0700000
  45 /* I2C */
  46 #define CONFIG_FTIIC010_BASE            0xf0a00000
  47 /* SD Controller */
  48 #define CONFIG_FTSDC010_BASE            0xf0e00000
  49
  50 /* The following address was not defined in Linux */
  51
  52 /* Synchronous Serial Port Controller (SSP) 01 */
  53 #define CONFIG_FTSSP010_01_BASE         0xf0d00000
  54 #endif  /* __AE3XX_H */