arch/nds32/include/asm/cache.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _ASM_CACHE_H
  10 #define _ASM_CACHE_H
  11
  12 /* cache */
  13 int     icache_status(void);
  14 void    icache_enable(void);
  15 void    icache_disable(void);
  16 int     dcache_status(void);
  17 void    dcache_enable(void);
  18 void    dcache_disable(void);
  19 void cache_flush(void);
  20
  21 #define DEFINE_GET_SYS_REG(reg) \
  22         static inline unsigned long GET_##reg(void)             \
  23         {                                                       \
  24                 unsigned long val;                              \
  25                 __asm__ volatile (                              \
  26                 "mfsr %0, $"#reg : "=&r" (val) : : "memory"     \
  27                 );                                              \
  28                 return val;                                     \
  29         }
  30
  31 enum cache_t {ICACHE, DCACHE};
  32 DEFINE_GET_SYS_REG(ICM_CFG);
  33 DEFINE_GET_SYS_REG(DCM_CFG);
  34 /* I-cache sets (# of cache lines) per way */
  35 #define ICM_CFG_OFF_ISET        0
  36 /* I-cache ways */
  37 #define ICM_CFG_OFF_IWAY        3
  38 #define ICM_CFG_MSK_ISET        (0x7 << ICM_CFG_OFF_ISET)
  39 #define ICM_CFG_MSK_IWAY        (0x7 << ICM_CFG_OFF_IWAY)
  40 /* D-cache sets (# of cache lines) per way */
  41 #define DCM_CFG_OFF_DSET        0
  42 /* D-cache ways */
  43 #define DCM_CFG_OFF_DWAY        3
  44 #define DCM_CFG_MSK_DSET        (0x7 << DCM_CFG_OFF_DSET)
  45 #define DCM_CFG_MSK_DWAY        (0x7 << DCM_CFG_OFF_DWAY)
  46 /* I-cache line size */
  47 #define ICM_CFG_OFF_ISZ 6
  48 #define ICM_CFG_MSK_ISZ         (0x7UL << ICM_CFG_OFF_ISZ)
  49 /* D-cache line size */
  50 #define DCM_CFG_OFF_DSZ 6
  51 #define DCM_CFG_MSK_DSZ         (0x7UL << DCM_CFG_OFF_DSZ)
  52
  53 /*
  54  * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
  55  * We use that value for aligning DMA buffers unless the board config has
  56  * specified an alternate cache line size.
  57  */
  58 #ifdef CONFIG_SYS_CACHELINE_SIZE
  59 #define ARCH_DMA_MINALIGN       CONFIG_SYS_CACHELINE_SIZE
  60 #else
  61 #define ARCH_DMA_MINALIGN       32
  62 #endif
  63
  64 #endif /* _ASM_CACHE_H */