2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
27 #include <asm/fsl_serdes.h>
28 #include <asm/immap_85xx.h>
30 #include <asm/processor.h>
31 #include <asm/fsl_law.h>
32 #include <asm/errno.h>
33 #include "fsl_corenet_serdes.h"
36 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
37 * The code is already very complicated as it is, and separating the two
38 * completely would just make things worse. We try to keep them as separate
39 * as possible, but for now we require SERDES8 if SERDES_A001 is defined.
41 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
42 #ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
43 #error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
47 static u32 serdes_prtcl_map
;
50 static const char *serdes_prtcl_str
[] = {
60 [SGMII_FM1_DTSEC1
] = "SGMII_FM1_DTSEC1",
61 [SGMII_FM1_DTSEC2
] = "SGMII_FM1_DTSEC2",
62 [SGMII_FM1_DTSEC3
] = "SGMII_FM1_DTSEC3",
63 [SGMII_FM1_DTSEC4
] = "SGMII_FM1_DTSEC4",
64 [SGMII_FM1_DTSEC5
] = "SGMII_FM1_DTSEC5",
65 [SGMII_FM2_DTSEC1
] = "SGMII_FM2_DTSEC1",
66 [SGMII_FM2_DTSEC2
] = "SGMII_FM2_DTSEC2",
67 [SGMII_FM2_DTSEC3
] = "SGMII_FM2_DTSEC3",
68 [SGMII_FM2_DTSEC4
] = "SGMII_FM2_DTSEC4",
69 [SGMII_FM2_DTSEC5
] = "SGMII_FM2_DTSEC5",
70 [XAUI_FM1
] = "XAUI_FM1",
71 [XAUI_FM2
] = "XAUI_FM2",
78 unsigned int lpd
; /* RCW lane powerdown bit */
80 } lanes
[SRDS_MAX_LANES
] = {
81 { 0, 152, FSL_SRDS_BANK_1
},
82 { 1, 153, FSL_SRDS_BANK_1
},
83 { 2, 154, FSL_SRDS_BANK_1
},
84 { 3, 155, FSL_SRDS_BANK_1
},
85 { 4, 156, FSL_SRDS_BANK_1
},
86 { 5, 157, FSL_SRDS_BANK_1
},
87 { 6, 158, FSL_SRDS_BANK_1
},
88 { 7, 159, FSL_SRDS_BANK_1
},
89 { 8, 160, FSL_SRDS_BANK_1
},
90 { 9, 161, FSL_SRDS_BANK_1
},
91 { 16, 162, FSL_SRDS_BANK_2
},
92 { 17, 163, FSL_SRDS_BANK_2
},
93 { 18, 164, FSL_SRDS_BANK_2
},
94 { 19, 165, FSL_SRDS_BANK_2
},
95 { 20, 170, FSL_SRDS_BANK_3
},
96 { 21, 171, FSL_SRDS_BANK_3
},
97 { 22, 172, FSL_SRDS_BANK_3
},
98 { 23, 173, FSL_SRDS_BANK_3
},
101 int serdes_get_lane_idx(int lane
)
103 return lanes
[lane
].idx
;
106 int serdes_get_bank_by_lane(int lane
)
108 return lanes
[lane
].bank
;
111 int serdes_lane_enabled(int lane
)
113 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
114 serdes_corenet_t
*regs
= (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR
;
116 int bank
= lanes
[lane
].bank
;
117 int word
= lanes
[lane
].lpd
/ 32;
118 int bit
= lanes
[lane
].lpd
% 32;
120 if (in_be32(®s
->bank
[bank
].rstctl
) & SRDS_RSTCTL_SDPD
)
123 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
125 * For banks two and three, use the srds_lpd_b[] array instead of the
126 * RCW, because this array contains the real values of SRDS_LPD_B2 and
130 return !(srds_lpd_b
[bank
] & (8 >> (lane
- (6 + 4 * bank
))));
133 return !(in_be32(&gur
->rcwsr
[word
]) & (0x80000000 >> bit
));
136 int is_serdes_configured(enum srds_prtcl device
)
138 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
140 /* Is serdes enabled at all? */
141 if (!(in_be32(&gur
->rcwsr
[5]) & FSL_CORENET_RCWSR5_SRDS_EN
))
144 return (1 << device
) & serdes_prtcl_map
;
147 static int __serdes_get_first_lane(uint32_t prtcl
, enum srds_prtcl device
)
151 for (i
= 0; i
< SRDS_MAX_LANES
; i
++) {
152 if (serdes_get_prtcl(prtcl
, i
) == device
)
160 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
161 * device. This depends on the current SERDES protocol, as defined in the RCW.
163 * Returns a negative error code if SERDES is disabled or the given device is
164 * not supported in the current SERDES protocol.
166 int serdes_get_first_lane(enum srds_prtcl device
)
169 const ccsr_gur_t
*gur
;
171 gur
= (typeof(gur
))CONFIG_SYS_MPC85xx_GUTS_ADDR
;
173 /* Is serdes enabled at all? */
174 if (unlikely((in_be32(&gur
->rcwsr
[5]) & 0x2000) == 0))
177 prtcl
= (in_be32(&gur
->rcwsr
[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL
) >> 26;
179 return __serdes_get_first_lane(prtcl
, device
);
182 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
184 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
187 * Returns a negative error code if the given device is not supported for the
188 * given SERDES protocol.
190 static int serdes_get_bank_by_device(uint32_t prtcl
, enum srds_prtcl device
)
194 lane
= __serdes_get_first_lane(prtcl
, device
);
195 if (unlikely(lane
< 0))
198 return serdes_get_bank_by_lane(lane
);
201 static uint32_t __serdes_get_lane_count(uint32_t prtcl
, enum srds_prtcl device
,
206 for (lane
= first
; lane
< SRDS_MAX_LANES
; lane
++) {
207 if (serdes_get_prtcl(prtcl
, lane
) != device
)
214 static void __serdes_reset_rx(serdes_corenet_t
*regs
,
216 enum srds_prtcl device
)
218 int lane
, idx
, first
, last
;
220 lane
= __serdes_get_first_lane(prtcl
, device
);
221 if (unlikely(lane
< 0))
223 first
= serdes_get_lane_idx(lane
);
224 last
= first
+ __serdes_get_lane_count(prtcl
, device
, lane
);
227 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
228 * selected as XAUI to place the lane into reset.
230 for (idx
= first
; idx
< last
; idx
++)
231 clrbits_be32(®s
->lane
[idx
].gcr0
, SRDS_GCR0_RRST
);
233 /* Wait at least 250 ns */
237 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
238 * selected as XAUI to bring the lane out of reset.
240 for (idx
= first
; idx
< last
; idx
++)
241 setbits_be32(®s
->lane
[idx
].gcr0
, SRDS_GCR0_RRST
);
244 void serdes_reset_rx(enum srds_prtcl device
)
247 const ccsr_gur_t
*gur
;
248 serdes_corenet_t
*regs
;
250 if (unlikely(device
== NONE
))
253 gur
= (typeof(gur
))CONFIG_SYS_MPC85xx_GUTS_ADDR
;
255 /* Is serdes enabled at all? */
256 if (unlikely((in_be32(&gur
->rcwsr
[5]) & 0x2000) == 0))
259 regs
= (typeof(regs
))CONFIG_SYS_FSL_CORENET_SERDES_ADDR
;
260 prtcl
= (in_be32(&gur
->rcwsr
[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL
) >> 26;
262 __serdes_reset_rx(regs
, prtcl
, device
);
266 #ifndef CONFIG_SYS_DCSRBAR_PHYS
267 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
268 #define CONFIG_SYS_DCSRBAR 0x80000000
269 #define __DCSR_NOT_DEFINED_BY_CONFIG
272 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
274 * Enable a SERDES bank that was disabled via the RCW
276 * We only call this function for SERDES8 and SERDES-A001 in cases we really
277 * want to enable the bank, whether we actually want to use the lanes or not,
278 * so make sure at least one lane is enabled. We're only enabling this one
279 * lane to satisfy errata requirements that the bank be enabled.
281 * We use a local variable instead of srds_lpd_b[] because we want drivers to
282 * think that the lanes actually are disabled.
284 static void enable_bank(ccsr_gur_t
*gur
, int bank
)
287 u32 temp_lpd_b
= srds_lpd_b
[bank
];
290 * If we're asked to disable all lanes, just pretend we're doing
293 if (temp_lpd_b
== 0xF)
297 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in
298 * CCSR, and read/write in DSCR.
300 rcw5
= in_be32(gur
->rcwsr
+ 5);
301 if (bank
== FSL_SRDS_BANK_2
) {
302 rcw5
&= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2
;
303 rcw5
|= temp_lpd_b
<< 26;
304 } else if (bank
== FSL_SRDS_BANK_3
) {
305 rcw5
&= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3
;
306 rcw5
|= temp_lpd_b
<< 18;
308 printf("SERDES: enable_bank: bad bank %d\n", bank
+ 1);
312 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
313 * of the DCSR mapping.
316 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
317 struct law_entry law
= find_law(CONFIG_SYS_DCSRBAR_PHYS
);
320 law_index
= set_next_law(CONFIG_SYS_DCSRBAR_PHYS
,
321 LAW_SIZE_1M
, LAW_TRGT_IF_DCSR
);
323 set_law(law
.index
, CONFIG_SYS_DCSRBAR_PHYS
, LAW_SIZE_1M
,
326 u32
*p
= (void *)CONFIG_SYS_DCSRBAR
+ 0x20114;
328 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
330 disable_law(law_index
);
332 set_law(law
.index
, law
.addr
, law
.size
, law
.trgt_id
);
338 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
339 * bank 3 to clock banks 2 and 3, as well as a limited selection of
340 * protocol configurations. This requires that banks 2 and 3's lanes be
341 * disabled in the RCW, and enabled with some fixup here to re-enable
342 * them, and to configure bank 2's clock parameters in bank 3's pll in
343 * cases where they differ.
345 static void p4080_erratum_serdes8(serdes_corenet_t
*regs
, ccsr_gur_t
*gur
,
346 u32 devdisr
, u32 devdisr2
, int cfg
)
352 * The disabled lanes of bank 2 will cause the associated
353 * logic blocks to be disabled in DEVDISR. We reverse that here.
355 * Note that normally it is not permitted to clear DEVDISR bits
356 * once the device has been disabled, but the hardware people
357 * say that this special case is OK.
359 clrbits_be32(&gur
->devdisr
, devdisr
);
360 clrbits_be32(&gur
->devdisr2
, devdisr2
);
363 * Some protocols require special handling. There are a few
364 * additional protocol configurations that can be used, which are
365 * not listed here. See app note 4065 for supported protocol
371 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
372 * SGMII on bank 3 should still be usable.
374 setbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr1
,
375 SRDS_PLLCR1_PLL_BWSEL
);
381 * Banks 2 (XAUI) and 3 (SGMII) have different clocking
382 * requirements in these configurations. Bank 3 cannot
383 * be used and should have its lanes (but not the bank
384 * itself) disabled in the RCW. We set up bank 3's pll
385 * for bank 2's needs here.
387 srds_ratio_b2
= (in_be32(&gur
->rcwsr
[4]) >> 13) & 7;
389 /* Determine refclock from XAUI ratio */
390 switch (srds_ratio_b2
) {
392 rfck_sel
= SRDS_PLLCR0_RFCK_SEL_156_25
;
395 rfck_sel
= SRDS_PLLCR0_RFCK_SEL_125
;
398 printf("SERDES: bad SRDS_RATIO_B2 %d\n",
403 clrsetbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr0
,
404 SRDS_PLLCR0_RFCK_SEL_MASK
, rfck_sel
);
406 clrsetbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr0
,
407 SRDS_PLLCR0_FRATE_SEL_MASK
,
408 SRDS_PLLCR0_FRATE_SEL_6_25
);
412 enable_bank(gur
, FSL_SRDS_BANK_3
);
416 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
418 * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
419 * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
421 static void p4080_erratum_serdes_a005(serdes_corenet_t
*regs
, unsigned int cfg
)
423 enum srds_prtcl device
;
429 * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
432 clrbits_be32(®s
->bank
[FSL_SRDS_BANK_1
].pllcr1
,
433 SRDS_PLLCR1_PLL_BWSEL
);
437 * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
438 * SRDSB3PLLCR1[PLLBW_SEL] to 1.
440 clrbits_be32(®s
->bank
[FSL_SRDS_BANK_1
].pllcr1
,
441 SRDS_PLLCR1_PLL_BWSEL
);
442 setbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr1
,
443 SRDS_PLLCR1_PLL_BWSEL
);
448 * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
449 * before XAUI is initialized.
451 for (device
= XAUI_FM1
; device
<= XAUI_FM2
; device
++) {
452 if (is_serdes_configured(device
)) {
453 int bank
= serdes_get_bank_by_device(cfg
, device
);
455 clrbits_be32(®s
->bank
[bank
].pllcr1
,
456 SRDS_PLLCR1_PLL_BWSEL
);
463 * Wait for the RSTDONE bit to get set, or a one-second timeout.
465 static void wait_for_rstdone(unsigned int bank
)
467 serdes_corenet_t
*srds_regs
=
468 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR
;
469 unsigned long long end_tick
;
472 /* wait for reset complete or 1-second timeout */
473 end_tick
= usec2ticks(1000000) + get_ticks();
475 rstctl
= in_be32(&srds_regs
->bank
[bank
].rstctl
);
476 if (rstctl
& SRDS_RSTCTL_RSTDONE
)
478 } while (end_tick
> get_ticks());
480 if (!(rstctl
& SRDS_RSTCTL_RSTDONE
))
481 printf("SERDES: timeout resetting bank %u\n", bank
+ 1);
485 void __soc_serdes_init(void)
487 /* Allow for SoC-specific initialization in <SOC>_serdes.c */
489 void soc_serdes_init(void) __attribute__((weak
, alias("__soc_serdes_init")));
491 void fsl_serdes_init(void)
493 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
495 serdes_corenet_t
*srds_regs
;
497 int have_bank
[SRDS_MAX_BANK
] = {};
498 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
499 u32 serdes8_devdisr
= 0;
500 u32 serdes8_devdisr2
= 0;
501 char srds_lpd_opt
[16];
502 const char *srds_lpd_arg
;
505 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
506 int need_serdes_a001
; /* TRUE == need work-around for SERDES A001 */
508 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
509 char buffer
[HWCONFIG_BUFFER_SIZE
];
513 * Extract hwconfig from environment since we have not properly setup
514 * the environment but need it for ddr config params
516 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
520 /* Is serdes enabled at all? */
521 if (!(in_be32(&gur
->rcwsr
[5]) & FSL_CORENET_RCWSR5_SRDS_EN
))
524 srds_regs
= (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR
);
525 cfg
= (in_be32(&gur
->rcwsr
[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL
) >> 26;
526 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg
);
528 if (!is_serdes_prtcl_valid(cfg
)) {
529 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg
);
533 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
535 * Display a warning if banks two and three are not disabled in the RCW,
536 * since our work-around for SERDES8 depends on these banks being
537 * disabled at power-on.
539 #define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
540 if ((in_be32(&gur
->rcwsr
[5]) & B2_B3
) != B2_B3
) {
541 printf("Warning: SERDES8 requires banks two and "
542 "three to be disabled in the RCW\n");
546 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
547 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds
548 * for a description of these options.
550 for (bank
= 1; bank
< ARRAY_SIZE(srds_lpd_b
); bank
++) {
551 sprintf(srds_lpd_opt
, "fsl_srds_lpd_b%u", bank
+ 1);
553 hwconfig_subarg_f("serdes", srds_lpd_opt
, &arglen
, buf
);
556 simple_strtoul(srds_lpd_arg
, NULL
, 0) & 0xf;
559 if ((cfg
== 0xf) || (cfg
== 0x10)) {
561 * For SERDES protocols 0xF and 0x10, force bank 3 to be
562 * disabled, because it is not supported.
564 srds_lpd_b
[FSL_SRDS_BANK_3
] = 0xF;
568 /* Look for banks with all lanes disabled, and power down the bank. */
569 for (lane
= 0; lane
< SRDS_MAX_LANES
; lane
++) {
570 enum srds_prtcl lane_prtcl
= serdes_get_prtcl(cfg
, lane
);
571 if (serdes_lane_enabled(lane
)) {
572 have_bank
[serdes_get_bank_by_lane(lane
)] = 1;
573 serdes_prtcl_map
|= (1 << lane_prtcl
);
579 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
581 * Bank two uses the clock from bank three, so if bank two is enabled,
582 * then bank three must also be enabled.
584 if (have_bank
[FSL_SRDS_BANK_2
])
585 have_bank
[FSL_SRDS_BANK_3
] = 1;
588 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
590 * The work-aroud for erratum SERDES-A001 is needed only if bank two
591 * is disabled and bank three is enabled. The converse is also true,
592 * but SERDES8 ensures that bank 3 is always enabled if bank 2 is
593 * enabled, so there's no point in complicating the code to handle
597 !have_bank
[FSL_SRDS_BANK_2
] && have_bank
[FSL_SRDS_BANK_3
];
600 /* Power down the banks we're not interested in */
601 for (bank
= 0; bank
< SRDS_MAX_BANK
; bank
++) {
602 if (!have_bank
[bank
]) {
603 printf("SERDES: bank %d disabled\n", bank
+ 1);
604 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
606 * Erratum SERDES-A001 says bank two needs to be powered
607 * down after bank three is powered up, so don't power
608 * down bank two here.
610 if (!need_serdes_a001
|| (bank
!= FSL_SRDS_BANK_2
))
611 setbits_be32(&srds_regs
->bank
[bank
].rstctl
,
614 setbits_be32(&srds_regs
->bank
[bank
].rstctl
,
620 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
621 for (lane
= 0; lane
< SRDS_MAX_LANES
; lane
++) {
622 enum srds_prtcl lane_prtcl
;
624 idx
= serdes_get_lane_idx(lane
);
625 lane_prtcl
= serdes_get_prtcl(cfg
, lane
);
642 printf("%s ", serdes_prtcl_str
[lane_prtcl
]);
645 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
647 * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for
648 * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
649 * AURORA before the device is initialized.
651 switch (lane_prtcl
) {
652 case SGMII_FM1_DTSEC1
:
653 case SGMII_FM1_DTSEC2
:
654 case SGMII_FM1_DTSEC3
:
655 case SGMII_FM1_DTSEC4
:
656 case SGMII_FM2_DTSEC1
:
657 case SGMII_FM2_DTSEC2
:
658 case SGMII_FM2_DTSEC3
:
659 case SGMII_FM2_DTSEC4
:
660 case SGMII_FM2_DTSEC5
:
666 clrsetbits_be32(&srds_regs
->lane
[idx
].ttlcr0
,
667 SRDS_TTLCR0_FLT_SEL_MASK
,
668 SRDS_TTLCR0_FLT_SEL_750PPM
|
675 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
676 switch (lane_prtcl
) {
680 serdes8_devdisr
|= FSL_CORENET_DEVDISR_PCIE1
>>
681 (lane_prtcl
- PCIE1
);
685 serdes8_devdisr
|= FSL_CORENET_DEVDISR_SRIO1
>>
686 (lane_prtcl
- SRIO1
);
688 case SGMII_FM1_DTSEC1
:
689 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
690 FSL_CORENET_DEVDISR2_DTSEC1_1
;
692 case SGMII_FM1_DTSEC2
:
693 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
694 FSL_CORENET_DEVDISR2_DTSEC1_2
;
696 case SGMII_FM1_DTSEC3
:
697 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
698 FSL_CORENET_DEVDISR2_DTSEC1_3
;
700 case SGMII_FM1_DTSEC4
:
701 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
702 FSL_CORENET_DEVDISR2_DTSEC1_4
;
704 case SGMII_FM2_DTSEC1
:
705 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
706 FSL_CORENET_DEVDISR2_DTSEC2_1
;
708 case SGMII_FM2_DTSEC2
:
709 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
710 FSL_CORENET_DEVDISR2_DTSEC2_2
;
712 case SGMII_FM2_DTSEC3
:
713 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
714 FSL_CORENET_DEVDISR2_DTSEC2_3
;
716 case SGMII_FM2_DTSEC4
:
717 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
718 FSL_CORENET_DEVDISR2_DTSEC2_4
;
720 case SGMII_FM2_DTSEC5
:
721 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
722 FSL_CORENET_DEVDISR2_DTSEC2_5
;
725 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
726 FSL_CORENET_DEVDISR2_10GEC1
;
729 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
730 FSL_CORENET_DEVDISR2_10GEC2
;
746 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
747 p4080_erratum_serdes_a005(srds_regs
, cfg
);
750 for (idx
= 0; idx
< SRDS_MAX_BANK
; idx
++) {
753 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
755 * Change bank init order to 0, 2, 1, so that the third bank's
756 * PLL is established before we start the second bank. The
757 * second bank uses the third bank's PLL.
761 bank
= FSL_SRDS_BANK_3
;
763 bank
= FSL_SRDS_BANK_2
;
766 /* Skip disabled banks */
767 if (!have_bank
[bank
])
770 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
773 * Re-enable devices on banks two and three that were
774 * disabled by the RCW, and then enable bank three. The
775 * devices need to be enabled before either bank is
778 p4080_erratum_serdes8(srds_regs
, gur
, serdes8_devdisr
,
779 serdes8_devdisr2
, cfg
);
780 } else if (idx
== 2) {
781 /* Enable bank two now that bank three is enabled. */
782 enable_bank(gur
, FSL_SRDS_BANK_2
);
786 wait_for_rstdone(bank
);
789 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
790 if (need_serdes_a001
) {
791 /* Bank 3 has been enabled, so now we can disable bank 2 */
792 setbits_be32(&srds_regs
->bank
[FSL_SRDS_BANK_2
].rstctl
,