2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
27 #include <asm/fsl_serdes.h>
28 #include <asm/immap_85xx.h>
30 #include <asm/processor.h>
31 #include <asm/fsl_law.h>
32 #include <asm/errno.h>
33 #include "fsl_corenet_serdes.h"
36 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
37 * The code is already very complicated as it is, and separating the two
38 * completely would just make things worse. We try to keep them as separate
39 * as possible, but for now we require SERDES8 if SERDES_A001 is defined.
41 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
42 #ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
43 #error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
47 static u32 serdes_prtcl_map
;
50 static const char *serdes_prtcl_str
[] = {
60 [SGMII_FM1_DTSEC1
] = "SGMII_FM1_DTSEC1",
61 [SGMII_FM1_DTSEC2
] = "SGMII_FM1_DTSEC2",
62 [SGMII_FM1_DTSEC3
] = "SGMII_FM1_DTSEC3",
63 [SGMII_FM1_DTSEC4
] = "SGMII_FM1_DTSEC4",
64 [SGMII_FM1_DTSEC5
] = "SGMII_FM1_DTSEC5",
65 [SGMII_FM2_DTSEC1
] = "SGMII_FM2_DTSEC1",
66 [SGMII_FM2_DTSEC2
] = "SGMII_FM2_DTSEC2",
67 [SGMII_FM2_DTSEC3
] = "SGMII_FM2_DTSEC3",
68 [SGMII_FM2_DTSEC4
] = "SGMII_FM2_DTSEC4",
69 [SGMII_FM2_DTSEC5
] = "SGMII_FM2_DTSEC5",
70 [XAUI_FM1
] = "XAUI_FM1",
71 [XAUI_FM2
] = "XAUI_FM2",
78 unsigned int lpd
; /* RCW lane powerdown bit */
80 } lanes
[SRDS_MAX_LANES
] = {
81 { 0, 152, FSL_SRDS_BANK_1
},
82 { 1, 153, FSL_SRDS_BANK_1
},
83 { 2, 154, FSL_SRDS_BANK_1
},
84 { 3, 155, FSL_SRDS_BANK_1
},
85 { 4, 156, FSL_SRDS_BANK_1
},
86 { 5, 157, FSL_SRDS_BANK_1
},
87 { 6, 158, FSL_SRDS_BANK_1
},
88 { 7, 159, FSL_SRDS_BANK_1
},
89 { 8, 160, FSL_SRDS_BANK_1
},
90 { 9, 161, FSL_SRDS_BANK_1
},
91 { 16, 162, FSL_SRDS_BANK_2
},
92 { 17, 163, FSL_SRDS_BANK_2
},
93 { 18, 164, FSL_SRDS_BANK_2
},
94 { 19, 165, FSL_SRDS_BANK_2
},
95 #ifdef CONFIG_PPC_P4080
96 { 20, 170, FSL_SRDS_BANK_3
},
97 { 21, 171, FSL_SRDS_BANK_3
},
98 { 22, 172, FSL_SRDS_BANK_3
},
99 { 23, 173, FSL_SRDS_BANK_3
},
101 { 20, 166, FSL_SRDS_BANK_3
},
102 { 21, 167, FSL_SRDS_BANK_3
},
103 { 22, 168, FSL_SRDS_BANK_3
},
104 { 23, 169, FSL_SRDS_BANK_3
},
108 int serdes_get_lane_idx(int lane
)
110 return lanes
[lane
].idx
;
113 int serdes_get_bank_by_lane(int lane
)
115 return lanes
[lane
].bank
;
118 int serdes_lane_enabled(int lane
)
120 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
121 serdes_corenet_t
*regs
= (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR
;
123 int bank
= lanes
[lane
].bank
;
124 int word
= lanes
[lane
].lpd
/ 32;
125 int bit
= lanes
[lane
].lpd
% 32;
127 if (in_be32(®s
->bank
[bank
].rstctl
) & SRDS_RSTCTL_SDPD
)
130 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
132 * For banks two and three, use the srds_lpd_b[] array instead of the
133 * RCW, because this array contains the real values of SRDS_LPD_B2 and
137 return !(srds_lpd_b
[bank
] & (8 >> (lane
- (6 + 4 * bank
))));
140 return !(in_be32(&gur
->rcwsr
[word
]) & (0x80000000 >> bit
));
143 int is_serdes_configured(enum srds_prtcl device
)
145 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
147 /* Is serdes enabled at all? */
148 if (!(in_be32(&gur
->rcwsr
[5]) & FSL_CORENET_RCWSR5_SRDS_EN
))
151 return (1 << device
) & serdes_prtcl_map
;
154 static int __serdes_get_first_lane(uint32_t prtcl
, enum srds_prtcl device
)
158 for (i
= 0; i
< SRDS_MAX_LANES
; i
++) {
159 if (serdes_get_prtcl(prtcl
, i
) == device
)
167 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
168 * device. This depends on the current SERDES protocol, as defined in the RCW.
170 * Returns a negative error code if SERDES is disabled or the given device is
171 * not supported in the current SERDES protocol.
173 int serdes_get_first_lane(enum srds_prtcl device
)
176 const ccsr_gur_t
*gur
;
178 gur
= (typeof(gur
))CONFIG_SYS_MPC85xx_GUTS_ADDR
;
180 /* Is serdes enabled at all? */
181 if (unlikely((in_be32(&gur
->rcwsr
[5]) & 0x2000) == 0))
184 prtcl
= (in_be32(&gur
->rcwsr
[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL
) >> 26;
186 return __serdes_get_first_lane(prtcl
, device
);
189 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
191 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
194 * Returns a negative error code if the given device is not supported for the
195 * given SERDES protocol.
197 static int serdes_get_bank_by_device(uint32_t prtcl
, enum srds_prtcl device
)
201 lane
= __serdes_get_first_lane(prtcl
, device
);
202 if (unlikely(lane
< 0))
205 return serdes_get_bank_by_lane(lane
);
208 static uint32_t __serdes_get_lane_count(uint32_t prtcl
, enum srds_prtcl device
,
213 for (lane
= first
; lane
< SRDS_MAX_LANES
; lane
++) {
214 if (serdes_get_prtcl(prtcl
, lane
) != device
)
221 static void __serdes_reset_rx(serdes_corenet_t
*regs
,
223 enum srds_prtcl device
)
225 int lane
, idx
, first
, last
;
227 lane
= __serdes_get_first_lane(prtcl
, device
);
228 if (unlikely(lane
< 0))
230 first
= serdes_get_lane_idx(lane
);
231 last
= first
+ __serdes_get_lane_count(prtcl
, device
, lane
);
234 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
235 * selected as XAUI to place the lane into reset.
237 for (idx
= first
; idx
< last
; idx
++)
238 clrbits_be32(®s
->lane
[idx
].gcr0
, SRDS_GCR0_RRST
);
240 /* Wait at least 250 ns */
244 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
245 * selected as XAUI to bring the lane out of reset.
247 for (idx
= first
; idx
< last
; idx
++)
248 setbits_be32(®s
->lane
[idx
].gcr0
, SRDS_GCR0_RRST
);
251 void serdes_reset_rx(enum srds_prtcl device
)
254 const ccsr_gur_t
*gur
;
255 serdes_corenet_t
*regs
;
257 if (unlikely(device
== NONE
))
260 gur
= (typeof(gur
))CONFIG_SYS_MPC85xx_GUTS_ADDR
;
262 /* Is serdes enabled at all? */
263 if (unlikely((in_be32(&gur
->rcwsr
[5]) & 0x2000) == 0))
266 regs
= (typeof(regs
))CONFIG_SYS_FSL_CORENET_SERDES_ADDR
;
267 prtcl
= (in_be32(&gur
->rcwsr
[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL
) >> 26;
269 __serdes_reset_rx(regs
, prtcl
, device
);
273 #ifndef CONFIG_SYS_DCSRBAR_PHYS
274 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
275 #define CONFIG_SYS_DCSRBAR 0x80000000
276 #define __DCSR_NOT_DEFINED_BY_CONFIG
279 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
281 * Enable a SERDES bank that was disabled via the RCW
283 * We only call this function for SERDES8 and SERDES-A001 in cases we really
284 * want to enable the bank, whether we actually want to use the lanes or not,
285 * so make sure at least one lane is enabled. We're only enabling this one
286 * lane to satisfy errata requirements that the bank be enabled.
288 * We use a local variable instead of srds_lpd_b[] because we want drivers to
289 * think that the lanes actually are disabled.
291 static void enable_bank(ccsr_gur_t
*gur
, int bank
)
294 u32 temp_lpd_b
= srds_lpd_b
[bank
];
297 * If we're asked to disable all lanes, just pretend we're doing
300 if (temp_lpd_b
== 0xF)
304 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in
305 * CCSR, and read/write in DSCR.
307 rcw5
= in_be32(gur
->rcwsr
+ 5);
308 if (bank
== FSL_SRDS_BANK_2
) {
309 rcw5
&= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2
;
310 rcw5
|= temp_lpd_b
<< 26;
311 } else if (bank
== FSL_SRDS_BANK_3
) {
312 rcw5
&= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3
;
313 rcw5
|= temp_lpd_b
<< 18;
315 printf("SERDES: enable_bank: bad bank %d\n", bank
+ 1);
319 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
320 * of the DCSR mapping.
323 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
324 struct law_entry law
= find_law(CONFIG_SYS_DCSRBAR_PHYS
);
327 law_index
= set_next_law(CONFIG_SYS_DCSRBAR_PHYS
,
328 LAW_SIZE_1M
, LAW_TRGT_IF_DCSR
);
330 set_law(law
.index
, CONFIG_SYS_DCSRBAR_PHYS
, LAW_SIZE_1M
,
333 u32
*p
= (void *)CONFIG_SYS_DCSRBAR
+ 0x20114;
335 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
337 disable_law(law_index
);
339 set_law(law
.index
, law
.addr
, law
.size
, law
.trgt_id
);
345 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
346 * bank 3 to clock banks 2 and 3, as well as a limited selection of
347 * protocol configurations. This requires that banks 2 and 3's lanes be
348 * disabled in the RCW, and enabled with some fixup here to re-enable
349 * them, and to configure bank 2's clock parameters in bank 3's pll in
350 * cases where they differ.
352 static void p4080_erratum_serdes8(serdes_corenet_t
*regs
, ccsr_gur_t
*gur
,
353 u32 devdisr
, u32 devdisr2
, int cfg
)
359 * The disabled lanes of bank 2 will cause the associated
360 * logic blocks to be disabled in DEVDISR. We reverse that here.
362 * Note that normally it is not permitted to clear DEVDISR bits
363 * once the device has been disabled, but the hardware people
364 * say that this special case is OK.
366 clrbits_be32(&gur
->devdisr
, devdisr
);
367 clrbits_be32(&gur
->devdisr2
, devdisr2
);
370 * Some protocols require special handling. There are a few
371 * additional protocol configurations that can be used, which are
372 * not listed here. See app note 4065 for supported protocol
378 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
379 * SGMII on bank 3 should still be usable.
381 setbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr1
,
382 SRDS_PLLCR1_PLL_BWSEL
);
388 * Banks 2 (XAUI) and 3 (SGMII) have different clocking
389 * requirements in these configurations. Bank 3 cannot
390 * be used and should have its lanes (but not the bank
391 * itself) disabled in the RCW. We set up bank 3's pll
392 * for bank 2's needs here.
394 srds_ratio_b2
= (in_be32(&gur
->rcwsr
[4]) >> 13) & 7;
396 /* Determine refclock from XAUI ratio */
397 switch (srds_ratio_b2
) {
399 rfck_sel
= SRDS_PLLCR0_RFCK_SEL_156_25
;
402 rfck_sel
= SRDS_PLLCR0_RFCK_SEL_125
;
405 printf("SERDES: bad SRDS_RATIO_B2 %d\n",
410 clrsetbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr0
,
411 SRDS_PLLCR0_RFCK_SEL_MASK
, rfck_sel
);
413 clrsetbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr0
,
414 SRDS_PLLCR0_FRATE_SEL_MASK
,
415 SRDS_PLLCR0_FRATE_SEL_6_25
);
419 enable_bank(gur
, FSL_SRDS_BANK_3
);
423 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
425 * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
426 * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
428 static void p4080_erratum_serdes_a005(serdes_corenet_t
*regs
, unsigned int cfg
)
430 enum srds_prtcl device
;
436 * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
439 clrbits_be32(®s
->bank
[FSL_SRDS_BANK_1
].pllcr1
,
440 SRDS_PLLCR1_PLL_BWSEL
);
444 * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
445 * SRDSB3PLLCR1[PLLBW_SEL] to 1.
447 clrbits_be32(®s
->bank
[FSL_SRDS_BANK_1
].pllcr1
,
448 SRDS_PLLCR1_PLL_BWSEL
);
449 setbits_be32(®s
->bank
[FSL_SRDS_BANK_3
].pllcr1
,
450 SRDS_PLLCR1_PLL_BWSEL
);
455 * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
456 * before XAUI is initialized.
458 for (device
= XAUI_FM1
; device
<= XAUI_FM2
; device
++) {
459 if (is_serdes_configured(device
)) {
460 int bank
= serdes_get_bank_by_device(cfg
, device
);
462 clrbits_be32(®s
->bank
[bank
].pllcr1
,
463 SRDS_PLLCR1_PLL_BWSEL
);
470 * Wait for the RSTDONE bit to get set, or a one-second timeout.
472 static void wait_for_rstdone(unsigned int bank
)
474 serdes_corenet_t
*srds_regs
=
475 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR
;
476 unsigned long long end_tick
;
479 /* wait for reset complete or 1-second timeout */
480 end_tick
= usec2ticks(1000000) + get_ticks();
482 rstctl
= in_be32(&srds_regs
->bank
[bank
].rstctl
);
483 if (rstctl
& SRDS_RSTCTL_RSTDONE
)
485 } while (end_tick
> get_ticks());
487 if (!(rstctl
& SRDS_RSTCTL_RSTDONE
))
488 printf("SERDES: timeout resetting bank %u\n", bank
+ 1);
492 static void __soc_serdes_init(void)
494 /* Allow for SoC-specific initialization in <SOC>_serdes.c */
496 void soc_serdes_init(void) __attribute__((weak
, alias("__soc_serdes_init")));
498 void fsl_serdes_init(void)
500 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
502 serdes_corenet_t
*srds_regs
;
503 #ifdef CONFIG_PPC_P5040
504 serdes_corenet_t
*srds2_regs
;
507 int have_bank
[SRDS_MAX_BANK
] = {};
508 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
509 u32 serdes8_devdisr
= 0;
510 u32 serdes8_devdisr2
= 0;
511 char srds_lpd_opt
[16];
512 const char *srds_lpd_arg
;
515 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
516 int need_serdes_a001
; /* TRUE == need work-around for SERDES A001 */
518 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
519 char buffer
[HWCONFIG_BUFFER_SIZE
];
523 * Extract hwconfig from environment since we have not properly setup
524 * the environment but need it for ddr config params
526 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
530 /* Is serdes enabled at all? */
531 if (!(in_be32(&gur
->rcwsr
[5]) & FSL_CORENET_RCWSR5_SRDS_EN
))
534 srds_regs
= (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR
);
535 cfg
= (in_be32(&gur
->rcwsr
[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL
) >> 26;
536 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg
);
538 if (!is_serdes_prtcl_valid(cfg
)) {
539 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg
);
543 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
545 * Display a warning if banks two and three are not disabled in the RCW,
546 * since our work-around for SERDES8 depends on these banks being
547 * disabled at power-on.
549 #define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
550 if ((in_be32(&gur
->rcwsr
[5]) & B2_B3
) != B2_B3
) {
551 printf("Warning: SERDES8 requires banks two and "
552 "three to be disabled in the RCW\n");
556 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
557 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds
558 * for a description of these options.
560 for (bank
= 1; bank
< ARRAY_SIZE(srds_lpd_b
); bank
++) {
561 sprintf(srds_lpd_opt
, "fsl_srds_lpd_b%u", bank
+ 1);
563 hwconfig_subarg_f("serdes", srds_lpd_opt
, &arglen
, buf
);
566 simple_strtoul(srds_lpd_arg
, NULL
, 0) & 0xf;
569 if ((cfg
== 0xf) || (cfg
== 0x10)) {
571 * For SERDES protocols 0xF and 0x10, force bank 3 to be
572 * disabled, because it is not supported.
574 srds_lpd_b
[FSL_SRDS_BANK_3
] = 0xF;
578 /* Look for banks with all lanes disabled, and power down the bank. */
579 for (lane
= 0; lane
< SRDS_MAX_LANES
; lane
++) {
580 enum srds_prtcl lane_prtcl
= serdes_get_prtcl(cfg
, lane
);
581 if (serdes_lane_enabled(lane
)) {
582 have_bank
[serdes_get_bank_by_lane(lane
)] = 1;
583 serdes_prtcl_map
|= (1 << lane_prtcl
);
587 #ifdef CONFIG_PPC_P5040
589 * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
590 * protocols, these lanes are routed to SATA. We use serdes_prtcl_map
591 * to decide whether a protocol is supported on a given lane, so SATA
592 * will be identified as not supported, and therefore not initialized.
593 * So for protocols which use SATA on bank4, we add SATA support in
605 serdes_prtcl_map
|= 1 << SATA1
| 1 << SATA2
;
608 srds2_regs
= (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR
;
610 /* We don't need bank 4, so power it down */
611 setbits_be32(&srds2_regs
->bank
[0].rstctl
, SRDS_RSTCTL_SDPD
);
617 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
619 * Bank two uses the clock from bank three, so if bank two is enabled,
620 * then bank three must also be enabled.
622 if (have_bank
[FSL_SRDS_BANK_2
])
623 have_bank
[FSL_SRDS_BANK_3
] = 1;
626 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
628 * The work-aroud for erratum SERDES-A001 is needed only if bank two
629 * is disabled and bank three is enabled. The converse is also true,
630 * but SERDES8 ensures that bank 3 is always enabled if bank 2 is
631 * enabled, so there's no point in complicating the code to handle
635 !have_bank
[FSL_SRDS_BANK_2
] && have_bank
[FSL_SRDS_BANK_3
];
638 /* Power down the banks we're not interested in */
639 for (bank
= 0; bank
< SRDS_MAX_BANK
; bank
++) {
640 if (!have_bank
[bank
]) {
641 printf("SERDES: bank %d disabled\n", bank
+ 1);
642 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
644 * Erratum SERDES-A001 says bank two needs to be powered
645 * down after bank three is powered up, so don't power
646 * down bank two here.
648 if (!need_serdes_a001
|| (bank
!= FSL_SRDS_BANK_2
))
649 setbits_be32(&srds_regs
->bank
[bank
].rstctl
,
652 setbits_be32(&srds_regs
->bank
[bank
].rstctl
,
658 #ifdef CONFIG_SYS_FSL_ERRATUM_A004699
660 * To avoid the situation that resulted in the P4080 erratum
661 * SERDES-8, a given SerDes bank will use the PLLs from the previous
662 * bank if one of the PLL frequencies is a multiple of the other. For
663 * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
664 * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says
665 * that, in this situation, lane synchronization is not initiated. So
666 * when we detect a bank with a "borrowed" PLL, we have to manually
667 * initiate lane synchronization.
669 for (bank
= FSL_SRDS_BANK_2
; bank
<= FSL_SRDS_BANK_3
; bank
++) {
670 /* Determine the first lane for this bank */
673 for (lane
= 0; lane
< SRDS_MAX_LANES
; lane
++)
674 if (lanes
[lane
].bank
== bank
)
676 idx
= lanes
[lane
].idx
;
679 * Check if the PLL for the bank is borrowed. The UOTHL
680 * bit of the first lane will tell us that.
682 if (in_be32(&srds_regs
->lane
[idx
].gcr0
) & SRDS_GCR0_UOTHL
) {
683 /* Manually start lane synchronization */
684 setbits_be32(&srds_regs
->bank
[bank
].pllcr0
,
685 SRDS_PLLCR0_PVCOCNT_EN
);
690 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
691 for (lane
= 0; lane
< SRDS_MAX_LANES
; lane
++) {
692 enum srds_prtcl lane_prtcl
;
694 idx
= serdes_get_lane_idx(lane
);
695 lane_prtcl
= serdes_get_prtcl(cfg
, lane
);
712 printf("%s ", serdes_prtcl_str
[lane_prtcl
]);
715 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
717 * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
718 * for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
719 * or AURORA before the device is initialized.
721 * Note that this part of the SERDES-9 work-around is
722 * redundant if the work-around for A-4580 has already been
725 switch (lane_prtcl
) {
726 case SGMII_FM1_DTSEC1
:
727 case SGMII_FM1_DTSEC2
:
728 case SGMII_FM1_DTSEC3
:
729 case SGMII_FM1_DTSEC4
:
730 case SGMII_FM2_DTSEC1
:
731 case SGMII_FM2_DTSEC2
:
732 case SGMII_FM2_DTSEC3
:
733 case SGMII_FM2_DTSEC4
:
734 case SGMII_FM2_DTSEC5
:
740 out_be32(&srds_regs
->lane
[idx
].ttlcr0
,
741 SRDS_TTLCR0_FLT_SEL_KFR_26
|
742 SRDS_TTLCR0_FLT_SEL_KPH_28
|
743 SRDS_TTLCR0_FLT_SEL_750PPM
|
744 SRDS_TTLCR0_FREQOVD_EN
);
751 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
752 switch (lane_prtcl
) {
756 serdes8_devdisr
|= FSL_CORENET_DEVDISR_PCIE1
>>
757 (lane_prtcl
- PCIE1
);
761 serdes8_devdisr
|= FSL_CORENET_DEVDISR_SRIO1
>>
762 (lane_prtcl
- SRIO1
);
764 case SGMII_FM1_DTSEC1
:
765 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
766 FSL_CORENET_DEVDISR2_DTSEC1_1
;
768 case SGMII_FM1_DTSEC2
:
769 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
770 FSL_CORENET_DEVDISR2_DTSEC1_2
;
772 case SGMII_FM1_DTSEC3
:
773 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
774 FSL_CORENET_DEVDISR2_DTSEC1_3
;
776 case SGMII_FM1_DTSEC4
:
777 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
778 FSL_CORENET_DEVDISR2_DTSEC1_4
;
780 case SGMII_FM2_DTSEC1
:
781 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
782 FSL_CORENET_DEVDISR2_DTSEC2_1
;
784 case SGMII_FM2_DTSEC2
:
785 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
786 FSL_CORENET_DEVDISR2_DTSEC2_2
;
788 case SGMII_FM2_DTSEC3
:
789 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
790 FSL_CORENET_DEVDISR2_DTSEC2_3
;
792 case SGMII_FM2_DTSEC4
:
793 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
794 FSL_CORENET_DEVDISR2_DTSEC2_4
;
796 case SGMII_FM2_DTSEC5
:
797 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
798 FSL_CORENET_DEVDISR2_DTSEC2_5
;
801 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM1
|
802 FSL_CORENET_DEVDISR2_10GEC1
;
805 serdes8_devdisr2
|= FSL_CORENET_DEVDISR2_FM2
|
806 FSL_CORENET_DEVDISR2_10GEC2
;
822 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
823 p4080_erratum_serdes_a005(srds_regs
, cfg
);
826 for (idx
= 0; idx
< SRDS_MAX_BANK
; idx
++) {
829 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
831 * Change bank init order to 0, 2, 1, so that the third bank's
832 * PLL is established before we start the second bank. The
833 * second bank uses the third bank's PLL.
837 bank
= FSL_SRDS_BANK_3
;
839 bank
= FSL_SRDS_BANK_2
;
842 /* Skip disabled banks */
843 if (!have_bank
[bank
])
846 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
849 * Re-enable devices on banks two and three that were
850 * disabled by the RCW, and then enable bank three. The
851 * devices need to be enabled before either bank is
854 p4080_erratum_serdes8(srds_regs
, gur
, serdes8_devdisr
,
855 serdes8_devdisr2
, cfg
);
856 } else if (idx
== 2) {
857 /* Enable bank two now that bank three is enabled. */
858 enable_bank(gur
, FSL_SRDS_BANK_2
);
862 wait_for_rstdone(bank
);
865 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
866 if (need_serdes_a001
) {
867 /* Bank 3 has been enabled, so now we can disable bank 2 */
868 setbits_be32(&srds_regs
->bank
[FSL_SRDS_BANK_2
].rstctl
,