arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
   3  * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
   4  * SDRAM controller. Those are all current 405 PPC's.
   5  *
   6  * (C) Copyright 2001
   7  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   8  *
   9  * Based on code by:
  10  *
  11  * Kenneth Johansson ,Ericsson AB.
  12  * kenneth.johansson@etx.ericsson.se
  13  *
  14  * hacked up by bill hunter. fixed so we could run before
  15  * serial_init and console_init. previous version avoided this by
  16  * running out of cache memory during serial/console init, then running
  17  * this code later.
  18  *
  19  * (C) Copyright 2002
  20  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  21  * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
  22  *
  23  * (C) Copyright 2005
  24  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  25  *
  26  * SPDX-License-Identifier:     GPL-2.0+
  27  */
  28
  29 #include <common.h>
  30 #include <asm/processor.h>
  31 #include <i2c.h>
  32 #include <asm/ppc4xx.h>
  33
  34 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
  35
  36 /*
  37  * Set default values
  38  */
  39 #ifndef CONFIG_SYS_I2C_SPEED
  40 #define CONFIG_SYS_I2C_SPEED    50000
  41 #endif
  42
  43 #define ONE_BILLION     1000000000
  44
  45 #define  SDRAM0_CFG_DCE         0x80000000
  46 #define  SDRAM0_CFG_SRE         0x40000000
  47 #define  SDRAM0_CFG_PME         0x20000000
  48 #define  SDRAM0_CFG_MEMCHK      0x10000000
  49 #define  SDRAM0_CFG_REGEN       0x08000000
  50 #define  SDRAM0_CFG_ECCDD       0x00400000
  51 #define  SDRAM0_CFG_EMDULR      0x00200000
  52 #define  SDRAM0_CFG_DRW_SHIFT   (31-6)
  53 #define  SDRAM0_CFG_BRPF_SHIFT  (31-8)
  54
  55 #define  SDRAM0_TR_CASL_SHIFT   (31-8)
  56 #define  SDRAM0_TR_PTA_SHIFT    (31-13)
  57 #define  SDRAM0_TR_CTP_SHIFT    (31-15)
  58 #define  SDRAM0_TR_LDF_SHIFT    (31-17)
  59 #define  SDRAM0_TR_RFTA_SHIFT   (31-29)
  60 #define  SDRAM0_TR_RCD_SHIFT    (31-31)
  61
  62 #define  SDRAM0_RTR_SHIFT       (31-15)
  63 #define  SDRAM0_ECCCFG_SHIFT    (31-11)
  64
  65 /* SDRAM0_CFG enable macro  */
  66 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
  67
  68 #define SDRAM0_BXCR_SZ_MASK     0x000e0000
  69 #define SDRAM0_BXCR_AM_MASK     0x0000e000
  70
  71 #define SDRAM0_BXCR_SZ_SHIFT    (31-14)
  72 #define SDRAM0_BXCR_AM_SHIFT    (31-18)
  73
  74 #define SDRAM0_BXCR_SZ(x)       ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
  75 #define SDRAM0_BXCR_AM(x)       ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
  76
  77 #ifdef CONFIG_SPDDRAM_SILENT
  78 # define SPD_ERR(x) do { return 0; } while (0)
  79 #else
  80 # define SPD_ERR(x) do { printf(x); return(0); } while (0)
  81 #endif
  82
  83 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
  84
  85 /* function prototypes */
  86 int spd_read(uint addr);
  87
  88
  89 /*
  90  * This function is reading data from the DIMM module EEPROM over the SPD bus
  91  * and uses that to program the sdram controller.
  92  *
  93  * This works on boards that has the same schematics that the AMCC walnut has.
  94  *
  95  * Input: null for default I2C spd functions or a pointer to a custom function
  96  * returning spd_data.
  97  */
  98
  99 long int spd_sdram(int(read_spd)(uint addr))
 100 {
 101         int tmp,row,col;
 102         int total_size,bank_size,bank_code;
 103         int mode;
 104         int bank_cnt;
 105
 106         int sdram0_pmit=0x07c00000;
 107         int sdram0_b0cr;
 108         int sdram0_b1cr = 0;
 109 #ifndef CONFIG_405EP /* not on PPC405EP */
 110         int sdram0_b2cr = 0;
 111         int sdram0_b3cr = 0;
 112         int sdram0_besr0 = -1;
 113         int sdram0_besr1 = -1;
 114         int sdram0_eccesr = -1;
 115         int sdram0_ecccfg;
 116         int ecc_on;
 117 #endif
 118
 119         int sdram0_rtr=0;
 120         int sdram0_tr=0;
 121
 122         int sdram0_cfg=0;
 123
 124         int t_rp;
 125         int t_rcd;
 126         int t_ras;
 127         int t_rc;
 128         int min_cas;
 129
 130         PPC4xx_SYS_INFO sys_info;
 131         unsigned long bus_period_x_10;
 132
 133         /*
 134          * get the board info
 135          */
 136         get_sys_info(&sys_info);
 137         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 138
 139         if (read_spd == 0){
 140                 read_spd=spd_read;
 141                 /*
 142                  * Make sure I2C controller is initialized
 143                  * before continuing.
 144                  */
 145                 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 146         }
 147
 148         /* Make shure we are using SDRAM */
 149         if (read_spd(2) != 0x04) {
 150                 SPD_ERR("SDRAM - non SDRAM memory module found\n");
 151         }
 152
 153         /* ------------------------------------------------------------------
 154          * configure memory timing register
 155          *
 156          * data from DIMM:
 157          * 27   IN Row Precharge Time ( t RP)
 158          * 29   MIN RAS to CAS Delay ( t RCD)
 159          * 127   Component and Clock Detail ,clk0-clk3, junction temp, CAS
 160          * -------------------------------------------------------------------*/
 161
 162         /*
 163          * first figure out which cas latency mode to use
 164          * use the min supported mode
 165          */
 166
 167         tmp = read_spd(127) & 0x6;
 168         if (tmp == 0x02) {              /* only cas = 2 supported */
 169                 min_cas = 2;
 170 /*              t_ck = read_spd(9); */
 171 /*              t_ac = read_spd(10); */
 172         } else if (tmp == 0x04) {       /* only cas = 3 supported */
 173                 min_cas = 3;
 174 /*              t_ck = read_spd(9); */
 175 /*              t_ac = read_spd(10); */
 176         } else if (tmp == 0x06) {       /* 2,3 supported, so use 2 */
 177                 min_cas = 2;
 178 /*              t_ck = read_spd(23); */
 179 /*              t_ac = read_spd(24); */
 180         } else {
 181                 SPD_ERR("SDRAM - unsupported CAS latency \n");
 182         }
 183
 184         /* get some timing values, t_rp,t_rcd,t_ras,t_rc
 185          */
 186         t_rp = read_spd(27);
 187         t_rcd = read_spd(29);
 188         t_ras = read_spd(30);
 189         t_rc = t_ras + t_rp;
 190
 191         /* The following timing calcs subtract 1 before deviding.
 192          * this has effect of using ceiling instead of floor rounding,
 193          * and also subtracting 1 to convert number to reg value
 194          */
 195         /* set up CASL */
 196         sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
 197         /* set up PTA */
 198         sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
 199         /* set up CTP */
 200         tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
 201         if (tmp < 1)
 202                 tmp = 1;
 203         sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
 204         /* set LDF      = 2 cycles, reg value = 1 */
 205         sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
 206         /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
 207         tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
 208         if (tmp < 0)
 209                 tmp = 0;
 210         if (tmp > 6)
 211                 tmp = 6;
 212         sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
 213         /* set RCD = t_rcd/bus_period*/
 214         sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
 215
 216
 217         /*------------------------------------------------------------------
 218          * configure RTR register
 219          * -------------------------------------------------------------------*/
 220         row = read_spd(3);
 221         col = read_spd(4);
 222         tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
 223         switch (tmp) {
 224         case 0x00:
 225                 tmp = 15625;
 226                 break;
 227         case 0x01:
 228                 tmp = 15625 / 4;
 229                 break;
 230         case 0x02:
 231                 tmp = 15625 / 2;
 232                 break;
 233         case 0x03:
 234                 tmp = 15625 * 2;
 235                 break;
 236         case 0x04:
 237                 tmp = 15625 * 4;
 238                 break;
 239         case 0x05:
 240                 tmp = 15625 * 8;
 241                 break;
 242         default:
 243                 SPD_ERR("SDRAM - Bad refresh period \n");
 244         }
 245         /* convert from nsec to bus cycles */
 246         tmp = (tmp * 10) / bus_period_x_10;
 247         sdram0_rtr = (tmp & 0x3ff8) <<  SDRAM0_RTR_SHIFT;
 248
 249         /*------------------------------------------------------------------
 250          * determine the number of banks used
 251          * -------------------------------------------------------------------*/
 252         /* byte 7:6 is module data width */
 253         if (read_spd(7) != 0)
 254                 SPD_ERR("SDRAM - unsupported module width\n");
 255         tmp = read_spd(6);
 256         if (tmp < 32)
 257                 SPD_ERR("SDRAM - unsupported module width\n");
 258         else if (tmp < 64)
 259                 bank_cnt = 1;           /* one bank per sdram side */
 260         else if (tmp < 73)
 261                 bank_cnt = 2;   /* need two banks per side */
 262         else if (tmp < 161)
 263                 bank_cnt = 4;   /* need four banks per side */
 264         else
 265                 SPD_ERR("SDRAM - unsupported module width\n");
 266
 267         /* byte 5 is the module row count (refered to as dimm "sides") */
 268         tmp = read_spd(5);
 269         if (tmp == 1)
 270                 ;
 271         else if (tmp==2)
 272                 bank_cnt *= 2;
 273         else if (tmp==4)
 274                 bank_cnt *= 4;
 275         else
 276                 bank_cnt = 8;           /* 8 is an error code */
 277
 278         if (bank_cnt > 4)       /* we only have 4 banks to work with */
 279                 SPD_ERR("SDRAM - unsupported module rows for this width\n");
 280
 281 #ifndef CONFIG_405EP /* not on PPC405EP */
 282         /* now check for ECC ability of module. We only support ECC
 283          *   on 32 bit wide devices with 8 bit ECC.
 284          */
 285         if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
 286                 sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
 287                 ecc_on = 1;
 288         } else {
 289                 sdram0_ecccfg = 0;
 290                 ecc_on = 0;
 291         }
 292 #endif
 293
 294         /*------------------------------------------------------------------
 295          * calculate total size
 296          * -------------------------------------------------------------------*/
 297         /* calculate total size and do sanity check */
 298         tmp = read_spd(31);
 299         total_size = 1 << 22;   /* total_size = 4MB */
 300         /* now multiply 4M by the smallest device row density */
 301         /* note that we don't support asymetric rows */
 302         while (((tmp & 0x0001) == 0) && (tmp != 0)) {
 303                 total_size = total_size << 1;
 304                 tmp = tmp >> 1;
 305         }
 306         total_size *= read_spd(5);      /* mult by module rows (dimm sides) */
 307
 308         /*------------------------------------------------------------------
 309          * map  rows * cols * banks to a mode
 310          * -------------------------------------------------------------------*/
 311
 312         switch (row) {
 313         case 11:
 314                 switch (col) {
 315                 case 8:
 316                         mode=4; /* mode 5 */
 317                         break;
 318                 case 9:
 319                 case 10:
 320                         mode=0; /* mode 1 */
 321                         break;
 322                 default:
 323                         SPD_ERR("SDRAM - unsupported mode\n");
 324                 }
 325                 break;
 326         case 12:
 327                 switch (col) {
 328                 case 8:
 329                         mode=3; /* mode 4 */
 330                         break;
 331                 case 9:
 332                 case 10:
 333                         mode=1; /* mode 2 */
 334                         break;
 335                 default:
 336                         SPD_ERR("SDRAM - unsupported mode\n");
 337                 }
 338                 break;
 339         case 13:
 340                 switch (col) {
 341                 case 8:
 342                         mode=5; /* mode 6 */
 343                         break;
 344                 case 9:
 345                 case 10:
 346                         if (read_spd(17) == 2)
 347                                 mode = 6; /* mode 7 */
 348                         else
 349                                 mode = 2; /* mode 3 */
 350                         break;
 351                 case 11:
 352                         mode = 2; /* mode 3 */
 353                         break;
 354                 default:
 355                         SPD_ERR("SDRAM - unsupported mode\n");
 356                 }
 357                 break;
 358         default:
 359                 SPD_ERR("SDRAM - unsupported mode\n");
 360         }
 361
 362         /*------------------------------------------------------------------
 363          * using the calculated values, compute the bank
 364          * config register values.
 365          * -------------------------------------------------------------------*/
 366
 367         /* compute the size of each bank */
 368         bank_size = total_size / bank_cnt;
 369         /* convert bank size to bank size code for ppc4xx
 370            by takeing log2(bank_size) - 22 */
 371         tmp = bank_size;                /* start with tmp = bank_size */
 372         bank_code = 0;                  /* and bank_code = 0 */
 373         while (tmp > 1) {               /* this takes log2 of tmp */
 374                 bank_code++;            /* and stores result in bank_code */
 375                 tmp = tmp >> 1;
 376         }                               /* bank_code is now log2(bank_size) */
 377         bank_code -= 22;                /* subtract 22 to get the code */
 378
 379         tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
 380         sdram0_b0cr = (bank_size * 0) | tmp;
 381 #ifndef CONFIG_405EP /* not on PPC405EP */
 382         if (bank_cnt > 1)
 383                 sdram0_b2cr = (bank_size * 1) | tmp;
 384         if (bank_cnt > 2)
 385                 sdram0_b1cr = (bank_size * 2) | tmp;
 386         if (bank_cnt > 3)
 387                 sdram0_b3cr = (bank_size * 3) | tmp;
 388 #else
 389         /* PPC405EP chip only supports two SDRAM banks */
 390         if (bank_cnt > 1)
 391                 sdram0_b1cr = (bank_size * 1) | tmp;
 392         if (bank_cnt > 2)
 393                 total_size = 2 * bank_size;
 394 #endif
 395
 396         /*
 397          *   enable sdram controller DCE=1
 398          *  enable burst read prefetch to 32 bytes BRPF=2
 399          *  leave other functions off
 400          */
 401
 402         /*------------------------------------------------------------------
 403          * now that we've done our calculations, we are ready to
 404          * program all the registers.
 405          * -------------------------------------------------------------------*/
 406
 407         /* disable memcontroller so updates work */
 408         mtsdram(SDRAM0_CFG, 0);
 409
 410 #ifndef CONFIG_405EP /* not on PPC405EP */
 411         mtsdram(SDRAM0_BESR0, sdram0_besr0);
 412         mtsdram(SDRAM0_BESR1, sdram0_besr1);
 413         mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg);
 414         mtsdram(SDRAM0_ECCESR, sdram0_eccesr);
 415 #endif
 416         mtsdram(SDRAM0_RTR, sdram0_rtr);
 417         mtsdram(SDRAM0_PMIT, sdram0_pmit);
 418         mtsdram(SDRAM0_B0CR, sdram0_b0cr);
 419         mtsdram(SDRAM0_B1CR, sdram0_b1cr);
 420 #ifndef CONFIG_405EP /* not on PPC405EP */
 421         mtsdram(SDRAM0_B2CR, sdram0_b2cr);
 422         mtsdram(SDRAM0_B3CR, sdram0_b3cr);
 423 #endif
 424         mtsdram(SDRAM0_TR, sdram0_tr);
 425
 426         /* SDRAM have a power on delay,  500 micro should do */
 427         udelay(500);
 428         sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
 429 #ifndef CONFIG_405EP /* not on PPC405EP */
 430         if (ecc_on)
 431                 sdram0_cfg |= SDRAM0_CFG_MEMCHK;
 432 #endif
 433         mtsdram(SDRAM0_CFG, sdram0_cfg);
 434
 435         return (total_size);
 436 }
 437
 438 int spd_read(uint addr)
 439 {
 440         uchar data[2];
 441
 442         if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
 443                 return (int)data[0];
 444         else
 445                 return 0;
 446 }
 447
 448 #endif /* CONFIG_SPD_EEPROM */