2 * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those currently are:
7 * 440/460: 440SP/440SPe/460EX/460GT/460SX
9 * (C) Copyright 2008 Applied Micro Circuits Corporation
10 * Adam Graham <agraham@amcc.com>
12 * (C) Copyright 2007-2008
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
15 * COPYRIGHT AMCC CORPORATION 2004
17 * SPDX-License-Identifier: GPL-2.0+
20 /* define DEBUG for debugging output (obviously ;-)) */
24 #include <asm/ppc4xx.h>
26 #include <asm/processor.h>
31 #define SDRAM_RXBAS_SHIFT_1M 20
33 #if defined(CONFIG_SYS_DECREMENT_PATTERNS)
34 #define NUMMEMTESTS 24
37 #endif /* CONFIG_SYS_DECREMENT_PATTERNS */
38 #define NUMLOOPS 1 /* configure as you deem approporiate */
39 #define NUMMEMWORDS 16
41 #define SDRAM_RDCC_RDSS_VAL(n) SDRAM_RDCC_RDSS_DECODE(ddr_rdss_opt(n))
43 /* Private Structure Definitions */
61 struct sdram_timing_clks
{
69 struct sdram_timing_clks clocks
;
70 struct ddrautocal autocal
;
73 /*--------------------------------------------------------------------------+
75 *--------------------------------------------------------------------------*/
76 #if defined(CONFIG_PPC4xx_DDR_METHOD_A)
77 static u32
DQS_calibration_methodA(struct ddrautocal
*);
78 static u32
program_DQS_calibration_methodA(struct ddrautocal
*);
80 static u32
DQS_calibration_methodB(struct ddrautocal
*);
81 static u32
program_DQS_calibration_methodB(struct ddrautocal
*);
83 static int short_mem_test(u32
*);
86 * To provide an interface for board specific config values in this common
87 * DDR setup code, we implement he "weak" default functions here. They return
88 * the default value back to the caller.
90 * Please see include/configs/yucca.h for an example fora board specific
94 #if !defined(CONFIG_SPD_EEPROM)
95 u32
__ddr_wrdtr(u32 default_val
)
99 u32
ddr_wrdtr(u32
) __attribute__((weak
, alias("__ddr_wrdtr")));
101 u32
__ddr_clktr(u32 default_val
)
105 u32
ddr_clktr(u32
) __attribute__((weak
, alias("__ddr_clktr")));
108 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
110 void __spd_ddr_init_hang(void)
115 spd_ddr_init_hang(void) __attribute__((weak
, alias("__spd_ddr_init_hang")));
116 #endif /* defined(CONFIG_SPD_EEPROM) */
118 struct sdram_timing
*__ddr_scan_option(struct sdram_timing
*default_val
)
122 struct sdram_timing
*ddr_scan_option(struct sdram_timing
*)
123 __attribute__((weak
, alias("__ddr_scan_option")));
125 u32
__ddr_rdss_opt(u32 default_val
)
129 u32
ddr_rdss_opt(ulong
) __attribute__((weak
, alias("__ddr_rdss_opt")));
132 static u32
*get_membase(int bxcr_num
)
136 #if defined(SDRAM_R0BAS)
137 /* BAS from Memory Queue rank reg. */
139 (u32
*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS
+bxcr_num
)));
144 /* BAS from SDRAM_MBxCF mem rank reg. */
145 mfsdram(SDRAM_MB0CF
+ (bxcr_num
<<2), bxcf
);
146 membase
= (u32
*)((bxcf
& 0xfff80000) << 3);
153 static inline void ecc_clear_status_reg(void)
155 mtsdram(SDRAM_ECCES
, 0xffffffff);
156 #if defined(SDRAM_R0BAS)
157 mtdcr(SDRAM_ERRSTATLL
, 0xffffffff);
162 * Reset and relock memory DLL after SDRAM_CLKTR change
164 static inline void relock_memory_DLL(void)
168 mtsdram(SDRAM_MCOPT2
, SDRAM_MCOPT2_IPTR_EXECUTE
);
171 mfsdram(SDRAM_MCSTAT
, reg
);
172 } while (!(reg
& SDRAM_MCSTAT_MIC_COMP
));
174 mfsdram(SDRAM_MCOPT2
, reg
);
175 mtsdram(SDRAM_MCOPT2
, reg
| SDRAM_MCOPT2_DCEN_ENABLE
);
178 static int ecc_check_status_reg(void)
183 * Compare suceeded, now check
184 * if got ecc error. If got an
185 * ecc error, then don't count
186 * this as a passing value
188 mfsdram(SDRAM_ECCES
, ecc_status
);
189 if (ecc_status
!= 0x00000000) {
191 ecc_clear_status_reg();
192 /* ecc check failure */
195 ecc_clear_status_reg();
201 /* return 1 if passes, 0 if fail */
202 static int short_mem_test(u32
*base_address
)
207 ulong test
[NUMMEMTESTS
][NUMMEMWORDS
] = {
208 /* 0 */ {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
209 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
210 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
211 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
212 /* 1 */ {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
213 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
214 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
215 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
216 /* 2 */ {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
217 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
218 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
219 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
220 /* 3 */ {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
221 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
222 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
223 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
224 /* 4 */ {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
225 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
226 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
227 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
228 /* 5 */ {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
229 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
230 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
231 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
232 /* 6 */ {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
233 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
234 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
235 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
236 /* 7 */ {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
237 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
238 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
239 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55},
241 #if defined(CONFIG_SYS_DECREMENT_PATTERNS)
242 /* 8 */ {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
243 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
244 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
245 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff},
246 /* 9 */ {0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
247 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
248 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
249 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe},
250 /* 10 */{0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
251 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
252 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
253 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd},
254 /* 11 */{0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
255 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
256 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
257 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc},
258 /* 12 */{0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
259 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
260 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
261 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb},
262 /* 13 */{0xfffafffa, 0xfffafffa, 0xfffffffa, 0xfffafffa,
263 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
264 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
265 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa},
266 /* 14 */{0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
267 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
268 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
269 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9},
270 /* 15 */{0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
271 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
272 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
273 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8},
274 /* 16 */{0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
275 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
276 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
277 0xfff7ffff, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7},
278 /* 17 */{0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
279 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
280 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
281 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7},
282 /* 18 */{0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
283 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
284 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
285 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5},
286 /* 19 */{0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
287 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
288 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
289 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4},
290 /* 20 */{0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
291 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
292 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
293 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3},
294 /* 21 */{0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
295 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
296 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
297 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2},
298 /* 22 */{0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
299 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
300 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
301 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1},
302 /* 23 */{0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
303 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
304 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
305 0xfff0fff0, 0xfff0fffe, 0xfff0fff0, 0xfff0fff0},
306 #endif /* CONFIG_SYS_DECREMENT_PATTERNS */
309 mfsdram(SDRAM_MCOPT1
, ecc_mode
);
310 if ((ecc_mode
& SDRAM_MCOPT1_MCHK_CHK_REP
) ==
311 SDRAM_MCOPT1_MCHK_CHK_REP
) {
312 ecc_clear_status_reg();
320 * Run the short memory test.
322 for (i
= 0; i
< NUMMEMTESTS
; i
++) {
323 for (j
= 0; j
< NUMMEMWORDS
; j
++) {
324 base_address
[j
] = test
[i
][j
];
325 ppcDcbf((ulong
)&(base_address
[j
]));
329 for (l
= 0; l
< NUMLOOPS
; l
++) {
330 for (j
= 0; j
< NUMMEMWORDS
; j
++) {
331 if (base_address
[j
] != test
[i
][j
]) {
332 ppcDcbf((u32
)&(base_address
[j
]));
336 if (!ecc_check_status_reg())
340 ppcDcbf((u32
)&(base_address
[j
]));
341 } /* for (j = 0; j < NUMMEMWORDS; j++) */
344 } /* for (l=0; l<NUMLOOPS; l++) */
350 #if defined(CONFIG_PPC4xx_DDR_METHOD_A)
351 /*-----------------------------------------------------------------------------+
352 | program_DQS_calibration_methodA.
353 +-----------------------------------------------------------------------------*/
354 static u32
program_DQS_calibration_methodA(struct ddrautocal
*ddrcal
)
361 mfsdram(SDRAM_RDCC
, temp
);
362 debug("<%s>SDRAM_RDCC=0x%08x\n", __func__
, temp
);
365 pass_result
= DQS_calibration_methodA(ddrcal
);
371 * DQS_calibration_methodA()
373 * Autocalibration Method A
375 * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros
376 * ARRAY [Entire FDBK Range] FDBK_Valid_Window; initialized to all zeros
377 * MEMWRITE(addr, expected_data);
378 * for (i = 0; i < Entire DQS Range; i++) { RQDC.RQFD
379 * for (j = 0; j < Entire FDBK Range; j++) { RFDC.RFFD
380 * MEMREAD(addr, actual_data);
381 * if (actual_data == expected_data) {
382 * DQS_Valid_Window[i] = 1; RQDC.RQFD
383 * FDBK_Valid_Window[i][j] = 1; RFDC.RFFD
388 static u32
DQS_calibration_methodA(struct ddrautocal
*cal
)
405 struct autocal_regs curr_win_min
;
406 struct autocal_regs curr_win_max
;
407 struct autocal_regs best_win_min
;
408 struct autocal_regs best_win_max
;
409 struct autocal_regs loop_win_min
;
410 struct autocal_regs loop_win_max
;
417 char slash
[] = "\\|/-\\|/-";
423 memset(&curr_win_min
, 0, sizeof(curr_win_min
));
424 memset(&curr_win_max
, 0, sizeof(curr_win_max
));
425 memset(&best_win_min
, 0, sizeof(best_win_min
));
426 memset(&best_win_max
, 0, sizeof(best_win_max
));
427 memset(&loop_win_min
, 0, sizeof(loop_win_min
));
428 memset(&loop_win_max
, 0, sizeof(loop_win_max
));
433 * Program RDCC register
434 * Read sample cycle auto-update enable
437 ddr_rdss_opt(SDRAM_RDCC_RDSS_T2
) | SDRAM_RDCC_RSAE_ENABLE
);
440 mfsdram(SDRAM_RDCC
, temp
);
441 debug("<%s>SDRAM_RDCC=0x%x\n", __func__
, temp
);
442 mfsdram(SDRAM_RTSR
, temp
);
443 debug("<%s>SDRAM_RTSR=0x%x\n", __func__
, temp
);
444 mfsdram(SDRAM_FCSR
, temp
);
445 debug("<%s>SDRAM_FCSR=0x%x\n", __func__
, temp
);
449 * Program RQDC register
450 * Internal DQS delay mechanism enable
453 SDRAM_RQDC_RQDE_ENABLE
| SDRAM_RQDC_RQFD_ENCODE(0x00));
456 mfsdram(SDRAM_RQDC
, temp
);
457 debug("<%s>SDRAM_RQDC=0x%x\n", __func__
, temp
);
461 * Program RFDC register
462 * Set Feedback Fractional Oversample
463 * Auto-detect read sample cycle enable
465 mtsdram(SDRAM_RFDC
, SDRAM_RFDC_ARSE_ENABLE
|
466 SDRAM_RFDC_RFOS_ENCODE(0) | SDRAM_RFDC_RFFD_ENCODE(0));
469 mfsdram(SDRAM_RFDC
, temp
);
470 debug("<%s>SDRAM_RFDC=0x%x\n", __func__
, temp
);
474 for (rqfd
= 0; rqfd
<= SDRAM_RQDC_RQFD_MAX
; rqfd
++) {
476 mfsdram(SDRAM_RQDC
, rqdc_reg
);
477 rqdc_reg
&= ~(SDRAM_RQDC_RQFD_MASK
);
478 mtsdram(SDRAM_RQDC
, rqdc_reg
| SDRAM_RQDC_RQFD_ENCODE(rqfd
));
481 putc(slash
[loopi
++ % 8]);
483 curr_win_min
.rffd
= 0;
484 curr_win_max
.rffd
= 0;
487 for (rffd
= 0, pass
= 0; rffd
<= SDRAM_RFDC_RFFD_MAX
; rffd
++) {
488 mfsdram(SDRAM_RFDC
, rfdc_reg
);
489 rfdc_reg
&= ~(SDRAM_RFDC_RFFD_MASK
);
491 rfdc_reg
| SDRAM_RFDC_RFFD_ENCODE(rffd
));
493 for (bxcr_num
= 0; bxcr_num
< MAXBXCF
; bxcr_num
++) {
494 mfsdram(SDRAM_MB0CF
+ (bxcr_num
<<2), bxcf
);
497 if (bxcf
& SDRAM_BXCF_M_BE_MASK
) {
498 /* Bank is enabled */
499 membase
= get_membase(bxcr_num
);
500 pass
= short_mem_test(membase
);
501 } /* if bank enabled */
504 /* If this value passed update RFFD windows */
505 if (pass
&& !in_window
) { /* at the start of window */
507 curr_win_min
.rffd
= curr_win_max
.rffd
= rffd
;
508 curr_win_min
.rqfd
= curr_win_max
.rqfd
= rqfd
;
509 mfsdram(SDRAM_RDCC
, rdcc
); /*record this value*/
510 } else if (!pass
&& in_window
) { /* at end of window */
512 } else if (pass
&& in_window
) { /* within the window */
513 curr_win_max
.rffd
= rffd
;
514 curr_win_max
.rqfd
= rqfd
;
516 /* else if (!pass && !in_window)
517 skip - no pass, not currently in a window */
520 if ((curr_win_max
.rffd
- curr_win_min
.rffd
) >
521 (best_win_max
.rffd
- best_win_min
.rffd
)) {
522 best_win_min
.rffd
= curr_win_min
.rffd
;
523 best_win_max
.rffd
= curr_win_max
.rffd
;
525 best_win_min
.rqfd
= curr_win_min
.rqfd
;
526 best_win_max
.rqfd
= curr_win_max
.rqfd
;
534 * save-off the best window results of the RFDC.RFFD
535 * for this RQDC.RQFD setting
538 * if (just ended RFDC.RFDC loop pass window) >
539 * (prior RFDC.RFFD loop pass window)
541 if ((best_win_max
.rffd
- best_win_min
.rffd
) >
542 (loop_win_max
.rffd
- loop_win_min
.rffd
)) {
543 loop_win_min
.rffd
= best_win_min
.rffd
;
544 loop_win_max
.rffd
= best_win_max
.rffd
;
545 loop_win_min
.rqfd
= rqfd
;
546 loop_win_max
.rqfd
= rqfd
;
547 debug("RQFD.min 0x%08x, RQFD.max 0x%08x, "
548 "RFFD.min 0x%08x, RFFD.max 0x%08x\n",
549 loop_win_min
.rqfd
, loop_win_max
.rqfd
,
550 loop_win_min
.rffd
, loop_win_max
.rffd
);
558 if ((loop_win_min
.rffd
== 0) && (loop_win_max
.rffd
== 0) &&
559 (best_win_min
.rffd
== 0) && (best_win_max
.rffd
== 0) &&
560 (best_win_min
.rqfd
== 0) && (best_win_max
.rqfd
== 0)) {
565 * Need to program RQDC before RFDC.
567 debug("<%s> RQFD Min: 0x%x\n", __func__
, loop_win_min
.rqfd
);
568 debug("<%s> RQFD Max: 0x%x\n", __func__
, loop_win_max
.rqfd
);
569 rqfd_average
= loop_win_max
.rqfd
;
571 if (rqfd_average
< 0)
574 if (rqfd_average
> SDRAM_RQDC_RQFD_MAX
)
575 rqfd_average
= SDRAM_RQDC_RQFD_MAX
;
577 debug("<%s> RFFD average: 0x%08x\n", __func__
, rqfd_average
);
578 mtsdram(SDRAM_RQDC
, (rqdc_reg
& ~SDRAM_RQDC_RQFD_MASK
) |
579 SDRAM_RQDC_RQFD_ENCODE(rqfd_average
));
581 debug("<%s> RFFD Min: 0x%08x\n", __func__
, loop_win_min
.rffd
);
582 debug("<%s> RFFD Max: 0x%08x\n", __func__
, loop_win_max
.rffd
);
583 rffd_average
= ((loop_win_min
.rffd
+ loop_win_max
.rffd
) / 2);
585 if (rffd_average
< 0)
588 if (rffd_average
> SDRAM_RFDC_RFFD_MAX
)
589 rffd_average
= SDRAM_RFDC_RFFD_MAX
;
591 debug("<%s> RFFD average: 0x%08x\n", __func__
, rffd_average
);
592 mtsdram(SDRAM_RFDC
, rfdc_reg
| SDRAM_RFDC_RFFD_ENCODE(rffd_average
));
594 /* if something passed, then return the size of the largest window */
596 passed
= loop_win_max
.rffd
- loop_win_min
.rffd
;
597 cal
->rqfd
= rqfd_average
;
598 cal
->rffd
= rffd_average
;
599 cal
->rffd_min
= loop_win_min
.rffd
;
600 cal
->rffd_max
= loop_win_max
.rffd
;
606 #else /* !defined(CONFIG_PPC4xx_DDR_METHOD_A) */
608 /*-----------------------------------------------------------------------------+
609 | program_DQS_calibration_methodB.
610 +-----------------------------------------------------------------------------*/
611 static u32
program_DQS_calibration_methodB(struct ddrautocal
*ddrcal
)
620 * Program RDCC register
621 * Read sample cycle auto-update enable
624 ddr_rdss_opt(SDRAM_RDCC_RDSS_T2
) | SDRAM_RDCC_RSAE_ENABLE
);
627 mfsdram(SDRAM_RDCC
, temp
);
628 debug("<%s>SDRAM_RDCC=0x%08x\n", __func__
, temp
);
632 * Program RQDC register
633 * Internal DQS delay mechanism enable
636 #if defined(CONFIG_DDR_RQDC_START_VAL)
637 SDRAM_RQDC_RQDE_ENABLE
|
638 SDRAM_RQDC_RQFD_ENCODE(CONFIG_DDR_RQDC_START_VAL
));
640 SDRAM_RQDC_RQDE_ENABLE
| SDRAM_RQDC_RQFD_ENCODE(0x38));
644 mfsdram(SDRAM_RQDC
, temp
);
645 debug("<%s>SDRAM_RQDC=0x%08x\n", __func__
, temp
);
649 * Program RFDC register
650 * Set Feedback Fractional Oversample
651 * Auto-detect read sample cycle enable
653 mtsdram(SDRAM_RFDC
, SDRAM_RFDC_ARSE_ENABLE
|
654 SDRAM_RFDC_RFOS_ENCODE(0) |
655 SDRAM_RFDC_RFFD_ENCODE(0));
658 mfsdram(SDRAM_RFDC
, temp
);
659 debug("<%s>SDRAM_RFDC=0x%08x\n", __func__
, temp
);
662 pass_result
= DQS_calibration_methodB(ddrcal
);
668 * DQS_calibration_methodB()
670 * Autocalibration Method B
672 * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros
673 * ARRAY [Entire Feedback Range] FDBK_Valid_Window; initialized to all zeros
674 * MEMWRITE(addr, expected_data);
675 * Initialialize the DQS delay to 80 degrees (MCIF0_RRQDC[RQFD]=0x38).
677 * for (j = 0; j < Entire Feedback Range; j++) {
678 * MEMREAD(addr, actual_data);
679 * if (actual_data == expected_data) {
680 * FDBK_Valid_Window[j] = 1;
684 * Set MCIF0_RFDC[RFFD] to the middle of the FDBK_Valid_Window.
686 * for (i = 0; i < Entire DQS Range; i++) {
687 * MEMREAD(addr, actual_data);
688 * if (actual_data == expected_data) {
689 * DQS_Valid_Window[i] = 1;
693 * Set MCIF0_RRQDC[RQFD] to the middle of the DQS_Valid_Window.
695 /*-----------------------------------------------------------------------------+
696 | DQS_calibration_methodB.
697 +-----------------------------------------------------------------------------*/
698 static u32
DQS_calibration_methodB(struct ddrautocal
*cal
)
701 #ifndef CONFIG_DDR_RFDC_FIXED
719 u32 curr_win_min
, curr_win_max
;
720 u32 best_win_min
, best_win_max
;
723 /*------------------------------------------------------------------
724 | Test to determine the best read clock delay tuning bits.
726 | Before the DDR controller can be used, the read clock delay needs to
727 | be set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
728 | This value cannot be hardcoded into the program because it changes
729 | depending on the board's setup and environment.
730 | To do this, all delay values are tested to see if they
731 | work or not. By doing this, you get groups of fails with groups of
732 | passing values. The idea is to find the start and end of a passing
733 | window and take the center of it to use as the read clock delay.
735 | A failure has to be seen first so that when we hit a pass, we know
736 | that it is truely the start of the window. If we get passing values
737 | to start off with, we don't know if we are at the start of the window
739 | The code assumes that a failure will always be found.
740 | If a failure is not found, there is no easy way to get the middle
741 | of the passing window. I guess we can pretty much pick any value
742 | but some values will be better than others. Since the lowest speed
743 | we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
744 | from experimentation it is safe to say you will always have a failure
745 +-----------------------------------------------------------------*/
749 #if defined(CONFIG_DDR_RFDC_FIXED)
750 mtsdram(SDRAM_RFDC
, CONFIG_DDR_RFDC_FIXED
);
752 rffd_average
= CONFIG_DDR_RFDC_FIXED
& SDRAM_RFDC_RFFD_MASK
;
753 mfsdram(SDRAM_RDCC
, rdcc
); /* record this value */
755 #else /* CONFIG_DDR_RFDC_FIXED */
759 curr_win_min
= curr_win_max
= 0;
760 best_win_min
= best_win_max
= 0;
761 for (rffd
= 0; rffd
<= SDRAM_RFDC_RFFD_MAX
; rffd
++) {
762 mfsdram(SDRAM_RFDC
, rfdc_reg
);
763 rfdc_reg
&= ~(SDRAM_RFDC_RFFD_MASK
);
764 mtsdram(SDRAM_RFDC
, rfdc_reg
| SDRAM_RFDC_RFFD_ENCODE(rffd
));
767 for (bxcr_num
= 0; bxcr_num
< MAXBXCF
; bxcr_num
++) {
768 mfsdram(SDRAM_MB0CF
+ (bxcr_num
<<2), bxcf
);
771 if (bxcf
& SDRAM_BXCF_M_BE_MASK
) {
772 /* Bank is enabled */
773 membase
= get_membase(bxcr_num
);
774 pass
&= short_mem_test(membase
);
775 } /* if bank enabled */
778 /* If this value passed */
779 if (pass
&& !in_window
) { /* start of passing window */
781 curr_win_min
= curr_win_max
= rffd
;
782 mfsdram(SDRAM_RDCC
, rdcc
); /* record this value */
783 } else if (!pass
&& in_window
) { /* end passing window */
785 } else if (pass
&& in_window
) { /* within the passing window */
790 if ((curr_win_max
- curr_win_min
) >
791 (best_win_max
- best_win_min
)) {
792 best_win_min
= curr_win_min
;
793 best_win_max
= curr_win_max
;
800 if ((best_win_min
== 0) && (best_win_max
== 0))
803 size
= best_win_max
- best_win_min
;
805 debug("RFFD Min: 0x%x\n", best_win_min
);
806 debug("RFFD Max: 0x%x\n", best_win_max
);
807 rffd_average
= ((best_win_min
+ best_win_max
) / 2);
809 cal
->rffd_min
= best_win_min
;
810 cal
->rffd_max
= best_win_max
;
812 if (rffd_average
< 0)
815 if (rffd_average
> SDRAM_RFDC_RFFD_MAX
)
816 rffd_average
= SDRAM_RFDC_RFFD_MAX
;
818 mtsdram(SDRAM_RFDC
, rfdc_reg
| SDRAM_RFDC_RFFD_ENCODE(rffd_average
));
819 #endif /* CONFIG_DDR_RFDC_FIXED */
823 curr_win_min
= curr_win_max
= 0;
824 best_win_min
= best_win_max
= 0;
825 for (rqfd
= 0; rqfd
<= SDRAM_RQDC_RQFD_MAX
; rqfd
++) {
826 mfsdram(SDRAM_RQDC
, rqdc_reg
);
827 rqdc_reg
&= ~(SDRAM_RQDC_RQFD_MASK
);
828 mtsdram(SDRAM_RQDC
, rqdc_reg
| SDRAM_RQDC_RQFD_ENCODE(rqfd
));
831 for (bxcr_num
= 0; bxcr_num
< MAXBXCF
; bxcr_num
++) {
833 mfsdram(SDRAM_MB0CF
+ (bxcr_num
<<2), bxcf
);
836 if (bxcf
& SDRAM_BXCF_M_BE_MASK
) {
837 /* Bank is enabled */
838 membase
= get_membase(bxcr_num
);
839 pass
&= short_mem_test(membase
);
840 } /* if bank enabled */
843 /* If this value passed */
844 if (pass
&& !in_window
) {
846 curr_win_min
= curr_win_max
= rqfd
;
847 } else if (!pass
&& in_window
) {
849 } else if (pass
&& in_window
) {
854 if ((curr_win_max
- curr_win_min
) >
855 (best_win_max
- best_win_min
)) {
856 best_win_min
= curr_win_min
;
857 best_win_max
= curr_win_max
;
863 if ((best_win_min
== 0) && (best_win_max
== 0))
866 debug("RQFD Min: 0x%x\n", best_win_min
);
867 debug("RQFD Max: 0x%x\n", best_win_max
);
868 rqfd_average
= ((best_win_min
+ best_win_max
) / 2);
870 if (rqfd_average
< 0)
873 if (rqfd_average
> SDRAM_RQDC_RQFD_MAX
)
874 rqfd_average
= SDRAM_RQDC_RQFD_MAX
;
876 mtsdram(SDRAM_RQDC
, (rqdc_reg
& ~SDRAM_RQDC_RQFD_MASK
) |
877 SDRAM_RQDC_RQFD_ENCODE(rqfd_average
));
879 mfsdram(SDRAM_RQDC
, rqdc_reg
);
880 mfsdram(SDRAM_RFDC
, rfdc_reg
);
883 * Need to program RQDC before RFDC. The value is read above.
884 * That is the reason why auto cal not work.
885 * See, comments below.
887 mtsdram(SDRAM_RQDC
, rqdc_reg
);
888 mtsdram(SDRAM_RFDC
, rfdc_reg
);
890 debug("RQDC: 0x%08lX\n", rqdc_reg
);
891 debug("RFDC: 0x%08lX\n", rfdc_reg
);
893 /* if something passed, then return the size of the largest window */
896 cal
->rqfd
= rqfd_average
;
897 cal
->rffd
= rffd_average
;
902 #endif /* defined(CONFIG_PPC4xx_DDR_METHOD_A) */
905 * Default table for DDR auto-calibration of all
906 * possible WRDTR and CLKTR values.
908 * {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]}
910 * Table is terminated with {-1, -1} value pair.
912 * Board vendors can specify their own board specific subset of
913 * known working {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} value
914 * pairs via a board defined ddr_scan_option() function.
916 static struct sdram_timing full_scan_options
[] = {
917 {0, 0}, {0, 1}, {0, 2}, {0, 3},
918 {1, 0}, {1, 1}, {1, 2}, {1, 3},
919 {2, 0}, {2, 1}, {2, 2}, {2, 3},
920 {3, 0}, {3, 1}, {3, 2}, {3, 3},
921 {4, 0}, {4, 1}, {4, 2}, {4, 3},
922 {5, 0}, {5, 1}, {5, 2}, {5, 3},
923 {6, 0}, {6, 1}, {6, 2}, {6, 3},
927 /*---------------------------------------------------------------------------+
929 +----------------------------------------------------------------------------*/
930 u32
DQS_autocalibration(void)
937 struct ddrautocal ddrcal
;
938 struct autocal_clks tcal
;
944 char slash
[] = "\\|/-\\|/-";
946 struct sdram_timing
*scan_list
;
948 #if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
950 char tmp
[64]; /* long enough for environment variables */
953 memset(&tcal
, 0, sizeof(tcal
));
955 scan_list
= ddr_scan_option(full_scan_options
);
957 mfsdram(SDRAM_MCOPT1
, val
);
958 if ((val
& SDRAM_MCOPT1_MCHK_CHK_REP
) == SDRAM_MCOPT1_MCHK_CHK_REP
)
959 str
= "ECC Auto calibration -";
961 str
= "Auto calibration -";
965 #if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
966 i
= getenv_f("autocalib", tmp
, sizeof(tmp
));
968 strcpy(tmp
, CONFIG_AUTOCALIB
);
970 if (strcmp(tmp
, "final") == 0) {
971 /* display the final autocalibration results only */
973 } else if (strcmp(tmp
, "loop") == 0) {
974 /* display summary autocalibration info per iteration */
976 } else if (strcmp(tmp
, "display") == 0) {
977 /* display full debug autocalibration window info. */
980 #endif /* (DEBUG_PPC4xx_DDR_AUTOCALIBRATION) */
982 best_rdcc
= (SDRAM_RDCC_RDSS_T4
>> 30);
984 while ((scan_list
->wrdtr
!= -1) && (scan_list
->clktr
!= -1)) {
985 wdtr
= scan_list
->wrdtr
;
986 clkp
= scan_list
->clktr
;
988 mfsdram(SDRAM_WRDTR
, val
);
989 val
&= ~(SDRAM_WRDTR_LLWP_MASK
| SDRAM_WRDTR_WTR_MASK
);
990 mtsdram(SDRAM_WRDTR
, (val
|
991 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC
| (wdtr
<< 25))));
993 mtsdram(SDRAM_CLKTR
, clkp
<< 30);
998 putc(slash
[loopi
++ % 8]);
1002 debug("*** --------------\n");
1003 mfsdram(SDRAM_WRDTR
, val
);
1004 debug("*** SDRAM_WRDTR set to 0x%08x\n", val
);
1005 mfsdram(SDRAM_CLKTR
, val
);
1006 debug("*** SDRAM_CLKTR set to 0x%08x\n", val
);
1010 if (verbose_lvl
> 2) {
1011 printf("*** SDRAM_WRDTR (wdtr) set to %d\n", wdtr
);
1012 printf("*** SDRAM_CLKTR (clkp) set to %d\n", clkp
);
1015 memset(&ddrcal
, 0, sizeof(ddrcal
));
1021 * program_DQS_calibration_method[A|B]() returns 0 if no
1022 * passing RFDC.[RFFD] window is found or returns the size
1023 * of the best passing window; in the case of a found passing
1024 * window, the ddrcal will contain the values of the best
1025 * window RQDC.[RQFD] and RFDC.[RFFD].
1029 * Call PPC4xx SDRAM DDR autocalibration methodA or methodB.
1030 * Default is methodB.
1031 * Defined the autocalibration method in the board specific
1033 * Please see include/configs/kilauea.h for an example for
1034 * a board specific implementation.
1036 #if defined(CONFIG_PPC4xx_DDR_METHOD_A)
1037 result
= program_DQS_calibration_methodA(&ddrcal
);
1039 result
= program_DQS_calibration_methodB(&ddrcal
);
1045 * Clear potential errors resulting from auto-calibration.
1046 * If not done, then we could get an interrupt later on when
1047 * exceptions are enabled.
1049 set_mcsr(get_mcsr());
1051 val
= ddrcal
.rdcc
; /* RDCC from the best passing window */
1055 if (verbose_lvl
> 1) {
1057 switch ((val
>> 30)) {
1077 printf("** WRDTR(%d) CLKTR(%d), Wind (%d), best (%d), "
1078 "max-min(0x%04x)(0x%04x), RDCC: %s\n",
1079 wdtr
, clkp
, result
, best_result
,
1080 ddrcal
.rffd_min
, ddrcal
.rffd_max
, tstr
);
1084 * The DQS calibration "result" is either "0"
1085 * if no passing window was found, or is the
1086 * size of the RFFD passing window.
1089 * want the lowest Read Sample Cycle Select
1091 val
= SDRAM_RDCC_RDSS_DECODE(val
);
1092 debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
1095 if ((result
!= 0) &&
1096 (val
>= SDRAM_RDCC_RDSS_VAL(SDRAM_RDCC_RDSS_T2
))) {
1097 if (((result
== best_result
) && (val
< best_rdcc
)) ||
1098 ((result
> best_result
) && (val
<= best_rdcc
))) {
1099 tcal
.autocal
.flags
= 1;
1100 debug("*** (%d)(%d) result passed window "
1101 "size: 0x%08x, rqfd = 0x%08x, "
1102 "rffd = 0x%08x, rdcc = 0x%08x\n",
1103 wdtr
, clkp
, result
, ddrcal
.rqfd
,
1104 ddrcal
.rffd
, ddrcal
.rdcc
);
1107 * Save the SDRAM_WRDTR and SDRAM_CLKTR
1108 * settings for the largest returned
1109 * RFFD passing window size.
1112 tcal
.clocks
.wrdtr
= wdtr
;
1113 tcal
.clocks
.clktr
= clkp
;
1114 tcal
.clocks
.rdcc
= SDRAM_RDCC_RDSS_ENCODE(val
);
1115 tcal
.autocal
.rqfd
= ddrcal
.rqfd
;
1116 tcal
.autocal
.rffd
= ddrcal
.rffd
;
1117 best_result
= result
;
1119 if (verbose_lvl
> 2) {
1120 printf("** (%d)(%d) "
1121 "best result: 0x%04x\n",
1124 printf("** (%d)(%d) "
1125 "best WRDTR: 0x%04x\n",
1128 printf("** (%d)(%d) "
1129 "best CLKTR: 0x%04x\n",
1132 printf("** (%d)(%d) "
1133 "best RQDC: 0x%04x\n",
1136 printf("** (%d)(%d) "
1137 "best RFDC: 0x%04x\n",
1140 printf("** (%d)(%d) "
1141 "best RDCC: 0x%08x\n",
1143 (u32
)tcal
.clocks
.rdcc
);
1144 mfsdram(SDRAM_RTSR
, val
);
1145 printf("** (%d)(%d) best "
1146 "loop RTSR: 0x%08x\n",
1148 mfsdram(SDRAM_FCSR
, val
);
1149 printf("** (%d)(%d) best "
1150 "loop FCSR: 0x%08x\n",
1154 } /* if ((result != 0) && (val >= (ddr_rdss_opt()))) */
1156 } /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */
1158 if (tcal
.autocal
.flags
== 1) {
1159 if (verbose_lvl
> 0) {
1160 printf("*** --------------\n");
1161 printf("*** best_result window size: %d\n",
1163 printf("*** best_result WRDTR: 0x%04x\n",
1165 printf("*** best_result CLKTR: 0x%04x\n",
1167 printf("*** best_result RQFD: 0x%04x\n",
1169 printf("*** best_result RFFD: 0x%04x\n",
1171 printf("*** best_result RDCC: 0x%04x\n",
1173 printf("*** --------------\n");
1178 * if got best passing result window, then lock in the
1179 * best CLKTR, WRDTR, RQFD, and RFFD values
1181 mfsdram(SDRAM_WRDTR
, val
);
1182 mtsdram(SDRAM_WRDTR
, (val
&
1183 ~(SDRAM_WRDTR_LLWP_MASK
| SDRAM_WRDTR_WTR_MASK
)) |
1184 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC
|
1185 (tcal
.clocks
.wrdtr
<< 25)));
1187 mtsdram(SDRAM_CLKTR
, tcal
.clocks
.clktr
<< 30);
1189 relock_memory_DLL();
1191 mfsdram(SDRAM_RQDC
, rqdc_reg
);
1192 rqdc_reg
&= ~(SDRAM_RQDC_RQFD_MASK
);
1193 mtsdram(SDRAM_RQDC
, rqdc_reg
|
1194 SDRAM_RQDC_RQFD_ENCODE(tcal
.autocal
.rqfd
));
1196 mfsdram(SDRAM_RQDC
, rqdc_reg
);
1197 debug("*** best_result: read value SDRAM_RQDC 0x%08lx\n",
1200 #if defined(CONFIG_DDR_RFDC_FIXED)
1201 mtsdram(SDRAM_RFDC
, CONFIG_DDR_RFDC_FIXED
);
1202 #else /* CONFIG_DDR_RFDC_FIXED */
1203 mfsdram(SDRAM_RFDC
, rfdc_reg
);
1204 rfdc_reg
&= ~(SDRAM_RFDC_RFFD_MASK
);
1205 mtsdram(SDRAM_RFDC
, rfdc_reg
|
1206 SDRAM_RFDC_RFFD_ENCODE(tcal
.autocal
.rffd
));
1207 #endif /* CONFIG_DDR_RFDC_FIXED */
1209 mfsdram(SDRAM_RFDC
, rfdc_reg
);
1210 debug("*** best_result: read value SDRAM_RFDC 0x%08lx\n",
1212 mfsdram(SDRAM_RDCC
, val
);
1213 debug("*** SDRAM_RDCC 0x%08x\n", val
);
1216 * no valid windows were found
1218 printf("DQS memory calibration window can not be determined, "
1219 "terminating u-boot.\n");
1220 ppc4xx_ibm_ddr2_register_dump();
1221 spd_ddr_init_hang();
1224 blank_string(strlen(str
));