]> git.ipfire.org Git - people/ms/u-boot.git/blob - arch/powerpc/cpu/ppc4xx/start.S
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
powerpc: Remove warm reset entry point
[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / start.S
1 /*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27 /*------------------------------------------------------------------------------+
28 * This source code is dual-licensed. You may use it under the terms of the
29 * GNU General Public License version 2, or under the license below.
30 *
31 * This source code has been made available to you by IBM on an AS-IS
32 * basis. Anyone receiving this source is licensed under IBM
33 * copyrights to use it in any way he or she deems fit, including
34 * copying it, modifying it, compiling it, and redistributing it either
35 * with or without modifications. No license under IBM patents or
36 * patent applications is to be implied by the copyright license.
37 *
38 * Any user of this software should understand that IBM cannot provide
39 * technical support for this software and will not be responsible for
40 * any consequences resulting from the use of this software.
41 *
42 * Any person who transfers this source code or any derivative work
43 * must include the IBM copyright notice, this paragraph, and the
44 * preceding two paragraphs in the transferred software.
45 *
46 * COPYRIGHT I B M CORPORATION 1995
47 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
48 *-------------------------------------------------------------------------------
49 */
50
51 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
52 *
53 *
54 * The processor starts at 0xfffffffc and the code is executed
55 * from flash/rom.
56 * in memory, but as long we don't jump around before relocating.
57 * board_init lies at a quite high address and when the cpu has
58 * jumped there, everything is ok.
59 * This works because the cpu gives the FLASH (CS0) the whole
60 * address space at startup, and board_init lies as a echo of
61 * the flash somewhere up there in the memorymap.
62 *
63 * board_init will change CS0 to be positioned at the correct
64 * address and (s)dram will be positioned at address 0
65 */
66 #include <config.h>
67 #include <asm/ppc4xx.h>
68 #include <timestamp.h>
69 #include <version.h>
70
71 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
72
73 #include <ppc_asm.tmpl>
74 #include <ppc_defs.h>
75
76 #include <asm/cache.h>
77 #include <asm/mmu.h>
78 #include <asm/ppc4xx-isram.h>
79
80 #ifndef CONFIG_IDENT_STRING
81 #define CONFIG_IDENT_STRING ""
82 #endif
83
84 #ifdef CONFIG_SYS_INIT_DCACHE_CS
85 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
86 # define PBxAP PB1AP
87 # define PBxCR PB0CR
88 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
89 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
90 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
91 # endif
92 # endif
93 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
94 # define PBxAP PB1AP
95 # define PBxCR PB1CR
96 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
97 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
98 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
99 # endif
100 # endif
101 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
102 # define PBxAP PB2AP
103 # define PBxCR PB2CR
104 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
105 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
106 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
107 # endif
108 # endif
109 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
110 # define PBxAP PB3AP
111 # define PBxCR PB3CR
112 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
113 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
114 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
115 # endif
116 # endif
117 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
118 # define PBxAP PB4AP
119 # define PBxCR PB4CR
120 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
121 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
122 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
123 # endif
124 # endif
125 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
126 # define PBxAP PB5AP
127 # define PBxCR PB5CR
128 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
129 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
130 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
131 # endif
132 # endif
133 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
134 # define PBxAP PB6AP
135 # define PBxCR PB6CR
136 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
137 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
138 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
139 # endif
140 # endif
141 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
142 # define PBxAP PB7AP
143 # define PBxCR PB7CR
144 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
145 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
146 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
147 # endif
148 # endif
149 # ifndef PBxAP_VAL
150 # define PBxAP_VAL 0
151 # endif
152 # ifndef PBxCR_VAL
153 # define PBxCR_VAL 0
154 # endif
155 /*
156 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
157 * used as temporary stack pointer for the primordial stack
158 */
159 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
160 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
161 EBC_BXAP_TWT_ENCODE(7) | \
162 EBC_BXAP_BCE_DISABLE | \
163 EBC_BXAP_BCT_2TRANS | \
164 EBC_BXAP_CSN_ENCODE(0) | \
165 EBC_BXAP_OEN_ENCODE(0) | \
166 EBC_BXAP_WBN_ENCODE(0) | \
167 EBC_BXAP_WBF_ENCODE(0) | \
168 EBC_BXAP_TH_ENCODE(2) | \
169 EBC_BXAP_RE_DISABLED | \
170 EBC_BXAP_SOR_NONDELAYED | \
171 EBC_BXAP_BEM_WRITEONLY | \
172 EBC_BXAP_PEN_DISABLED)
173 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
174 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
175 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
176 EBC_BXCR_BS_64MB | \
177 EBC_BXCR_BU_RW | \
178 EBC_BXCR_BW_16BIT)
179 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
180 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
181 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
182 # endif
183 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
184
185 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
186 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
187 #endif
188
189 /*
190 * Unless otherwise overriden, enable two 128MB cachable instruction regions
191 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
192 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
193 */
194 #if !defined(CONFIG_SYS_FLASH_BASE)
195 /* If not already defined, set it to the "last" 128MByte region */
196 # define CONFIG_SYS_FLASH_BASE 0xf8000000
197 #endif
198 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
199 # define CONFIG_SYS_ICACHE_SACR_VALUE \
200 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
201 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
202 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
203 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
204
205 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
206 # define CONFIG_SYS_DCACHE_SACR_VALUE \
207 (0x00000000)
208 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
209
210 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
211 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
212 #endif
213
214 #define function_prolog(func_name) .text; \
215 .align 2; \
216 .globl func_name; \
217 func_name:
218 #define function_epilog(func_name) .type func_name,@function; \
219 .size func_name,.-func_name
220
221 /* We don't want the MMU yet.
222 */
223 #undef MSR_KERNEL
224 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
225
226
227 .extern ext_bus_cntlr_init
228 #ifdef CONFIG_NAND_U_BOOT
229 .extern reconfig_tlb0
230 #endif
231
232 /*
233 * Set up GOT: Global Offset Table
234 *
235 * Use r12 to access the GOT
236 */
237 #if !defined(CONFIG_NAND_SPL)
238 START_GOT
239 GOT_ENTRY(_GOT2_TABLE_)
240 GOT_ENTRY(_FIXUP_TABLE_)
241
242 GOT_ENTRY(_start)
243 GOT_ENTRY(_start_of_vectors)
244 GOT_ENTRY(_end_of_vectors)
245 GOT_ENTRY(transfer_to_handler)
246
247 GOT_ENTRY(__init_end)
248 GOT_ENTRY(_end)
249 GOT_ENTRY(__bss_start)
250 END_GOT
251 #endif /* CONFIG_NAND_SPL */
252
253 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
254 /*
255 * NAND U-Boot image is started from offset 0
256 */
257 .text
258 #if defined(CONFIG_440)
259 bl reconfig_tlb0
260 #endif
261 GET_GOT
262 bl cpu_init_f /* run low-level CPU init code (from Flash) */
263 bl board_init_f
264 /* NOTREACHED - board_init_f() does not return */
265 #endif
266
267 #if defined(CONFIG_SYS_RAMBOOT)
268 /*
269 * 4xx RAM-booting U-Boot image is started from offset 0
270 */
271 .text
272 bl _start_440
273 #endif
274
275 /*
276 * 440 Startup -- on reset only the top 4k of the effective
277 * address space is mapped in by an entry in the instruction
278 * and data shadow TLB. The .bootpg section is located in the
279 * top 4k & does only what's necessary to map in the the rest
280 * of the boot rom. Once the boot rom is mapped in we can
281 * proceed with normal startup.
282 *
283 * NOTE: CS0 only covers the top 2MB of the effective address
284 * space after reset.
285 */
286
287 #if defined(CONFIG_440)
288 #if !defined(CONFIG_NAND_SPL)
289 .section .bootpg,"ax"
290 #endif
291 .globl _start_440
292
293 /**************************************************************************/
294 _start_440:
295 /*--------------------------------------------------------------------+
296 | 440EPX BUP Change - Hardware team request
297 +--------------------------------------------------------------------*/
298 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
299 sync
300 nop
301 nop
302 #endif
303 /*----------------------------------------------------------------+
304 | Core bug fix. Clear the esr
305 +-----------------------------------------------------------------*/
306 li r0,0
307 mtspr SPRN_ESR,r0
308 /*----------------------------------------------------------------*/
309 /* Clear and set up some registers. */
310 /*----------------------------------------------------------------*/
311 iccci r0,r0 /* NOTE: operands not used for 440 */
312 dccci r0,r0 /* NOTE: operands not used for 440 */
313 sync
314 li r0,0
315 mtspr SPRN_SRR0,r0
316 mtspr SPRN_SRR1,r0
317 mtspr SPRN_CSRR0,r0
318 mtspr SPRN_CSRR1,r0
319 /* NOTE: 440GX adds machine check status regs */
320 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
321 mtspr SPRN_MCSRR0,r0
322 mtspr SPRN_MCSRR1,r0
323 mfspr r1,SPRN_MCSR
324 mtspr SPRN_MCSR,r1
325 #endif
326
327 /*----------------------------------------------------------------*/
328 /* CCR0 init */
329 /*----------------------------------------------------------------*/
330 /* Disable store gathering & broadcast, guarantee inst/data
331 * cache block touch, force load/store alignment
332 * (see errata 1.12: 440_33)
333 */
334 lis r1,0x0030 /* store gathering & broadcast disable */
335 ori r1,r1,0x6000 /* cache touch */
336 mtspr SPRN_CCR0,r1
337
338 /*----------------------------------------------------------------*/
339 /* Initialize debug */
340 /*----------------------------------------------------------------*/
341 mfspr r1,SPRN_DBCR0
342 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
343 bne skip_debug_init /* if set, don't clear debug register */
344 mfspr r1,SPRN_CCR0
345 ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
346 mtspr SPRN_CCR0,r1
347 mtspr SPRN_DBCR0,r0
348 mtspr SPRN_DBCR1,r0
349 mtspr SPRN_DBCR2,r0
350 mtspr SPRN_IAC1,r0
351 mtspr SPRN_IAC2,r0
352 mtspr SPRN_IAC3,r0
353 mtspr SPRN_DAC1,r0
354 mtspr SPRN_DAC2,r0
355 mtspr SPRN_DVC1,r0
356 mtspr SPRN_DVC2,r0
357
358 mfspr r1,SPRN_DBSR
359 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
360 skip_debug_init:
361
362 #if defined (CONFIG_440SPE)
363 /*----------------------------------------------------------------+
364 | Initialize Core Configuration Reg1.
365 | a. ICDPEI: Record even parity. Normal operation.
366 | b. ICTPEI: Record even parity. Normal operation.
367 | c. DCTPEI: Record even parity. Normal operation.
368 | d. DCDPEI: Record even parity. Normal operation.
369 | e. DCUPEI: Record even parity. Normal operation.
370 | f. DCMPEI: Record even parity. Normal operation.
371 | g. FCOM: Normal operation
372 | h. MMUPEI: Record even parity. Normal operation.
373 | i. FFF: Flush only as much data as necessary.
374 | j. TCS: Timebase increments from CPU clock.
375 +-----------------------------------------------------------------*/
376 li r0,0
377 mtspr SPRN_CCR1, r0
378
379 /*----------------------------------------------------------------+
380 | Reset the timebase.
381 | The previous write to CCR1 sets the timebase source.
382 +-----------------------------------------------------------------*/
383 mtspr SPRN_TBWL, r0
384 mtspr SPRN_TBWU, r0
385 #endif
386
387 /*----------------------------------------------------------------*/
388 /* Setup interrupt vectors */
389 /*----------------------------------------------------------------*/
390 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
391 li r1,0x0100
392 mtspr SPRN_IVOR0,r1 /* Critical input */
393 li r1,0x0200
394 mtspr SPRN_IVOR1,r1 /* Machine check */
395 li r1,0x0300
396 mtspr SPRN_IVOR2,r1 /* Data storage */
397 li r1,0x0400
398 mtspr SPRN_IVOR3,r1 /* Instruction storage */
399 li r1,0x0500
400 mtspr SPRN_IVOR4,r1 /* External interrupt */
401 li r1,0x0600
402 mtspr SPRN_IVOR5,r1 /* Alignment */
403 li r1,0x0700
404 mtspr SPRN_IVOR6,r1 /* Program check */
405 li r1,0x0800
406 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
407 li r1,0x0c00
408 mtspr SPRN_IVOR8,r1 /* System call */
409 li r1,0x0a00
410 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
411 li r1,0x0900
412 mtspr SPRN_IVOR10,r1 /* Decrementer */
413 li r1,0x1300
414 mtspr SPRN_IVOR13,r1 /* Data TLB error */
415 li r1,0x1400
416 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
417 li r1,0x2000
418 mtspr SPRN_IVOR15,r1 /* Debug */
419
420 /*----------------------------------------------------------------*/
421 /* Configure cache regions */
422 /*----------------------------------------------------------------*/
423 mtspr SPRN_INV0,r0
424 mtspr SPRN_INV1,r0
425 mtspr SPRN_INV2,r0
426 mtspr SPRN_INV3,r0
427 mtspr SPRN_DNV0,r0
428 mtspr SPRN_DNV1,r0
429 mtspr SPRN_DNV2,r0
430 mtspr SPRN_DNV3,r0
431 mtspr SPRN_ITV0,r0
432 mtspr SPRN_ITV1,r0
433 mtspr SPRN_ITV2,r0
434 mtspr SPRN_ITV3,r0
435 mtspr SPRN_DTV0,r0
436 mtspr SPRN_DTV1,r0
437 mtspr SPRN_DTV2,r0
438 mtspr SPRN_DTV3,r0
439
440 /*----------------------------------------------------------------*/
441 /* Cache victim limits */
442 /*----------------------------------------------------------------*/
443 /* floors 0, ceiling max to use the entire cache -- nothing locked
444 */
445 lis r1,0x0001
446 ori r1,r1,0xf800
447 mtspr SPRN_IVLIM,r1
448 mtspr SPRN_DVLIM,r1
449
450 /*----------------------------------------------------------------+
451 |Initialize MMUCR[STID] = 0.
452 +-----------------------------------------------------------------*/
453 mfspr r0,SPRN_MMUCR
454 addis r1,0,0xFFFF
455 ori r1,r1,0xFF00
456 and r0,r0,r1
457 mtspr SPRN_MMUCR,r0
458
459 /*----------------------------------------------------------------*/
460 /* Clear all TLB entries -- TID = 0, TS = 0 */
461 /*----------------------------------------------------------------*/
462 addis r0,0,0x0000
463 #ifdef CONFIG_SYS_RAMBOOT
464 li r4,0 /* Start with TLB #0 */
465 #else
466 li r4,1 /* Start with TLB #1 */
467 #endif
468 li r1,64 /* 64 TLB entries */
469 sub r1,r1,r4 /* calculate last TLB # */
470 mtctr r1
471 rsttlb:
472 #ifdef CONFIG_SYS_RAMBOOT
473 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
474 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
475 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
476 #endif
477 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
478 tlbwe r0,r4,1
479 tlbwe r0,r4,2
480 tlbnxt: addi r4,r4,1 /* Next TLB */
481 bdnz rsttlb
482
483 /*----------------------------------------------------------------*/
484 /* TLB entry setup -- step thru tlbtab */
485 /*----------------------------------------------------------------*/
486 #if defined(CONFIG_440SPE_REVA)
487 /*----------------------------------------------------------------*/
488 /* We have different TLB tables for revA and rev B of 440SPe */
489 /*----------------------------------------------------------------*/
490 mfspr r1, PVR
491 lis r0,0x5342
492 ori r0,r0,0x1891
493 cmpw r7,r1,r0
494 bne r7,..revA
495 bl tlbtabB
496 b ..goon
497 ..revA:
498 bl tlbtabA
499 ..goon:
500 #else
501 bl tlbtab /* Get tlbtab pointer */
502 #endif
503 mr r5,r0
504 li r1,0x003f /* 64 TLB entries max */
505 mtctr r1
506 li r4,0 /* TLB # */
507
508 addi r5,r5,-4
509 1:
510 #ifdef CONFIG_SYS_RAMBOOT
511 tlbre r3,r4,0 /* Read contents from TLB word #0 */
512 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
513 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
514 #endif
515 lwzu r0,4(r5)
516 cmpwi r0,0
517 beq 2f /* 0 marks end */
518 lwzu r1,4(r5)
519 lwzu r2,4(r5)
520 tlbwe r0,r4,0 /* TLB Word 0 */
521 tlbwe r1,r4,1 /* TLB Word 1 */
522 tlbwe r2,r4,2 /* TLB Word 2 */
523 tlbnx2: addi r4,r4,1 /* Next TLB */
524 bdnz 1b
525
526 /*----------------------------------------------------------------*/
527 /* Continue from 'normal' start */
528 /*----------------------------------------------------------------*/
529 2:
530 bl 3f
531 b _start
532
533 3: li r0,0
534 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
535 mflr r1
536 mtspr SPRN_SRR0,r1
537 rfi
538 #endif /* CONFIG_440 */
539
540 /*
541 * r3 - 1st arg to board_init(): IMMP pointer
542 * r4 - 2nd arg to board_init(): boot flag
543 */
544 #ifndef CONFIG_NAND_SPL
545 .text
546 .long 0x27051956 /* U-Boot Magic Number */
547 .globl version_string
548 version_string:
549 .ascii U_BOOT_VERSION
550 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
551 .ascii CONFIG_IDENT_STRING, "\0"
552
553 . = EXC_OFF_SYS_RESET
554 .globl _start_of_vectors
555 _start_of_vectors:
556
557 /* Critical input. */
558 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
559
560 #ifdef CONFIG_440
561 /* Machine check */
562 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
563 #else
564 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
565 #endif /* CONFIG_440 */
566
567 /* Data Storage exception. */
568 STD_EXCEPTION(0x300, DataStorage, UnknownException)
569
570 /* Instruction Storage exception. */
571 STD_EXCEPTION(0x400, InstStorage, UnknownException)
572
573 /* External Interrupt exception. */
574 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
575
576 /* Alignment exception. */
577 . = 0x600
578 Alignment:
579 EXCEPTION_PROLOG(SRR0, SRR1)
580 mfspr r4,DAR
581 stw r4,_DAR(r21)
582 mfspr r5,DSISR
583 stw r5,_DSISR(r21)
584 addi r3,r1,STACK_FRAME_OVERHEAD
585 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
586
587 /* Program check exception */
588 . = 0x700
589 ProgramCheck:
590 EXCEPTION_PROLOG(SRR0, SRR1)
591 addi r3,r1,STACK_FRAME_OVERHEAD
592 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
593 MSR_KERNEL, COPY_EE)
594
595 #ifdef CONFIG_440
596 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
597 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
598 STD_EXCEPTION(0xa00, APU, UnknownException)
599 #endif
600 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
601
602 #ifdef CONFIG_440
603 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
604 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
605 #else
606 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
607 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
608 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
609 #endif
610 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
611
612 .globl _end_of_vectors
613 _end_of_vectors:
614 . = _START_OFFSET
615 #endif
616 .globl _start
617 _start:
618
619 /*****************************************************************************/
620 #if defined(CONFIG_440)
621
622 /*----------------------------------------------------------------*/
623 /* Clear and set up some registers. */
624 /*----------------------------------------------------------------*/
625 li r0,0x0000
626 lis r1,0xffff
627 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
628 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
629 mtspr SPRN_TBWU,r0
630 mtspr SPRN_TSR,r1 /* clear all timer exception status */
631 mtspr SPRN_TCR,r0 /* disable all */
632 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
633 mtxer r0 /* clear integer exception register */
634
635 /*----------------------------------------------------------------*/
636 /* Debug setup -- some (not very good) ice's need an event*/
637 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
638 /* value you need in this case 0x8cff 0000 should do the trick */
639 /*----------------------------------------------------------------*/
640 #if defined(CONFIG_SYS_INIT_DBCR)
641 lis r1,0xffff
642 ori r1,r1,0xffff
643 mtspr SPRN_DBSR,r1 /* Clear all status bits */
644 lis r0,CONFIG_SYS_INIT_DBCR@h
645 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
646 mtspr SPRN_DBCR0,r0
647 isync
648 #endif
649
650 /*----------------------------------------------------------------*/
651 /* Setup the internal SRAM */
652 /*----------------------------------------------------------------*/
653 li r0,0
654
655 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
656 /* Clear Dcache to use as RAM */
657 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
658 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
659 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
660 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
661 rlwinm. r5,r4,0,27,31
662 rlwinm r5,r4,27,5,31
663 beq ..d_ran
664 addi r5,r5,0x0001
665 ..d_ran:
666 mtctr r5
667 ..d_ag:
668 dcbz r0,r3
669 addi r3,r3,32
670 bdnz ..d_ag
671
672 /*
673 * Lock the init-ram/stack in d-cache, so that other regions
674 * may use d-cache as well
675 * Note, that this current implementation locks exactly 4k
676 * of d-cache, so please make sure that you don't define a
677 * bigger init-ram area. Take a look at the lwmon5 440EPx
678 * implementation as a reference.
679 */
680 msync
681 isync
682 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
683 lis r1,0x0201
684 ori r1,r1,0xf808
685 mtspr SPRN_DVLIM,r1
686 lis r1,0x0808
687 ori r1,r1,0x0808
688 mtspr SPRN_DNV0,r1
689 mtspr SPRN_DNV1,r1
690 mtspr SPRN_DNV2,r1
691 mtspr SPRN_DNV3,r1
692 mtspr SPRN_DTV0,r1
693 mtspr SPRN_DTV1,r1
694 mtspr SPRN_DTV2,r1
695 mtspr SPRN_DTV3,r1
696 msync
697 isync
698 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
699
700 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
701 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
702 /* not all PPC's have internal SRAM usable as L2-cache */
703 #if defined(CONFIG_440GX) || \
704 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
705 defined(CONFIG_460SX)
706 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
707 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
708 defined(CONFIG_APM821XX)
709 lis r1, 0x0000
710 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
711 mtdcr L2_CACHE_CFG,r1
712 #endif
713
714 lis r2,0x7fff
715 ori r2,r2,0xffff
716 mfdcr r1,ISRAM0_DPC
717 and r1,r1,r2 /* Disable parity check */
718 mtdcr ISRAM0_DPC,r1
719 mfdcr r1,ISRAM0_PMEG
720 and r1,r1,r2 /* Disable pwr mgmt */
721 mtdcr ISRAM0_PMEG,r1
722
723 lis r1,0x8000 /* BAS = 8000_0000 */
724 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
725 ori r1,r1,0x0980 /* first 64k */
726 mtdcr ISRAM0_SB0CR,r1
727 lis r1,0x8001
728 ori r1,r1,0x0980 /* second 64k */
729 mtdcr ISRAM0_SB1CR,r1
730 lis r1, 0x8002
731 ori r1,r1, 0x0980 /* third 64k */
732 mtdcr ISRAM0_SB2CR,r1
733 lis r1, 0x8003
734 ori r1,r1, 0x0980 /* fourth 64k */
735 mtdcr ISRAM0_SB3CR,r1
736 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
737 defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
738 lis r1,0x0000 /* BAS = X_0000_0000 */
739 ori r1,r1,0x0984 /* first 64k */
740 mtdcr ISRAM0_SB0CR,r1
741 lis r1,0x0001
742 ori r1,r1,0x0984 /* second 64k */
743 mtdcr ISRAM0_SB1CR,r1
744 lis r1, 0x0002
745 ori r1,r1, 0x0984 /* third 64k */
746 mtdcr ISRAM0_SB2CR,r1
747 lis r1, 0x0003
748 ori r1,r1, 0x0984 /* fourth 64k */
749 mtdcr ISRAM0_SB3CR,r1
750 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
751 defined(CONFIG_APM821XX)
752 lis r2,0x7fff
753 ori r2,r2,0xffff
754 mfdcr r1,ISRAM1_DPC
755 and r1,r1,r2 /* Disable parity check */
756 mtdcr ISRAM1_DPC,r1
757 mfdcr r1,ISRAM1_PMEG
758 and r1,r1,r2 /* Disable pwr mgmt */
759 mtdcr ISRAM1_PMEG,r1
760
761 lis r1,0x0004 /* BAS = 4_0004_0000 */
762 ori r1,r1,ISRAM1_SIZE /* ocm size */
763 mtdcr ISRAM1_SB0CR,r1
764 #endif
765 #elif defined(CONFIG_460SX)
766 lis r1,0x0000 /* BAS = 0000_0000 */
767 ori r1,r1,0x0B84 /* first 128k */
768 mtdcr ISRAM0_SB0CR,r1
769 lis r1,0x0001
770 ori r1,r1,0x0B84 /* second 128k */
771 mtdcr ISRAM0_SB1CR,r1
772 lis r1, 0x0002
773 ori r1,r1, 0x0B84 /* third 128k */
774 mtdcr ISRAM0_SB2CR,r1
775 lis r1, 0x0003
776 ori r1,r1, 0x0B84 /* fourth 128k */
777 mtdcr ISRAM0_SB3CR,r1
778 #elif defined(CONFIG_440GP)
779 ori r1,r1,0x0380 /* 8k rw */
780 mtdcr ISRAM0_SB0CR,r1
781 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
782 #endif
783 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
784
785 /*----------------------------------------------------------------*/
786 /* Setup the stack in internal SRAM */
787 /*----------------------------------------------------------------*/
788 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
789 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
790 li r0,0
791 stwu r0,-4(r1)
792 stwu r0,-4(r1) /* Terminate call chain */
793
794 stwu r1,-8(r1) /* Save back chain and move SP */
795 lis r0,RESET_VECTOR@h /* Address of reset vector */
796 ori r0,r0, RESET_VECTOR@l
797 stwu r1,-8(r1) /* Save back chain and move SP */
798 stw r0,+12(r1) /* Save return addr (underflow vect) */
799
800 #ifdef CONFIG_NAND_SPL
801 bl nand_boot_common /* will not return */
802 #else
803 GET_GOT
804
805 bl cpu_init_f /* run low-level CPU init code (from Flash) */
806 bl board_init_f
807 /* NOTREACHED - board_init_f() does not return */
808 #endif
809
810 #endif /* CONFIG_440 */
811
812 /*****************************************************************************/
813 #ifdef CONFIG_IOP480
814 /*----------------------------------------------------------------------- */
815 /* Set up some machine state registers. */
816 /*----------------------------------------------------------------------- */
817 addi r0,r0,0x0000 /* initialize r0 to zero */
818 mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
819 mttcr r0 /* timer control register */
820 mtexier r0 /* disable all interrupts */
821 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
822 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
823 mtdbsr r4 /* clear/reset the dbsr */
824 mtexisr r4 /* clear all pending interrupts */
825 addis r4,r0,0x8000
826 mtexier r4 /* enable critical exceptions */
827 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
828 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
829 mtiocr r4 /* since bit not used) & DRC to latch */
830 /* data bus on rising edge of CAS */
831 /*----------------------------------------------------------------------- */
832 /* Clear XER. */
833 /*----------------------------------------------------------------------- */
834 mtxer r0
835 /*----------------------------------------------------------------------- */
836 /* Invalidate i-cache and d-cache TAG arrays. */
837 /*----------------------------------------------------------------------- */
838 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
839 addi r4,0,1024 /* 1/4 of I-cache */
840 ..cloop:
841 iccci 0,r3
842 iccci r4,r3
843 dccci 0,r3
844 addic. r3,r3,-16 /* move back one cache line */
845 bne ..cloop /* loop back to do rest until r3 = 0 */
846
847 /* */
848 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
849 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
850 /* */
851
852 /* first copy IOP480 register base address into r3 */
853 addis r3,0,0x5000 /* IOP480 register base address hi */
854 /* ori r3,r3,0x0000 / IOP480 register base address lo */
855
856 #ifdef CONFIG_ADCIOP
857 /* use r4 as the working variable */
858 /* turn on CS3 (LOCCTL.7) */
859 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
860 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
861 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
862 #endif
863
864 #ifdef CONFIG_DASA_SIM
865 /* use r4 as the working variable */
866 /* turn on MA17 (LOCCTL.7) */
867 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
868 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
869 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
870 #endif
871
872 /* turn on MA16..13 (LCS0BRD.12 = 0) */
873 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
874 andi. r4,r4,0xefff /* make bit 12 = 0 */
875 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
876
877 /* make sure above stores all comlete before going on */
878 sync
879
880 /* last thing, set local init status done bit (DEVINIT.31) */
881 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
882 oris r4,r4,0x8000 /* make bit 31 = 1 */
883 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
884
885 /* clear all pending interrupts and disable all interrupts */
886 li r4,-1 /* set p1 to 0xffffffff */
887 stw r4,0x1b0(r3) /* clear all pending interrupts */
888 stw r4,0x1b8(r3) /* clear all pending interrupts */
889 li r4,0 /* set r4 to 0 */
890 stw r4,0x1b4(r3) /* disable all interrupts */
891 stw r4,0x1bc(r3) /* disable all interrupts */
892
893 /* make sure above stores all comlete before going on */
894 sync
895
896 /* Set-up icache cacheability. */
897 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
898 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
899 mticcr r1
900 isync
901
902 /* Set-up dcache cacheability. */
903 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
904 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
905 mtdccr r1
906
907 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
908 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
909 li r0, 0 /* Make room for stack frame header and */
910 stwu r0, -4(r1) /* clear final stack frame so that */
911 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
912
913 GET_GOT /* initialize GOT access */
914
915 bl board_init_f /* run first part of init code (from Flash) */
916 /* NOTREACHED - board_init_f() does not return */
917
918 #endif /* CONFIG_IOP480 */
919
920 /*****************************************************************************/
921 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
922 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
923 defined(CONFIG_405EX) || defined(CONFIG_405)
924 /*----------------------------------------------------------------------- */
925 /* Clear and set up some registers. */
926 /*----------------------------------------------------------------------- */
927 addi r4,r0,0x0000
928 #if !defined(CONFIG_405EX)
929 mtspr SPRN_SGR,r4
930 #else
931 /*
932 * On 405EX, completely clearing the SGR leads to PPC hangup
933 * upon PCIe configuration access. The PCIe memory regions
934 * need to be guarded!
935 */
936 lis r3,0x0000
937 ori r3,r3,0x7FFC
938 mtspr SPRN_SGR,r3
939 #endif
940 mtspr SPRN_DCWR,r4
941 mtesr r4 /* clear Exception Syndrome Reg */
942 mttcr r4 /* clear Timer Control Reg */
943 mtxer r4 /* clear Fixed-Point Exception Reg */
944 mtevpr r4 /* clear Exception Vector Prefix Reg */
945 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
946 /* dbsr is cleared by setting bits to 1) */
947 mtdbsr r4 /* clear/reset the dbsr */
948
949 /* Invalidate the i- and d-caches. */
950 bl invalidate_icache
951 bl invalidate_dcache
952
953 /* Set-up icache cacheability. */
954 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
955 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
956 mticcr r4
957 isync
958
959 /* Set-up dcache cacheability. */
960 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
961 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
962 mtdccr r4
963
964 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
965 && !defined (CONFIG_XILINX_405)
966 /*----------------------------------------------------------------------- */
967 /* Tune the speed and size for flash CS0 */
968 /*----------------------------------------------------------------------- */
969 bl ext_bus_cntlr_init
970 #endif
971
972 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
973 /*
974 * For boards that don't have OCM and can't use the data cache
975 * for their primordial stack, setup stack here directly after the
976 * SDRAM is initialized in ext_bus_cntlr_init.
977 */
978 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
979 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
980
981 li r0, 0 /* Make room for stack frame header and */
982 stwu r0, -4(r1) /* clear final stack frame so that */
983 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
984 /*
985 * Set up a dummy frame to store reset vector as return address.
986 * this causes stack underflow to reset board.
987 */
988 stwu r1, -8(r1) /* Save back chain and move SP */
989 lis r0, RESET_VECTOR@h /* Address of reset vector */
990 ori r0, r0, RESET_VECTOR@l
991 stwu r1, -8(r1) /* Save back chain and move SP */
992 stw r0, +12(r1) /* Save return addr (underflow vect) */
993 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
994
995 #if defined(CONFIG_405EP)
996 /*----------------------------------------------------------------------- */
997 /* DMA Status, clear to come up clean */
998 /*----------------------------------------------------------------------- */
999 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
1000 ori r3,r3, 0xFFFF
1001 mtdcr DMASR, r3
1002
1003 bl ppc405ep_init /* do ppc405ep specific init */
1004 #endif /* CONFIG_405EP */
1005
1006 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
1007 #if defined(CONFIG_405EZ)
1008 /********************************************************************
1009 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
1010 *******************************************************************/
1011 /*
1012 * We can map the OCM on the PLB3, so map it at
1013 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
1014 */
1015 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1016 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1017 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1018 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
1019 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1020 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
1021 isync
1022
1023 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1024 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1025 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1026 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
1027 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
1028 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1029 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
1030 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
1031 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
1032 mtdcr OCM0_DISDPC,r3
1033
1034 isync
1035 #else /* CONFIG_405EZ */
1036 /********************************************************************
1037 * Setup OCM - On Chip Memory
1038 *******************************************************************/
1039 /* Setup OCM */
1040 lis r0, 0x7FFF
1041 ori r0, r0, 0xFFFF
1042 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
1043 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
1044 and r3, r3, r0 /* disable data-side IRAM */
1045 and r4, r4, r0 /* disable data-side IRAM */
1046 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
1047 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
1048 isync
1049
1050 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1051 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1052 mtdcr OCM0_DSARC, r3
1053 addis r4, 0, 0xC000 /* OCM data area enabled */
1054 mtdcr OCM0_DSCNTL, r4
1055 isync
1056 #endif /* CONFIG_405EZ */
1057 #endif
1058
1059 /*----------------------------------------------------------------------- */
1060 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1061 /*----------------------------------------------------------------------- */
1062 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1063 li r4, PBxAP
1064 mtdcr EBC0_CFGADDR, r4
1065 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1066 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1067 mtdcr EBC0_CFGDATA, r4
1068
1069 addi r4, 0, PBxCR
1070 mtdcr EBC0_CFGADDR, r4
1071 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1072 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1073 mtdcr EBC0_CFGDATA, r4
1074
1075 /*
1076 * Enable the data cache for the 128MB storage access control region
1077 * at CONFIG_SYS_INIT_RAM_ADDR.
1078 */
1079 mfdccr r4
1080 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1081 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1082 mtdccr r4
1083
1084 /*
1085 * Preallocate data cache lines to be used to avoid a subsequent
1086 * cache miss and an ensuing machine check exception when exceptions
1087 * are enabled.
1088 */
1089 li r0, 0
1090
1091 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1092 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1093
1094 lis r4, CONFIG_SYS_INIT_RAM_END@h
1095 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1096
1097 /*
1098 * Convert the size, in bytes, to the number of cache lines/blocks
1099 * to preallocate.
1100 */
1101 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1102 srwi r5, r4, L1_CACHE_SHIFT
1103 beq ..load_counter
1104 addi r5, r5, 0x0001
1105 ..load_counter:
1106 mtctr r5
1107
1108 /* Preallocate the computed number of cache blocks. */
1109 ..alloc_dcache_block:
1110 dcba r0, r3
1111 addi r3, r3, L1_CACHE_BYTES
1112 bdnz ..alloc_dcache_block
1113 sync
1114
1115 /*
1116 * Load the initial stack pointer and data area and convert the size,
1117 * in bytes, to the number of words to initialize to a known value.
1118 */
1119 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1120 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1121
1122 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
1123 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
1124 mtctr r4
1125
1126 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1127 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
1128
1129 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1130 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1131
1132 ..stackloop:
1133 stwu r4, -4(r2)
1134 bdnz ..stackloop
1135
1136 /*
1137 * Make room for stack frame header and clear final stack frame so
1138 * that stack backtraces terminate cleanly.
1139 */
1140 stwu r0, -4(r1)
1141 stwu r0, -4(r1)
1142
1143 /*
1144 * Set up a dummy frame to store reset vector as return address.
1145 * this causes stack underflow to reset board.
1146 */
1147 stwu r1, -8(r1) /* Save back chain and move SP */
1148 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1149 ori r0, r0, RESET_VECTOR@l
1150 stwu r1, -8(r1) /* Save back chain and move SP */
1151 stw r0, +12(r1) /* Save return addr (underflow vect) */
1152
1153 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1154 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1155 /*
1156 * Stack in OCM.
1157 */
1158
1159 /* Set up Stack at top of OCM */
1160 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1161 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1162
1163 /* Set up a zeroized stack frame so that backtrace works right */
1164 li r0, 0
1165 stwu r0, -4(r1)
1166 stwu r0, -4(r1)
1167
1168 /*
1169 * Set up a dummy frame to store reset vector as return address.
1170 * this causes stack underflow to reset board.
1171 */
1172 stwu r1, -8(r1) /* Save back chain and move SP */
1173 lis r0, RESET_VECTOR@h /* Address of reset vector */
1174 ori r0, r0, RESET_VECTOR@l
1175 stwu r1, -8(r1) /* Save back chain and move SP */
1176 stw r0, +12(r1) /* Save return addr (underflow vect) */
1177 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1178
1179 #ifdef CONFIG_NAND_SPL
1180 bl nand_boot_common /* will not return */
1181 #else
1182 GET_GOT /* initialize GOT access */
1183
1184 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1185
1186 bl board_init_f /* run first part of init code (from Flash) */
1187 /* NOTREACHED - board_init_f() does not return */
1188
1189 #endif /* CONFIG_NAND_SPL */
1190
1191 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1192 /*----------------------------------------------------------------------- */
1193
1194
1195 #ifndef CONFIG_NAND_SPL
1196 /*
1197 * This code finishes saving the registers to the exception frame
1198 * and jumps to the appropriate handler for the exception.
1199 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1200 */
1201 .globl transfer_to_handler
1202 transfer_to_handler:
1203 stw r22,_NIP(r21)
1204 lis r22,MSR_POW@h
1205 andc r23,r23,r22
1206 stw r23,_MSR(r21)
1207 SAVE_GPR(7, r21)
1208 SAVE_4GPRS(8, r21)
1209 SAVE_8GPRS(12, r21)
1210 SAVE_8GPRS(24, r21)
1211 mflr r23
1212 andi. r24,r23,0x3f00 /* get vector offset */
1213 stw r24,TRAP(r21)
1214 li r22,0
1215 stw r22,RESULT(r21)
1216 mtspr SPRG2,r22 /* r1 is now kernel sp */
1217 lwz r24,0(r23) /* virtual address of handler */
1218 lwz r23,4(r23) /* where to go when done */
1219 mtspr SRR0,r24
1220 mtspr SRR1,r20
1221 mtlr r23
1222 SYNC
1223 rfi /* jump to handler, enable MMU */
1224
1225 int_return:
1226 mfmsr r28 /* Disable interrupts */
1227 li r4,0
1228 ori r4,r4,MSR_EE
1229 andc r28,r28,r4
1230 SYNC /* Some chip revs need this... */
1231 mtmsr r28
1232 SYNC
1233 lwz r2,_CTR(r1)
1234 lwz r0,_LINK(r1)
1235 mtctr r2
1236 mtlr r0
1237 lwz r2,_XER(r1)
1238 lwz r0,_CCR(r1)
1239 mtspr XER,r2
1240 mtcrf 0xFF,r0
1241 REST_10GPRS(3, r1)
1242 REST_10GPRS(13, r1)
1243 REST_8GPRS(23, r1)
1244 REST_GPR(31, r1)
1245 lwz r2,_NIP(r1) /* Restore environment */
1246 lwz r0,_MSR(r1)
1247 mtspr SRR0,r2
1248 mtspr SRR1,r0
1249 lwz r0,GPR0(r1)
1250 lwz r2,GPR2(r1)
1251 lwz r1,GPR1(r1)
1252 SYNC
1253 rfi
1254
1255 crit_return:
1256 mfmsr r28 /* Disable interrupts */
1257 li r4,0
1258 ori r4,r4,MSR_EE
1259 andc r28,r28,r4
1260 SYNC /* Some chip revs need this... */
1261 mtmsr r28
1262 SYNC
1263 lwz r2,_CTR(r1)
1264 lwz r0,_LINK(r1)
1265 mtctr r2
1266 mtlr r0
1267 lwz r2,_XER(r1)
1268 lwz r0,_CCR(r1)
1269 mtspr XER,r2
1270 mtcrf 0xFF,r0
1271 REST_10GPRS(3, r1)
1272 REST_10GPRS(13, r1)
1273 REST_8GPRS(23, r1)
1274 REST_GPR(31, r1)
1275 lwz r2,_NIP(r1) /* Restore environment */
1276 lwz r0,_MSR(r1)
1277 mtspr SPRN_CSRR0,r2
1278 mtspr SPRN_CSRR1,r0
1279 lwz r0,GPR0(r1)
1280 lwz r2,GPR2(r1)
1281 lwz r1,GPR1(r1)
1282 SYNC
1283 rfci
1284
1285 #ifdef CONFIG_440
1286 mck_return:
1287 mfmsr r28 /* Disable interrupts */
1288 li r4,0
1289 ori r4,r4,MSR_EE
1290 andc r28,r28,r4
1291 SYNC /* Some chip revs need this... */
1292 mtmsr r28
1293 SYNC
1294 lwz r2,_CTR(r1)
1295 lwz r0,_LINK(r1)
1296 mtctr r2
1297 mtlr r0
1298 lwz r2,_XER(r1)
1299 lwz r0,_CCR(r1)
1300 mtspr XER,r2
1301 mtcrf 0xFF,r0
1302 REST_10GPRS(3, r1)
1303 REST_10GPRS(13, r1)
1304 REST_8GPRS(23, r1)
1305 REST_GPR(31, r1)
1306 lwz r2,_NIP(r1) /* Restore environment */
1307 lwz r0,_MSR(r1)
1308 mtspr SPRN_MCSRR0,r2
1309 mtspr SPRN_MCSRR1,r0
1310 lwz r0,GPR0(r1)
1311 lwz r2,GPR2(r1)
1312 lwz r1,GPR1(r1)
1313 SYNC
1314 rfmci
1315 #endif /* CONFIG_440 */
1316
1317
1318 .globl get_pvr
1319 get_pvr:
1320 mfspr r3, PVR
1321 blr
1322
1323 /*------------------------------------------------------------------------------- */
1324 /* Function: out16 */
1325 /* Description: Output 16 bits */
1326 /*------------------------------------------------------------------------------- */
1327 .globl out16
1328 out16:
1329 sth r4,0x0000(r3)
1330 blr
1331
1332 /*------------------------------------------------------------------------------- */
1333 /* Function: out16r */
1334 /* Description: Byte reverse and output 16 bits */
1335 /*------------------------------------------------------------------------------- */
1336 .globl out16r
1337 out16r:
1338 sthbrx r4,r0,r3
1339 blr
1340
1341 /*------------------------------------------------------------------------------- */
1342 /* Function: out32r */
1343 /* Description: Byte reverse and output 32 bits */
1344 /*------------------------------------------------------------------------------- */
1345 .globl out32r
1346 out32r:
1347 stwbrx r4,r0,r3
1348 blr
1349
1350 /*------------------------------------------------------------------------------- */
1351 /* Function: in16 */
1352 /* Description: Input 16 bits */
1353 /*------------------------------------------------------------------------------- */
1354 .globl in16
1355 in16:
1356 lhz r3,0x0000(r3)
1357 blr
1358
1359 /*------------------------------------------------------------------------------- */
1360 /* Function: in16r */
1361 /* Description: Input 16 bits and byte reverse */
1362 /*------------------------------------------------------------------------------- */
1363 .globl in16r
1364 in16r:
1365 lhbrx r3,r0,r3
1366 blr
1367
1368 /*------------------------------------------------------------------------------- */
1369 /* Function: in32r */
1370 /* Description: Input 32 bits and byte reverse */
1371 /*------------------------------------------------------------------------------- */
1372 .globl in32r
1373 in32r:
1374 lwbrx r3,r0,r3
1375 blr
1376
1377 /*
1378 * void relocate_code (addr_sp, gd, addr_moni)
1379 *
1380 * This "function" does not return, instead it continues in RAM
1381 * after relocating the monitor code.
1382 *
1383 * r3 = Relocated stack pointer
1384 * r4 = Relocated global data pointer
1385 * r5 = Relocated text pointer
1386 */
1387 .globl relocate_code
1388 relocate_code:
1389 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1390 /*
1391 * We need to flush the initial global data (gd_t) before the dcache
1392 * will be invalidated.
1393 */
1394
1395 /* Save registers */
1396 mr r9, r3
1397 mr r10, r4
1398 mr r11, r5
1399
1400 /* Flush initial global data range */
1401 mr r3, r4
1402 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
1403 bl flush_dcache_range
1404
1405 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1406 /*
1407 * Undo the earlier data cache set-up for the primordial stack and
1408 * data area. First, invalidate the data cache and then disable data
1409 * cacheability for that area. Finally, restore the EBC values, if
1410 * any.
1411 */
1412
1413 /* Invalidate the primordial stack and data area in cache */
1414 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1415 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1416
1417 lis r4, CONFIG_SYS_INIT_RAM_END@h
1418 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1419 add r4, r4, r3
1420
1421 bl invalidate_dcache_range
1422
1423 /* Disable cacheability for the region */
1424 mfdccr r3
1425 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1426 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1427 and r3, r3, r4
1428 mtdccr r3
1429
1430 /* Restore the EBC parameters */
1431 li r3, PBxAP
1432 mtdcr EBC0_CFGADDR, r3
1433 lis r3, PBxAP_VAL@h
1434 ori r3, r3, PBxAP_VAL@l
1435 mtdcr EBC0_CFGDATA, r3
1436
1437 li r3, PBxCR
1438 mtdcr EBC0_CFGADDR, r3
1439 lis r3, PBxCR_VAL@h
1440 ori r3, r3, PBxCR_VAL@l
1441 mtdcr EBC0_CFGDATA, r3
1442 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1443
1444 /* Restore registers */
1445 mr r3, r9
1446 mr r4, r10
1447 mr r5, r11
1448 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1449
1450 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1451 /*
1452 * Unlock the previously locked d-cache
1453 */
1454 msync
1455 isync
1456 /* set TFLOOR/NFLOOR to 0 again */
1457 lis r6,0x0001
1458 ori r6,r6,0xf800
1459 mtspr SPRN_DVLIM,r6
1460 lis r6,0x0000
1461 ori r6,r6,0x0000
1462 mtspr SPRN_DNV0,r6
1463 mtspr SPRN_DNV1,r6
1464 mtspr SPRN_DNV2,r6
1465 mtspr SPRN_DNV3,r6
1466 mtspr SPRN_DTV0,r6
1467 mtspr SPRN_DTV1,r6
1468 mtspr SPRN_DTV2,r6
1469 mtspr SPRN_DTV3,r6
1470 msync
1471 isync
1472
1473 /* Invalidate data cache, now no longer our stack */
1474 dccci 0,0
1475 sync
1476 isync
1477 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1478
1479 /*
1480 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1481 * to speed up the boot process. Now this cache needs to be disabled.
1482 */
1483 #if defined(CONFIG_440)
1484 /* Clear all potential pending exceptions */
1485 mfspr r1,SPRN_MCSR
1486 mtspr SPRN_MCSR,r1
1487 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1488 tlbre r0,r1,0x0002 /* Read contents */
1489 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1490 tlbwe r0,r1,0x0002 /* Save it out */
1491 sync
1492 isync
1493 #endif /* defined(CONFIG_440) */
1494 mr r1, r3 /* Set new stack pointer */
1495 mr r9, r4 /* Save copy of Init Data pointer */
1496 mr r10, r5 /* Save copy of Destination Address */
1497
1498 GET_GOT
1499 mr r3, r5 /* Destination Address */
1500 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1501 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1502 lwz r5, GOT(__init_end)
1503 sub r5, r5, r4
1504 li r6, L1_CACHE_BYTES /* Cache Line Size */
1505
1506 /*
1507 * Fix GOT pointer:
1508 *
1509 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1510 *
1511 * Offset:
1512 */
1513 sub r15, r10, r4
1514
1515 /* First our own GOT */
1516 add r12, r12, r15
1517 /* then the one used by the C code */
1518 add r30, r30, r15
1519
1520 /*
1521 * Now relocate code
1522 */
1523
1524 cmplw cr1,r3,r4
1525 addi r0,r5,3
1526 srwi. r0,r0,2
1527 beq cr1,4f /* In place copy is not necessary */
1528 beq 7f /* Protect against 0 count */
1529 mtctr r0
1530 bge cr1,2f
1531
1532 la r8,-4(r4)
1533 la r7,-4(r3)
1534 1: lwzu r0,4(r8)
1535 stwu r0,4(r7)
1536 bdnz 1b
1537 b 4f
1538
1539 2: slwi r0,r0,2
1540 add r8,r4,r0
1541 add r7,r3,r0
1542 3: lwzu r0,-4(r8)
1543 stwu r0,-4(r7)
1544 bdnz 3b
1545
1546 /*
1547 * Now flush the cache: note that we must start from a cache aligned
1548 * address. Otherwise we might miss one cache line.
1549 */
1550 4: cmpwi r6,0
1551 add r5,r3,r5
1552 beq 7f /* Always flush prefetch queue in any case */
1553 subi r0,r6,1
1554 andc r3,r3,r0
1555 mr r4,r3
1556 5: dcbst 0,r4
1557 add r4,r4,r6
1558 cmplw r4,r5
1559 blt 5b
1560 sync /* Wait for all dcbst to complete on bus */
1561 mr r4,r3
1562 6: icbi 0,r4
1563 add r4,r4,r6
1564 cmplw r4,r5
1565 blt 6b
1566 7: sync /* Wait for all icbi to complete on bus */
1567 isync
1568
1569 /*
1570 * We are done. Do not return, instead branch to second part of board
1571 * initialization, now running from RAM.
1572 */
1573
1574 addi r0, r10, in_ram - _start + _START_OFFSET
1575 mtlr r0
1576 blr /* NEVER RETURNS! */
1577
1578 in_ram:
1579
1580 /*
1581 * Relocation Function, r12 point to got2+0x8000
1582 *
1583 * Adjust got2 pointers, no need to check for 0, this code
1584 * already puts a few entries in the table.
1585 */
1586 li r0,__got2_entries@sectoff@l
1587 la r3,GOT(_GOT2_TABLE_)
1588 lwz r11,GOT(_GOT2_TABLE_)
1589 mtctr r0
1590 sub r11,r3,r11
1591 addi r3,r3,-4
1592 1: lwzu r0,4(r3)
1593 cmpwi r0,0
1594 beq- 2f
1595 add r0,r0,r11
1596 stw r0,0(r3)
1597 2: bdnz 1b
1598
1599 /*
1600 * Now adjust the fixups and the pointers to the fixups
1601 * in case we need to move ourselves again.
1602 */
1603 li r0,__fixup_entries@sectoff@l
1604 lwz r3,GOT(_FIXUP_TABLE_)
1605 cmpwi r0,0
1606 mtctr r0
1607 addi r3,r3,-4
1608 beq 4f
1609 3: lwzu r4,4(r3)
1610 lwzux r0,r4,r11
1611 add r0,r0,r11
1612 stw r10,0(r3)
1613 stw r0,0(r4)
1614 bdnz 3b
1615 4:
1616 clear_bss:
1617 /*
1618 * Now clear BSS segment
1619 */
1620 lwz r3,GOT(__bss_start)
1621 lwz r4,GOT(_end)
1622
1623 cmplw 0, r3, r4
1624 beq 7f
1625
1626 li r0, 0
1627
1628 andi. r5, r4, 3
1629 beq 6f
1630 sub r4, r4, r5
1631 mtctr r5
1632 mr r5, r4
1633 5: stb r0, 0(r5)
1634 addi r5, r5, 1
1635 bdnz 5b
1636 6:
1637 stw r0, 0(r3)
1638 addi r3, r3, 4
1639 cmplw 0, r3, r4
1640 bne 6b
1641
1642 7:
1643 mr r3, r9 /* Init Data pointer */
1644 mr r4, r10 /* Destination Address */
1645 bl board_init_r
1646
1647 /*
1648 * Copy exception vector code to low memory
1649 *
1650 * r3: dest_addr
1651 * r7: source address, r8: end address, r9: target address
1652 */
1653 .globl trap_init
1654 trap_init:
1655 mflr r4 /* save link register */
1656 GET_GOT
1657 lwz r7, GOT(_start_of_vectors)
1658 lwz r8, GOT(_end_of_vectors)
1659
1660 li r9, 0x100 /* reset vector always at 0x100 */
1661
1662 cmplw 0, r7, r8
1663 bgelr /* return if r7>=r8 - just in case */
1664 1:
1665 lwz r0, 0(r7)
1666 stw r0, 0(r9)
1667 addi r7, r7, 4
1668 addi r9, r9, 4
1669 cmplw 0, r7, r8
1670 bne 1b
1671
1672 /*
1673 * relocate `hdlr' and `int_return' entries
1674 */
1675 li r7, .L_MachineCheck - _start + _START_OFFSET
1676 li r8, Alignment - _start + _START_OFFSET
1677 2:
1678 bl trap_reloc
1679 addi r7, r7, 0x100 /* next exception vector */
1680 cmplw 0, r7, r8
1681 blt 2b
1682
1683 li r7, .L_Alignment - _start + _START_OFFSET
1684 bl trap_reloc
1685
1686 li r7, .L_ProgramCheck - _start + _START_OFFSET
1687 bl trap_reloc
1688
1689 #ifdef CONFIG_440
1690 li r7, .L_FPUnavailable - _start + _START_OFFSET
1691 bl trap_reloc
1692
1693 li r7, .L_Decrementer - _start + _START_OFFSET
1694 bl trap_reloc
1695
1696 li r7, .L_APU - _start + _START_OFFSET
1697 bl trap_reloc
1698
1699 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1700 bl trap_reloc
1701
1702 li r7, .L_DataTLBError - _start + _START_OFFSET
1703 bl trap_reloc
1704 #else /* CONFIG_440 */
1705 li r7, .L_PIT - _start + _START_OFFSET
1706 bl trap_reloc
1707
1708 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1709 bl trap_reloc
1710
1711 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1712 bl trap_reloc
1713 #endif /* CONFIG_440 */
1714
1715 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1716 bl trap_reloc
1717
1718 #if !defined(CONFIG_440)
1719 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1720 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1721 mtmsr r7 /* change MSR */
1722 #else
1723 bl __440_msr_set
1724 b __440_msr_continue
1725
1726 __440_msr_set:
1727 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1728 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1729 mtspr SPRN_SRR1,r7
1730 mflr r7
1731 mtspr SPRN_SRR0,r7
1732 rfi
1733 __440_msr_continue:
1734 #endif
1735
1736 mtlr r4 /* restore link register */
1737 blr
1738
1739 #if defined(CONFIG_440)
1740 /*----------------------------------------------------------------------------+
1741 | dcbz_area.
1742 +----------------------------------------------------------------------------*/
1743 function_prolog(dcbz_area)
1744 rlwinm. r5,r4,0,27,31
1745 rlwinm r5,r4,27,5,31
1746 beq ..d_ra2
1747 addi r5,r5,0x0001
1748 ..d_ra2:mtctr r5
1749 ..d_ag2:dcbz r0,r3
1750 addi r3,r3,32
1751 bdnz ..d_ag2
1752 sync
1753 blr
1754 function_epilog(dcbz_area)
1755 #endif /* CONFIG_440 */
1756 #endif /* CONFIG_NAND_SPL */
1757
1758 /*------------------------------------------------------------------------------- */
1759 /* Function: in8 */
1760 /* Description: Input 8 bits */
1761 /*------------------------------------------------------------------------------- */
1762 .globl in8
1763 in8:
1764 lbz r3,0x0000(r3)
1765 blr
1766
1767 /*------------------------------------------------------------------------------- */
1768 /* Function: out8 */
1769 /* Description: Output 8 bits */
1770 /*------------------------------------------------------------------------------- */
1771 .globl out8
1772 out8:
1773 stb r4,0x0000(r3)
1774 blr
1775
1776 /*------------------------------------------------------------------------------- */
1777 /* Function: out32 */
1778 /* Description: Output 32 bits */
1779 /*------------------------------------------------------------------------------- */
1780 .globl out32
1781 out32:
1782 stw r4,0x0000(r3)
1783 blr
1784
1785 /*------------------------------------------------------------------------------- */
1786 /* Function: in32 */
1787 /* Description: Input 32 bits */
1788 /*------------------------------------------------------------------------------- */
1789 .globl in32
1790 in32:
1791 lwz 3,0x0000(3)
1792 blr
1793
1794 /**************************************************************************/
1795 /* PPC405EP specific stuff */
1796 /**************************************************************************/
1797 #ifdef CONFIG_405EP
1798 ppc405ep_init:
1799
1800 #ifdef CONFIG_BUBINGA
1801 /*
1802 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1803 * function) to support FPGA and NVRAM accesses below.
1804 */
1805
1806 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1807 ori r3,r3,GPIO0_OSRH@l
1808 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1809 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1810 stw r4,0(r3)
1811 lis r3,GPIO0_OSRL@h
1812 ori r3,r3,GPIO0_OSRL@l
1813 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1814 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1815 stw r4,0(r3)
1816
1817 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1818 ori r3,r3,GPIO0_ISR1H@l
1819 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1820 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1821 stw r4,0(r3)
1822 lis r3,GPIO0_ISR1L@h
1823 ori r3,r3,GPIO0_ISR1L@l
1824 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1825 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1826 stw r4,0(r3)
1827
1828 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1829 ori r3,r3,GPIO0_TSRH@l
1830 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1831 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1832 stw r4,0(r3)
1833 lis r3,GPIO0_TSRL@h
1834 ori r3,r3,GPIO0_TSRL@l
1835 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1836 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1837 stw r4,0(r3)
1838
1839 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1840 ori r3,r3,GPIO0_TCR@l
1841 lis r4,CONFIG_SYS_GPIO0_TCR@h
1842 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1843 stw r4,0(r3)
1844
1845 li r3,PB1AP /* program EBC bank 1 for RTC access */
1846 mtdcr EBC0_CFGADDR,r3
1847 lis r3,CONFIG_SYS_EBC_PB1AP@h
1848 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1849 mtdcr EBC0_CFGDATA,r3
1850 li r3,PB1CR
1851 mtdcr EBC0_CFGADDR,r3
1852 lis r3,CONFIG_SYS_EBC_PB1CR@h
1853 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1854 mtdcr EBC0_CFGDATA,r3
1855
1856 li r3,PB1AP /* program EBC bank 1 for RTC access */
1857 mtdcr EBC0_CFGADDR,r3
1858 lis r3,CONFIG_SYS_EBC_PB1AP@h
1859 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1860 mtdcr EBC0_CFGDATA,r3
1861 li r3,PB1CR
1862 mtdcr EBC0_CFGADDR,r3
1863 lis r3,CONFIG_SYS_EBC_PB1CR@h
1864 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1865 mtdcr EBC0_CFGDATA,r3
1866
1867 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1868 mtdcr EBC0_CFGADDR,r3
1869 lis r3,CONFIG_SYS_EBC_PB4AP@h
1870 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1871 mtdcr EBC0_CFGDATA,r3
1872 li r3,PB4CR
1873 mtdcr EBC0_CFGADDR,r3
1874 lis r3,CONFIG_SYS_EBC_PB4CR@h
1875 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1876 mtdcr EBC0_CFGDATA,r3
1877 #endif
1878
1879 /*
1880 !-----------------------------------------------------------------------
1881 ! Check to see if chip is in bypass mode.
1882 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1883 ! CPU reset Otherwise, skip this step and keep going.
1884 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1885 ! will not be fast enough for the SDRAM (min 66MHz)
1886 !-----------------------------------------------------------------------
1887 */
1888 mfdcr r5, CPC0_PLLMR1
1889 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1890 cmpi cr0,0,r4,0x1
1891
1892 beq pll_done /* if SSCS =b'1' then PLL has */
1893 /* already been set */
1894 /* and CPU has been reset */
1895 /* so skip to next section */
1896
1897 #ifdef CONFIG_BUBINGA
1898 /*
1899 !-----------------------------------------------------------------------
1900 ! Read NVRAM to get value to write in PLLMR.
1901 ! If value has not been correctly saved, write default value
1902 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1903 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1904 !
1905 ! WARNING: This code assumes the first three words in the nvram_t
1906 ! structure in openbios.h. Changing the beginning of
1907 ! the structure will break this code.
1908 !
1909 !-----------------------------------------------------------------------
1910 */
1911 addis r3,0,NVRAM_BASE@h
1912 addi r3,r3,NVRAM_BASE@l
1913
1914 lwz r4, 0(r3)
1915 addis r5,0,NVRVFY1@h
1916 addi r5,r5,NVRVFY1@l
1917 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1918 bne ..no_pllset
1919 addi r3,r3,4
1920 lwz r4, 0(r3)
1921 addis r5,0,NVRVFY2@h
1922 addi r5,r5,NVRVFY2@l
1923 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1924 bne ..no_pllset
1925 addi r3,r3,8 /* Skip over conf_size */
1926 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1927 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1928 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1929 cmpi cr0,0,r5,1 /* See if PLL is locked */
1930 beq pll_write
1931 ..no_pllset:
1932 #endif /* CONFIG_BUBINGA */
1933
1934 #ifdef CONFIG_TAIHU
1935 mfdcr r4, CPC0_BOOT
1936 andi. r5, r4, CPC0_BOOT_SEP@l
1937 bne strap_1 /* serial eeprom present */
1938 addis r5,0,CPLD_REG0_ADDR@h
1939 ori r5,r5,CPLD_REG0_ADDR@l
1940 andi. r5, r5, 0x10
1941 bne _pci_66mhz
1942 #endif /* CONFIG_TAIHU */
1943
1944 #if defined(CONFIG_ZEUS)
1945 mfdcr r4, CPC0_BOOT
1946 andi. r5, r4, CPC0_BOOT_SEP@l
1947 bne strap_1 /* serial eeprom present */
1948 lis r3,0x0000
1949 addi r3,r3,0x3030
1950 lis r4,0x8042
1951 addi r4,r4,0x223e
1952 b 1f
1953 strap_1:
1954 mfdcr r3, CPC0_PLLMR0
1955 mfdcr r4, CPC0_PLLMR1
1956 b 1f
1957 #endif
1958
1959 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1960 ori r3,r3,PLLMR0_DEFAULT@l /* */
1961 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1962 ori r4,r4,PLLMR1_DEFAULT@l /* */
1963
1964 #ifdef CONFIG_TAIHU
1965 b 1f
1966 _pci_66mhz:
1967 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1968 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1969 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1970 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1971 b 1f
1972 strap_1:
1973 mfdcr r3, CPC0_PLLMR0
1974 mfdcr r4, CPC0_PLLMR1
1975 #endif /* CONFIG_TAIHU */
1976
1977 1:
1978 b pll_write /* Write the CPC0_PLLMR with new value */
1979
1980 pll_done:
1981 /*
1982 !-----------------------------------------------------------------------
1983 ! Clear Soft Reset Register
1984 ! This is needed to enable PCI if not booting from serial EPROM
1985 !-----------------------------------------------------------------------
1986 */
1987 addi r3, 0, 0x0
1988 mtdcr CPC0_SRR, r3
1989
1990 addis r3,0,0x0010
1991 mtctr r3
1992 pci_wait:
1993 bdnz pci_wait
1994
1995 blr /* return to main code */
1996
1997 /*
1998 !-----------------------------------------------------------------------------
1999 ! Function: pll_write
2000 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
2001 ! That is:
2002 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
2003 ! 2. PLL is reset
2004 ! 3. Clock dividers are set while PLL is held in reset and bypassed
2005 ! 4. PLL Reset is cleared
2006 ! 5. Wait 100us for PLL to lock
2007 ! 6. A core reset is performed
2008 ! Input: r3 = Value to write to CPC0_PLLMR0
2009 ! Input: r4 = Value to write to CPC0_PLLMR1
2010 ! Output r3 = none
2011 !-----------------------------------------------------------------------------
2012 */
2013 .globl pll_write
2014 pll_write:
2015 mfdcr r5, CPC0_UCR
2016 andis. r5,r5,0xFFFF
2017 ori r5,r5,0x0101 /* Stop the UART clocks */
2018 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2019
2020 mfdcr r5, CPC0_PLLMR1
2021 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2022 mtdcr CPC0_PLLMR1,r5
2023 oris r5,r5,0x4000 /* Set PLL Reset */
2024 mtdcr CPC0_PLLMR1,r5
2025
2026 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2027 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2028 oris r5,r5,0x4000 /* Set PLL Reset */
2029 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2030 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2031 mtdcr CPC0_PLLMR1,r5
2032
2033 /*
2034 ! Wait min of 100us for PLL to lock.
2035 ! See CMOS 27E databook for more info.
2036 ! At 200MHz, that means waiting 20,000 instructions
2037 */
2038 addi r3,0,20000 /* 2000 = 0x4e20 */
2039 mtctr r3
2040 pll_wait:
2041 bdnz pll_wait
2042
2043 oris r5,r5,0x8000 /* Enable PLL */
2044 mtdcr CPC0_PLLMR1,r5 /* Engage */
2045
2046 /*
2047 * Reset CPU to guarantee timings are OK
2048 * Not sure if this is needed...
2049 */
2050 addis r3,0,0x1000
2051 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
2052 /* execution will continue from the poweron */
2053 /* vector of 0xfffffffc */
2054 #endif /* CONFIG_405EP */
2055
2056 #if defined(CONFIG_440)
2057 /*----------------------------------------------------------------------------+
2058 | mttlb3.
2059 +----------------------------------------------------------------------------*/
2060 function_prolog(mttlb3)
2061 TLBWE(4,3,2)
2062 blr
2063 function_epilog(mttlb3)
2064
2065 /*----------------------------------------------------------------------------+
2066 | mftlb3.
2067 +----------------------------------------------------------------------------*/
2068 function_prolog(mftlb3)
2069 TLBRE(3,3,2)
2070 blr
2071 function_epilog(mftlb3)
2072
2073 /*----------------------------------------------------------------------------+
2074 | mttlb2.
2075 +----------------------------------------------------------------------------*/
2076 function_prolog(mttlb2)
2077 TLBWE(4,3,1)
2078 blr
2079 function_epilog(mttlb2)
2080
2081 /*----------------------------------------------------------------------------+
2082 | mftlb2.
2083 +----------------------------------------------------------------------------*/
2084 function_prolog(mftlb2)
2085 TLBRE(3,3,1)
2086 blr
2087 function_epilog(mftlb2)
2088
2089 /*----------------------------------------------------------------------------+
2090 | mttlb1.
2091 +----------------------------------------------------------------------------*/
2092 function_prolog(mttlb1)
2093 TLBWE(4,3,0)
2094 blr
2095 function_epilog(mttlb1)
2096
2097 /*----------------------------------------------------------------------------+
2098 | mftlb1.
2099 +----------------------------------------------------------------------------*/
2100 function_prolog(mftlb1)
2101 TLBRE(3,3,0)
2102 blr
2103 function_epilog(mftlb1)
2104 #endif /* CONFIG_440 */
2105
2106 #if defined(CONFIG_NAND_SPL)
2107 /*
2108 * void nand_boot_relocate(dst, src, bytes)
2109 *
2110 * r3 = Destination address to copy code to (in SDRAM)
2111 * r4 = Source address to copy code from
2112 * r5 = size to copy in bytes
2113 */
2114 nand_boot_relocate:
2115 mr r6,r3
2116 mr r7,r4
2117 mflr r8
2118
2119 /*
2120 * Copy SPL from icache into SDRAM
2121 */
2122 subi r3,r3,4
2123 subi r4,r4,4
2124 srwi r5,r5,2
2125 mtctr r5
2126 ..spl_loop:
2127 lwzu r0,4(r4)
2128 stwu r0,4(r3)
2129 bdnz ..spl_loop
2130
2131 /*
2132 * Calculate "corrected" link register, so that we "continue"
2133 * in execution in destination range
2134 */
2135 sub r3,r7,r6 /* r3 = src - dst */
2136 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2137 mtlr r8
2138 blr
2139
2140 nand_boot_common:
2141 /*
2142 * First initialize SDRAM. It has to be available *before* calling
2143 * nand_boot().
2144 */
2145 lis r3,CONFIG_SYS_SDRAM_BASE@h
2146 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2147 bl initdram
2148
2149 /*
2150 * Now copy the 4k SPL code into SDRAM and continue execution
2151 * from there.
2152 */
2153 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2154 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2155 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2156 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2157 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2158 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2159 bl nand_boot_relocate
2160
2161 /*
2162 * We're running from SDRAM now!!!
2163 *
2164 * It is necessary for 4xx systems to relocate from running at
2165 * the original location (0xfffffxxx) to somewhere else (SDRAM
2166 * preferably). This is because CS0 needs to be reconfigured for
2167 * NAND access. And we can't reconfigure this CS when currently
2168 * "running" from it.
2169 */
2170
2171 /*
2172 * Finally call nand_boot() to load main NAND U-Boot image from
2173 * NAND and jump to it.
2174 */
2175 bl nand_boot /* will not return */
2176 #endif /* CONFIG_NAND_SPL */
"Das U-Boot" Source Tree