arch/powerpc/include/asm/fsl_pci.h

   1 /*
   2  * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __FSL_PCI_H_
   8 #define __FSL_PCI_H_
   9
  10 #include <asm/fsl_law.h>
  11 #include <asm/fsl_serdes.h>
  12 #include <pci.h>
  13
  14 #define PEX_IP_BLK_REV_2_2      0x02080202
  15 #define PEX_IP_BLK_REV_2_3      0x02080203
  16
  17 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
  18 int fsl_is_pci_agent(struct pci_controller *hose);
  19 void fsl_pci_config_unlock(struct pci_controller *hose);
  20 void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
  21
  22 /*
  23  * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
  24  */
  25
  26 /*
  27  * PCI Translation Registers
  28  */
  29 typedef struct pci_outbound_window {
  30         u32     potar;          /* 0x00 - Address */
  31         u32     potear;         /* 0x04 - Address Extended */
  32         u32     powbar;         /* 0x08 - Window Base Address */
  33         u32     res1;
  34         u32     powar;          /* 0x10 - Window Attributes */
  35 #define POWAR_EN        0x80000000
  36 #define POWAR_IO_READ   0x00080000
  37 #define POWAR_MEM_READ  0x00040000
  38 #define POWAR_IO_WRITE  0x00008000
  39 #define POWAR_MEM_WRITE 0x00004000
  40         u32     res2[3];
  41 } pot_t;
  42
  43 typedef struct pci_inbound_window {
  44         u32     pitar;          /* 0x00 - Address */
  45         u32     res1;
  46         u32     piwbar;         /* 0x08 - Window Base Address */
  47         u32     piwbear;        /* 0x0c - Window Base Address Extended */
  48         u32     piwar;          /* 0x10 - Window Attributes */
  49 #define PIWAR_EN                0x80000000
  50 #define PIWAR_PF                0x20000000
  51 #define PIWAR_LOCAL             0x00f00000
  52 #define PIWAR_READ_SNOOP        0x00050000
  53 #define PIWAR_WRITE_SNOOP       0x00005000
  54         u32     res2[3];
  55 } pit_t;
  56
  57 /* PCI/PCI Express Registers */
  58 typedef struct ccsr_pci {
  59         u32     cfg_addr;       /* 0x000 - PCI Configuration Address Register */
  60         u32     cfg_data;       /* 0x004 - PCI Configuration Data Register */
  61         u32     int_ack;        /* 0x008 - PCI Interrupt Acknowledge Register */
  62         u32     out_comp_to;    /* 0x00C - PCI Outbound Completion Timeout Register */
  63         u32     out_conf_to;    /* 0x010 - PCI Configuration Timeout Register */
  64         u32     config;         /* 0x014 - PCIE CONFIG Register */
  65         u32     int_status;     /* 0x018 - PCIE interrupt status register */
  66         char    res2[4];
  67         u32     pme_msg_det;    /* 0x020 - PCIE PME & message detect register */
  68         u32     pme_msg_dis;    /* 0x024 - PCIE PME & message disable register */
  69         u32     pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
  70         u32     pm_command;     /* 0x02c - PCIE PM Command register */
  71         char    res4[3016];     /*     (- #xbf8  #x30)3016 */
  72         u32     block_rev1;     /* 0xbf8 - PCIE Block Revision register 1 */
  73         u32     block_rev2;     /* 0xbfc - PCIE Block Revision register 2 */
  74
  75         pot_t   pot[5];         /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
  76         u32     res5[24];
  77         pit_t   pmit;           /* 0xd00 - 0xd9c Inbound ATMU's MSI */
  78         u32     res6[24];
  79         pit_t   pit[4];         /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
  80
  81 #define PIT3 0
  82 #define PIT2 1
  83 #define PIT1 2
  84
  85 #if 0
  86         u32     potar0;         /* 0xc00 - PCI Outbound Transaction Address Register 0 */
  87         u32     potear0;        /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
  88         char    res5[8];
  89         u32     powar0;         /* 0xc10 - PCI Outbound Window Attributes Register 0 */
  90         char    res6[12];
  91         u32     potar1;         /* 0xc20 - PCI Outbound Transaction Address Register 1 */
  92         u32     potear1;        /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
  93         u32     powbar1;        /* 0xc28 - PCI Outbound Window Base Address Register 1 */
  94         char    res7[4];
  95         u32     powar1;         /* 0xc30 - PCI Outbound Window Attributes Register 1 */
  96         char    res8[12];
  97         u32     potar2;         /* 0xc40 - PCI Outbound Transaction Address Register 2 */
  98         u32     potear2;        /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
  99         u32     powbar2;        /* 0xc48 - PCI Outbound Window Base Address Register 2 */
 100         char    res9[4];
 101         u32     powar2;         /* 0xc50 - PCI Outbound Window Attributes Register 2 */
 102         char    res10[12];
 103         u32     potar3;         /* 0xc60 - PCI Outbound Transaction Address Register 3 */
 104         u32     potear3;        /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
 105         u32     powbar3;        /* 0xc68 - PCI Outbound Window Base Address Register 3 */
 106         char    res11[4];
 107         u32     powar3;         /* 0xc70 - PCI Outbound Window Attributes Register 3 */
 108         char    res12[12];
 109         u32     potar4;         /* 0xc80 - PCI Outbound Transaction Address Register 4 */
 110         u32     potear4;        /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
 111         u32     powbar4;        /* 0xc88 - PCI Outbound Window Base Address Register 4 */
 112         char    res13[4];
 113         u32     powar4;         /* 0xc90 - PCI Outbound Window Attributes Register 4 */
 114         char    res14[268];
 115         u32     pitar3;         /* 0xda0 - PCI Inbound Translation Address Register 3 */
 116         char    res15[4];
 117         u32     piwbar3;        /* 0xda8 - PCI Inbound Window Base Address Register 3 */
 118         u32     piwbear3;       /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
 119         u32     piwar3;         /* 0xdb0 - PCI Inbound Window Attributes Register 3 */
 120         char    res16[12];
 121         u32     pitar2;         /* 0xdc0 - PCI Inbound Translation Address Register 2 */
 122         char    res17[4];
 123         u32     piwbar2;        /* 0xdc8 - PCI Inbound Window Base Address Register 2 */
 124         u32     piwbear2;       /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
 125         u32     piwar2;         /* 0xdd0 - PCI Inbound Window Attributes Register 2 */
 126         char    res18[12];
 127         u32     pitar1;         /* 0xde0 - PCI Inbound Translation Address Register 1 */
 128         char    res19[4];
 129         u32     piwbar1;        /* 0xde8 - PCI Inbound Window Base Address Register 1 */
 130         char    res20[4];
 131         u32     piwar1;         /* 0xdf0 - PCI Inbound Window Attributes Register 1 */
 132         char    res21[12];
 133 #endif
 134         u32     pedr;           /* 0xe00 - PCI Error Detect Register */
 135         u32     pecdr;          /* 0xe04 - PCI Error Capture Disable Register */
 136         u32     peer;           /* 0xe08 - PCI Error Interrupt Enable Register */
 137         u32     peattrcr;       /* 0xe0c - PCI Error Attributes Capture Register */
 138         u32     peaddrcr;       /* 0xe10 - PCI Error Address Capture Register */
 139 /*      u32     perr_disr        * 0xe10 - PCIE Erorr Disable Register */
 140         u32     peextaddrcr;    /* 0xe14 - PCI  Error Extended Address Capture Register */
 141         u32     pedlcr;         /* 0xe18 - PCI Error Data Low Capture Register */
 142         u32     pedhcr;         /* 0xe1c - PCI Error Error Data High Capture Register */
 143         u32     gas_timr;       /* 0xe20 - PCI Gasket Timer Register */
 144 /*      u32     perr_cap_stat;   * 0xe20 - PCIE Error Capture Status Register */
 145         char    res22[4];
 146         u32     perr_cap0;      /* 0xe28 - PCIE Error Capture Register 0 */
 147         u32     perr_cap1;      /* 0xe2c - PCIE Error Capture Register 1 */
 148         u32     perr_cap2;      /* 0xe30 - PCIE Error Capture Register 2 */
 149         u32     perr_cap3;      /* 0xe34 - PCIE Error Capture Register 3 */
 150         char    res23[200];
 151         u32     pdb_stat;       /* 0xf00 - PCIE Debug Status */
 152         char    res24[252];
 153 } ccsr_fsl_pci_t;
 154 #define PCIE_CONFIG_PC  0x00020000
 155 #define PCIE_CONFIG_OB_CK       0x00002000
 156 #define PCIE_CONFIG_SAC 0x00000010
 157 #define PCIE_CONFIG_SP  0x80000002
 158 #define PCIE_CONFIG_SCC 0x80000001
 159
 160 struct fsl_pci_info {
 161         unsigned long regs;
 162         pci_addr_t mem_bus;
 163         phys_size_t mem_phys;
 164         pci_size_t mem_size;
 165         pci_addr_t io_bus;
 166         phys_size_t io_phys;
 167         pci_size_t io_size;
 168         enum law_trgt_if law;
 169         int pci_num;
 170 };
 171
 172 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info);
 173 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 174                                 struct pci_controller *hose, int busno);
 175 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
 176                         struct fsl_pci_info *pci_info);
 177 int fsl_pcie_init_board(int busno);
 178
 179 #define SET_STD_PCI_INFO(x, num) \
 180 {                       \
 181         x.regs = CONFIG_SYS_PCI##num##_ADDR;    \
 182         x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
 183         x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
 184         x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
 185         x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
 186         x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
 187         x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
 188         x.law = LAW_TRGT_IF_PCI_##num; \
 189         x.pci_num = num; \
 190 }
 191
 192 #define SET_STD_PCIE_INFO(x, num) \
 193 {                       \
 194         x.regs = CONFIG_SYS_PCIE##num##_ADDR;   \
 195         x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
 196         x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
 197         x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
 198         x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
 199         x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
 200         x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
 201         x.law = LAW_TRGT_IF_PCIE_##num; \
 202         x.pci_num = num; \
 203 }
 204
 205 #define __FT_FSL_PCI_SETUP(blob, compat, num) \
 206         ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
 207
 208 #define __FT_FSL_PCIE_SETUP(blob, compat, num) \
 209         ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
 210
 211 #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
 212 #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
 213
 214 #define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
 215 #define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
 216 #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
 217 #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
 218
 219 #if !defined(CONFIG_PCI)
 220 #define FT_FSL_PCI_SETUP
 221 #elif defined(CONFIG_FSL_CORENET)
 222 #define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
 223 #define FT_FSL_PCI_SETUP \
 224         FT_FSL_PCIE1_SETUP; \
 225         FT_FSL_PCIE2_SETUP; \
 226         FT_FSL_PCIE3_SETUP; \
 227         FT_FSL_PCIE4_SETUP;
 228 #define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
 229 #elif defined(CONFIG_MPC85xx)
 230 #define FSL_PCI_COMPAT  "fsl,mpc8540-pci"
 231 #ifdef CONFIG_SYS_FSL_PCIE_COMPAT
 232 #define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
 233 #else
 234 #define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
 235 #endif
 236 #define FT_FSL_PCI_SETUP \
 237         FT_FSL_PCI1_SETUP; \
 238         FT_FSL_PCI2_SETUP; \
 239         FT_FSL_PCIE1_SETUP; \
 240         FT_FSL_PCIE2_SETUP; \
 241         FT_FSL_PCIE3_SETUP;
 242 #define FT_FSL_PCIE_SETUP \
 243         FT_FSL_PCIE1_SETUP; \
 244         FT_FSL_PCIE2_SETUP; \
 245         FT_FSL_PCIE3_SETUP;
 246 #elif defined(CONFIG_MPC86xx)
 247 #define FSL_PCI_COMPAT  "fsl,mpc8610-pci"
 248 #define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
 249 #define FT_FSL_PCI_SETUP \
 250         FT_FSL_PCI1_SETUP; \
 251         FT_FSL_PCIE1_SETUP; \
 252         FT_FSL_PCIE2_SETUP;
 253 #else
 254 #error FT_FSL_PCI_SETUP not defined
 255 #endif
 256
 257
 258 #endif