arch/ppc/cpu/mpc8xxx/pci_cfg.c

   1 /*
   2  * Copyright 2009-2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/fsl_law.h>
  25 #include <pci.h>
  26
  27 struct pci_info {
  28         u32     cfg;
  29 };
  30
  31 /* The cfg field is a bit mask in which each bit represents the value of
  32  * cfg_IO_ports[] signal and the bit is set if the interface would be
  33  * enabled based on the value of cfg_IO_ports[] signal
  34  *
  35  * On MPC86xx/PQ3 based systems:
  36  *   we extract cfg_IO_ports from GUTS register PORDEVSR
  37  *
  38  * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems
  39  * without PCIe)
  40  */
  41
  42 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560)
  43 static struct pci_info pci_config_info[] =
  44 {
  45         [LAW_TRGT_IF_PCI] = {
  46                 .cfg =   0,
  47         },
  48 };
  49 #elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
  50 static struct pci_info pci_config_info[] =
  51 {
  52         [LAW_TRGT_IF_PCI] = {
  53                 .cfg =   0,
  54         },
  55 };
  56 #elif defined(CONFIG_MPC8536)
  57 static struct pci_info pci_config_info[] =
  58 {
  59         [LAW_TRGT_IF_PCI] = {
  60                 .cfg =   0,
  61         },
  62         [LAW_TRGT_IF_PCIE_1] = {
  63                 .cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7),
  64         },
  65         [LAW_TRGT_IF_PCIE_2] = {
  66                 .cfg =   (1 << 5) | (1 << 7),
  67         },
  68         [LAW_TRGT_IF_PCIE_3] = {
  69                 .cfg =   (1 << 7),
  70         },
  71 };
  72 #elif defined(CONFIG_MPC8544)
  73 static struct pci_info pci_config_info[] =
  74 {
  75         [LAW_TRGT_IF_PCI] = {
  76                 .cfg =   0,
  77         },
  78         [LAW_TRGT_IF_PCIE_1] = {
  79                 .cfg =   (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
  80                          (1 << 6) | (1 << 7),
  81         },
  82         [LAW_TRGT_IF_PCIE_2] = {
  83                 .cfg =   (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7),
  84         },
  85         [LAW_TRGT_IF_PCIE_3] = {
  86                 .cfg =   (1 << 6) | (1 << 7),
  87         },
  88 };
  89 #elif defined(CONFIG_MPC8548)
  90 static struct pci_info pci_config_info[] =
  91 {
  92         [LAW_TRGT_IF_PCI_1] = {
  93                 .cfg =   0,
  94         },
  95         [LAW_TRGT_IF_PCI_2] = {
  96                 .cfg =   0,
  97         },
  98         /* PCI_2 is always host and we dont use iosel to determine enable/disable */
  99         [LAW_TRGT_IF_PCIE_1] = {
 100                 .cfg =   (1 << 3) | (1 << 4) | (1 << 7),
 101         },
 102 };
 103 #elif defined(CONFIG_MPC8568)
 104 static struct pci_info pci_config_info[] =
 105 {
 106         [LAW_TRGT_IF_PCI] = {
 107                 .cfg =   0,
 108         },
 109         [LAW_TRGT_IF_PCIE_1] = {
 110                 .cfg =   (1 << 3) | (1 << 4) | (1 << 7),
 111         },
 112 };
 113 #elif defined(CONFIG_MPC8569)
 114 static struct pci_info pci_config_info[] =
 115 {
 116         [LAW_TRGT_IF_PCIE_1] = {
 117                 .cfg =   (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
 118                          (1 << 8) | (1 << 0xc) | (1 << 0xf),
 119         },
 120 };
 121 #elif defined(CONFIG_MPC8572)
 122 static struct pci_info pci_config_info[] =
 123 {
 124         [LAW_TRGT_IF_PCIE_1] = {
 125                 .cfg =   (1 << 2) | (1 << 3) | (1 << 7) |
 126                          (1 << 0xb) | (1 << 0xc) | (1 << 0xf),
 127         },
 128         [LAW_TRGT_IF_PCIE_2] = {
 129                 .cfg =   (1 << 3) | (1 << 7),
 130         },
 131         [LAW_TRGT_IF_PCIE_3] = {
 132                 .cfg =   (1 << 7),
 133         },
 134 };
 135 #elif defined(CONFIG_MPC8610)
 136 static struct pci_info pci_config_info[] =
 137 {
 138         [LAW_TRGT_IF_PCI_1] = {
 139                 .cfg =   0,
 140         },
 141         [LAW_TRGT_IF_PCIE_1] = {
 142                 .cfg =   (1 << 1) | (1 << 4),
 143         },
 144         [LAW_TRGT_IF_PCIE_2] = {
 145                 .cfg =   (1 << 0) | (1 << 4),
 146         },
 147 };
 148 #elif defined(CONFIG_MPC8641)
 149 static struct pci_info pci_config_info[] =
 150 {
 151         [LAW_TRGT_IF_PCIE_1] = {
 152                 .cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) |
 153                          (1 << 7) | (1 << 0xe) | (1 << 0xf),
 154         },
 155 };
 156 #elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
 157       defined(CONFIG_P1012) || defined(CONFIG_P1021)
 158 static struct pci_info pci_config_info[] =
 159 {
 160         [LAW_TRGT_IF_PCIE_1] = {
 161                 .cfg =   (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf),
 162         },
 163         [LAW_TRGT_IF_PCIE_2] = {
 164                 .cfg =   (1 << 0xe),
 165         },
 166 };
 167 #elif defined(CONFIG_P1013) || defined(CONFIG_P1022)
 168 static struct pci_info pci_config_info[] =
 169 {
 170         [LAW_TRGT_IF_PCIE_1] = {
 171                 .cfg =   (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) |
 172                          (1 << 0xb) | (1 << 0xd) | (1 << 0xe) |
 173                          (1 << 0xf) | (1 << 0x15) | (1 << 0x16) |
 174                          (1 << 0x17) | (1 << 0x18) | (1 << 0x19) |
 175                          (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) |
 176                          (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
 177         },
 178         [LAW_TRGT_IF_PCIE_2] = {
 179                 .cfg =   (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) |
 180                          (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) |
 181                          (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
 182                          (1 << 0x18) | (1 << 0x1c),
 183         },
 184         [LAW_TRGT_IF_PCIE_3] = {
 185                 .cfg =   (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) |
 186                          (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) |
 187                          (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
 188         },
 189 };
 190 #elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
 191 static struct pci_info pci_config_info[] =
 192 {
 193         [LAW_TRGT_IF_PCIE_1] = {
 194                 .cfg =   (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) |
 195                          (1 << 0xd) | (1 << 0xe) | (1 << 0xf),
 196         },
 197         [LAW_TRGT_IF_PCIE_2] = {
 198                 .cfg =   (1 << 2) | (1 << 0xe),
 199         },
 200         [LAW_TRGT_IF_PCIE_3] = {
 201                 .cfg =   (1 << 2) | (1 << 4),
 202         },
 203 };
 204 #elif defined(CONFIG_FSL_CORENET)
 205 #else
 206 #error Need to define pci_config_info for processor
 207 #endif
 208
 209 #ifndef CONFIG_FSL_CORENET
 210 int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel)
 211 {
 212         return ((1 << io_sel) & pci_config_info[trgt].cfg);
 213 }
 214 #endif