arch/ppc/cpu/ppc4xx/cpu.c

   1 /*
   2  * (C) Copyright 2000-2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * CPU specific code
  26  *
  27  * written or collected and sometimes rewritten by
  28  * Magnus Damm <damm@bitsmart.com>
  29  *
  30  * minor modifications by
  31  * Wolfgang Denk <wd@denx.de>
  32  */
  33
  34 #include <common.h>
  35 #include <watchdog.h>
  36 #include <command.h>
  37 #include <asm/cache.h>
  38 #include <ppc4xx.h>
  39 #include <netdev.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 void board_reset(void);
  44
  45 /*
  46  * To provide an interface to detect CPU number for boards that support
  47  * more then one CPU, we implement the "weak" default functions here.
  48  *
  49  * Returns CPU number
  50  */
  51 int __get_cpu_num(void)
  52 {
  53         return NA_OR_UNKNOWN_CPU;
  54 }
  55 int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
  56
  57 #if defined(CONFIG_PCI)
  58 #if defined(CONFIG_405GP) || \
  59     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  60     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  61
  62 #define PCI_ASYNC
  63
  64 static int pci_async_enabled(void)
  65 {
  66 #if defined(CONFIG_405GP)
  67         return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
  68 #endif
  69
  70 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  71     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  72     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  73         unsigned long val;
  74
  75         mfsdr(SDR0_SDSTP1, val);
  76         return (val & SDR0_SDSTP1_PAME_MASK);
  77 #endif
  78 }
  79 #endif
  80 #endif /* CONFIG_PCI */
  81
  82 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
  83     !defined(CONFIG_405) && !defined(CONFIG_405EX)
  84 int pci_arbiter_enabled(void)
  85 {
  86 #if defined(CONFIG_405GP)
  87         return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
  88 #endif
  89
  90 #if defined(CONFIG_405EP)
  91         return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
  92 #endif
  93
  94 #if defined(CONFIG_440GP)
  95         return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
  96 #endif
  97
  98 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  99         unsigned long val;
 100
 101         mfsdr(SDR0_XCR, val);
 102         return (val & 0x80000000);
 103 #endif
 104 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
 105     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 106     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 107         unsigned long val;
 108
 109         mfsdr(SDR0_PCI0, val);
 110         return (val & 0x80000000);
 111 #endif
 112 }
 113 #endif
 114
 115 #if defined(CONFIG_405EP)
 116 #define I2C_BOOTROM
 117
 118 static int i2c_bootrom_enabled(void)
 119 {
 120 #if defined(CONFIG_405EP)
 121         return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
 122 #else
 123         unsigned long val;
 124
 125         mfsdr(SDR0_SDCS0, val);
 126         return (val & SDR0_SDCS_SDD);
 127 #endif
 128 }
 129 #endif
 130
 131 #if defined(CONFIG_440GX)
 132 #define SDR0_PINSTP_SHIFT       29
 133 static char *bootstrap_str[] = {
 134         "EBC (16 bits)",
 135         "EBC (8 bits)",
 136         "EBC (32 bits)",
 137         "EBC (8 bits)",
 138         "PCI",
 139         "I2C (Addr 0x54)",
 140         "Reserved",
 141         "I2C (Addr 0x50)",
 142 };
 143 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
 144 #endif
 145
 146 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 147 #define SDR0_PINSTP_SHIFT       30
 148 static char *bootstrap_str[] = {
 149         "EBC (8 bits)",
 150         "PCI",
 151         "I2C (Addr 0x54)",
 152         "I2C (Addr 0x50)",
 153 };
 154 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
 155 #endif
 156
 157 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 158 #define SDR0_PINSTP_SHIFT       29
 159 static char *bootstrap_str[] = {
 160         "EBC (8 bits)",
 161         "PCI",
 162         "NAND (8 bits)",
 163         "EBC (16 bits)",
 164         "EBC (16 bits)",
 165         "I2C (Addr 0x54)",
 166         "PCI",
 167         "I2C (Addr 0x52)",
 168 };
 169 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 170 #endif
 171
 172 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 173 #define SDR0_PINSTP_SHIFT       29
 174 static char *bootstrap_str[] = {
 175         "EBC (8 bits)",
 176         "EBC (16 bits)",
 177         "EBC (16 bits)",
 178         "NAND (8 bits)",
 179         "PCI",
 180         "I2C (Addr 0x54)",
 181         "PCI",
 182         "I2C (Addr 0x52)",
 183 };
 184 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 185 #endif
 186
 187 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 188 #define SDR0_PINSTP_SHIFT       29
 189 static char *bootstrap_str[] = {
 190         "EBC (8 bits)",
 191         "EBC (16 bits)",
 192         "PCI",
 193         "PCI",
 194         "EBC (16 bits)",
 195         "NAND (8 bits)",
 196         "I2C (Addr 0x54)",      /* A8 */
 197         "I2C (Addr 0x52)",      /* A4 */
 198 };
 199 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
 200 #endif
 201
 202 #if defined(CONFIG_460SX)
 203 #define SDR0_PINSTP_SHIFT       29
 204 static char *bootstrap_str[] = {
 205         "EBC (8 bits)",
 206         "EBC (16 bits)",
 207         "EBC (32 bits)",
 208         "NAND (8 bits)",
 209         "I2C (Addr 0x54)",      /* A8 */
 210         "I2C (Addr 0x52)",      /* A4 */
 211 };
 212 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
 213 #endif
 214
 215 #if defined(CONFIG_405EZ)
 216 #define SDR0_PINSTP_SHIFT       28
 217 static char *bootstrap_str[] = {
 218         "EBC (8 bits)",
 219         "SPI (fast)",
 220         "NAND (512 page, 4 addr cycle)",
 221         "I2C (Addr 0x50)",
 222         "EBC (32 bits)",
 223         "I2C (Addr 0x50)",
 224         "NAND (2K page, 5 addr cycle)",
 225         "I2C (Addr 0x50)",
 226         "EBC (16 bits)",
 227         "Reserved",
 228         "NAND (2K page, 4 addr cycle)",
 229         "I2C (Addr 0x50)",
 230         "NAND (512 page, 3 addr cycle)",
 231         "I2C (Addr 0x50)",
 232         "SPI (slow)",
 233         "I2C (Addr 0x50)",
 234 };
 235 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
 236                                  'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
 237 #endif
 238
 239 #if defined(CONFIG_405EX)
 240 #define SDR0_PINSTP_SHIFT       29
 241 static char *bootstrap_str[] = {
 242         "EBC (8 bits)",
 243         "EBC (16 bits)",
 244         "EBC (16 bits)",
 245         "NAND (8 bits)",
 246         "NAND (8 bits)",
 247         "I2C (Addr 0x54)",
 248         "EBC (8 bits)",
 249         "I2C (Addr 0x52)",
 250 };
 251 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 252 #endif
 253
 254 #if defined(SDR0_PINSTP_SHIFT)
 255 static int bootstrap_option(void)
 256 {
 257         unsigned long val;
 258
 259         mfsdr(SDR0_PINSTP, val);
 260         return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
 261 }
 262 #endif /* SDR0_PINSTP_SHIFT */
 263
 264
 265 #if defined(CONFIG_440)
 266 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
 267 {
 268         /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
 269          * reset.
 270          */
 271         mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000);        /* Set SWE */
 272         mtdcr (CPC0_SYS0, sys0);
 273         mtdcr (CPC0_SYS1, sys1);
 274         mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000);       /* Clr SWE */
 275         mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
 276
 277         return 1;
 278 }
 279 #endif
 280
 281
 282 int checkcpu (void)
 283 {
 284 #if !defined(CONFIG_405)        /* not used on Xilinx 405 FPGA implementations */
 285         uint pvr = get_pvr();
 286         ulong clock = gd->cpu_clk;
 287         char buf[32];
 288 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 289         u32 reg;
 290 #endif
 291
 292 #if !defined(CONFIG_IOP480)
 293         char addstr[64] = "";
 294         sys_info_t sys_info;
 295         int cpu_num;
 296
 297         cpu_num = get_cpu_num();
 298         if (cpu_num >= 0)
 299                 printf("CPU%d:  ", cpu_num);
 300         else
 301                 puts("CPU:   ");
 302
 303         get_sys_info(&sys_info);
 304
 305 #if defined(CONFIG_XILINX_440)
 306         puts("IBM PowerPC 4");
 307 #else
 308         puts("AMCC PowerPC 4");
 309 #endif
 310
 311 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
 312     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 313     defined(CONFIG_405EX)
 314         puts("05");
 315 #endif
 316 #if defined(CONFIG_440)
 317 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 318         puts("60");
 319 #else
 320         puts("40");
 321 #endif
 322 #endif
 323
 324         switch (pvr) {
 325         case PVR_405GP_RB:
 326                 puts("GP Rev. B");
 327                 break;
 328
 329         case PVR_405GP_RC:
 330                 puts("GP Rev. C");
 331                 break;
 332
 333         case PVR_405GP_RD:
 334                 puts("GP Rev. D");
 335                 break;
 336
 337 #ifdef CONFIG_405GP
 338         case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
 339                 puts("GP Rev. E");
 340                 break;
 341 #endif
 342
 343         case PVR_405CR_RA:
 344                 puts("CR Rev. A");
 345                 break;
 346
 347         case PVR_405CR_RB:
 348                 puts("CR Rev. B");
 349                 break;
 350
 351 #ifdef CONFIG_405CR
 352         case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
 353                 puts("CR Rev. C");
 354                 break;
 355 #endif
 356
 357         case PVR_405GPR_RB:
 358                 puts("GPr Rev. B");
 359                 break;
 360
 361         case PVR_405EP_RB:
 362                 puts("EP Rev. B");
 363                 break;
 364
 365         case PVR_405EZ_RA:
 366                 puts("EZ Rev. A");
 367                 break;
 368
 369         case PVR_405EX1_RA:
 370                 puts("EX Rev. A");
 371                 strcpy(addstr, "Security support");
 372                 break;
 373
 374         case PVR_405EXR2_RA:
 375                 puts("EXr Rev. A");
 376                 strcpy(addstr, "No Security support");
 377                 break;
 378
 379         case PVR_405EX1_RC:
 380                 puts("EX Rev. C");
 381                 strcpy(addstr, "Security support");
 382                 break;
 383
 384         case PVR_405EX2_RC:
 385                 puts("EX Rev. C");
 386                 strcpy(addstr, "No Security support");
 387                 break;
 388
 389         case PVR_405EXR1_RC:
 390                 puts("EXr Rev. C");
 391                 strcpy(addstr, "Security support");
 392                 break;
 393
 394         case PVR_405EXR2_RC:
 395                 puts("EXr Rev. C");
 396                 strcpy(addstr, "No Security support");
 397                 break;
 398
 399         case PVR_405EX1_RD:
 400                 puts("EX Rev. D");
 401                 strcpy(addstr, "Security support");
 402                 break;
 403
 404         case PVR_405EX2_RD:
 405                 puts("EX Rev. D");
 406                 strcpy(addstr, "No Security support");
 407                 break;
 408
 409         case PVR_405EXR1_RD:
 410                 puts("EXr Rev. D");
 411                 strcpy(addstr, "Security support");
 412                 break;
 413
 414         case PVR_405EXR2_RD:
 415                 puts("EXr Rev. D");
 416                 strcpy(addstr, "No Security support");
 417                 break;
 418
 419 #if defined(CONFIG_440)
 420         case PVR_440GP_RB:
 421                 puts("GP Rev. B");
 422                 /* See errata 1.12: CHIP_4 */
 423                 if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
 424                     (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
 425                         puts (  "\n\t CPC0_SYSx DCRs corrupted. "
 426                                 "Resetting chip ...\n");
 427                         udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
 428                         do_chip_reset ( mfdcr(CPC0_STRP0),
 429                                         mfdcr(CPC0_STRP1) );
 430                 }
 431                 break;
 432
 433         case PVR_440GP_RC:
 434                 puts("GP Rev. C");
 435                 break;
 436
 437         case PVR_440GX_RA:
 438                 puts("GX Rev. A");
 439                 break;
 440
 441         case PVR_440GX_RB:
 442                 puts("GX Rev. B");
 443                 break;
 444
 445         case PVR_440GX_RC:
 446                 puts("GX Rev. C");
 447                 break;
 448
 449         case PVR_440GX_RF:
 450                 puts("GX Rev. F");
 451                 break;
 452
 453         case PVR_440EP_RA:
 454                 puts("EP Rev. A");
 455                 break;
 456
 457 #ifdef CONFIG_440EP
 458         case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
 459                 puts("EP Rev. B");
 460                 break;
 461
 462         case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
 463                 puts("EP Rev. C");
 464                 break;
 465 #endif /*  CONFIG_440EP */
 466
 467 #ifdef CONFIG_440GR
 468         case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
 469                 puts("GR Rev. A");
 470                 break;
 471
 472         case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
 473                 puts("GR Rev. B");
 474                 break;
 475 #endif /* CONFIG_440GR */
 476 #endif /* CONFIG_440 */
 477
 478 #ifdef CONFIG_440EPX
 479         case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 480                 puts("EPx Rev. A");
 481                 strcpy(addstr, "Security/Kasumi support");
 482                 break;
 483
 484         case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 485                 puts("EPx Rev. A");
 486                 strcpy(addstr, "No Security/Kasumi support");
 487                 break;
 488 #endif /* CONFIG_440EPX */
 489
 490 #ifdef CONFIG_440GRX
 491         case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 492                 puts("GRx Rev. A");
 493                 strcpy(addstr, "Security/Kasumi support");
 494                 break;
 495
 496         case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 497                 puts("GRx Rev. A");
 498                 strcpy(addstr, "No Security/Kasumi support");
 499                 break;
 500 #endif /* CONFIG_440GRX */
 501
 502         case PVR_440SP_6_RAB:
 503                 puts("SP Rev. A/B");
 504                 strcpy(addstr, "RAID 6 support");
 505                 break;
 506
 507         case PVR_440SP_RAB:
 508                 puts("SP Rev. A/B");
 509                 strcpy(addstr, "No RAID 6 support");
 510                 break;
 511
 512         case PVR_440SP_6_RC:
 513                 puts("SP Rev. C");
 514                 strcpy(addstr, "RAID 6 support");
 515                 break;
 516
 517         case PVR_440SP_RC:
 518                 puts("SP Rev. C");
 519                 strcpy(addstr, "No RAID 6 support");
 520                 break;
 521
 522         case PVR_440SPe_6_RA:
 523                 puts("SPe Rev. A");
 524                 strcpy(addstr, "RAID 6 support");
 525                 break;
 526
 527         case PVR_440SPe_RA:
 528                 puts("SPe Rev. A");
 529                 strcpy(addstr, "No RAID 6 support");
 530                 break;
 531
 532         case PVR_440SPe_6_RB:
 533                 puts("SPe Rev. B");
 534                 strcpy(addstr, "RAID 6 support");
 535                 break;
 536
 537         case PVR_440SPe_RB:
 538                 puts("SPe Rev. B");
 539                 strcpy(addstr, "No RAID 6 support");
 540                 break;
 541
 542 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 543         case PVR_460EX_RA:
 544                 puts("EX Rev. A");
 545                 strcpy(addstr, "No Security/Kasumi support");
 546                 break;
 547
 548         case PVR_460EX_SE_RA:
 549                 puts("EX Rev. A");
 550                 strcpy(addstr, "Security/Kasumi support");
 551                 break;
 552
 553         case PVR_460EX_RB:
 554                 puts("EX Rev. B");
 555                 mfsdr(SDR0_ECID3, reg);
 556                 if (reg & 0x00100000)
 557                         strcpy(addstr, "No Security/Kasumi support");
 558                 else
 559                         strcpy(addstr, "Security/Kasumi support");
 560                 break;
 561
 562         case PVR_460GT_RA:
 563                 puts("GT Rev. A");
 564                 strcpy(addstr, "No Security/Kasumi support");
 565                 break;
 566
 567         case PVR_460GT_SE_RA:
 568                 puts("GT Rev. A");
 569                 strcpy(addstr, "Security/Kasumi support");
 570                 break;
 571
 572         case PVR_460GT_RB:
 573                 puts("GT Rev. B");
 574                 mfsdr(SDR0_ECID3, reg);
 575                 if (reg & 0x00100000)
 576                         strcpy(addstr, "No Security/Kasumi support");
 577                 else
 578                         strcpy(addstr, "Security/Kasumi support");
 579                 break;
 580 #endif
 581
 582         case PVR_460SX_RA:
 583                 puts("SX Rev. A");
 584                 strcpy(addstr, "Security support");
 585                 break;
 586
 587         case PVR_460SX_RA_V1:
 588                 puts("SX Rev. A");
 589                 strcpy(addstr, "No Security support");
 590                 break;
 591
 592         case PVR_460GX_RA:
 593                 puts("GX Rev. A");
 594                 strcpy(addstr, "Security support");
 595                 break;
 596
 597         case PVR_460GX_RA_V1:
 598                 puts("GX Rev. A");
 599                 strcpy(addstr, "No Security support");
 600                 break;
 601
 602         case PVR_VIRTEX5:
 603                 puts("x5 VIRTEX5");
 604                 break;
 605
 606         default:
 607                 printf (" UNKNOWN (PVR=%08x)", pvr);
 608                 break;
 609         }
 610
 611         printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
 612                 strmhz(buf, clock),
 613                 sys_info.freqPLB / 1000000,
 614                 get_OPB_freq() / 1000000,
 615                 sys_info.freqEBC / 1000000);
 616 #if defined(CONFIG_PCI) && \
 617         (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
 618          defined(CONFIG_440GR) || defined(CONFIG_440GRX))
 619         printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
 620 #endif
 621         printf(")\n");
 622
 623         if (addstr[0] != 0)
 624                 printf("       %s\n", addstr);
 625
 626 #if defined(I2C_BOOTROM)
 627         printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
 628 #endif  /* I2C_BOOTROM */
 629 #if defined(SDR0_PINSTP_SHIFT)
 630         printf ("       Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
 631         printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
 632 #ifdef CONFIG_NAND_U_BOOT
 633         puts(", booting from NAND");
 634 #endif /* CONFIG_NAND_U_BOOT */
 635         putc('\n');
 636 #endif  /* SDR0_PINSTP_SHIFT */
 637
 638 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
 639         printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
 640 #endif
 641
 642 #if defined(CONFIG_PCI) && defined(PCI_ASYNC)
 643         if (pci_async_enabled()) {
 644                 printf (", PCI async ext clock used");
 645         } else {
 646                 printf (", PCI sync clock at %lu MHz",
 647                        sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
 648         }
 649 #endif
 650
 651 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
 652         putc('\n');
 653 #endif
 654
 655 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
 656         printf ("       16 kB I-Cache 16 kB D-Cache");
 657 #elif defined(CONFIG_440)
 658         printf ("       32 kB I-Cache 32 kB D-Cache");
 659 #else
 660         printf ("       16 kB I-Cache %d kB D-Cache",
 661                 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
 662 #endif
 663 #endif /* !defined(CONFIG_IOP480) */
 664
 665 #if defined(CONFIG_IOP480)
 666         printf ("PLX IOP480 (PVR=%08x)", pvr);
 667         printf (" at %s MHz:", strmhz(buf, clock));
 668         printf (" %u kB I-Cache", 4);
 669         printf (" %u kB D-Cache", 2);
 670 #endif
 671
 672 #endif /* !defined(CONFIG_405) */
 673
 674         putc ('\n');
 675
 676         return 0;
 677 }
 678
 679 int ppc440spe_revB() {
 680         unsigned int pvr;
 681
 682         pvr = get_pvr();
 683         if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
 684                 return 1;
 685         else
 686                 return 0;
 687 }
 688
 689 /* ------------------------------------------------------------------------- */
 690
 691 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 692 {
 693 #if defined(CONFIG_BOARD_RESET)
 694         board_reset();
 695 #else
 696 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
 697         mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
 698 #else
 699         /*
 700          * Initiate system reset in debug control register DBCR
 701          */
 702         mtspr(SPRN_DBCR0, 0x30000000);
 703 #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
 704 #endif /* defined(CONFIG_BOARD_RESET) */
 705
 706         return 1;
 707 }
 708
 709
 710 /*
 711  * Get timebase clock frequency
 712  */
 713 unsigned long get_tbclk (void)
 714 {
 715 #if !defined(CONFIG_IOP480)
 716         sys_info_t  sys_info;
 717
 718         get_sys_info(&sys_info);
 719         return (sys_info.freqProcessor);
 720 #else
 721         return (66000000);
 722 #endif
 723
 724 }
 725
 726
 727 #if defined(CONFIG_WATCHDOG)
 728 void watchdog_reset(void)
 729 {
 730         int re_enable = disable_interrupts();
 731         reset_4xx_watchdog();
 732         if (re_enable) enable_interrupts();
 733 }
 734
 735 void reset_4xx_watchdog(void)
 736 {
 737         /*
 738          * Clear TSR(WIS) bit
 739          */
 740         mtspr(SPRN_TSR, 0x40000000);
 741 }
 742 #endif  /* CONFIG_WATCHDOG */
 743
 744 /*
 745  * Initializes on-chip ethernet controllers.
 746  * to override, implement board_eth_init()
 747  */
 748 int cpu_eth_init(bd_t *bis)
 749 {
 750 #if defined(CONFIG_PPC4xx_EMAC)
 751         ppc_4xx_eth_initialize(bis);
 752 #endif
 753         return 0;
 754 }