]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/sh/cpu/sh4/cache.c
3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
15 * When handling TLB or caches, we need to do it from P2 area.
17 #define jump_to_P2() \
19 unsigned long __dummy; \
20 __asm__ __volatile__( \
29 : "r" (0x20000000)); \
35 #define back_to_P1() \
37 unsigned long __dummy; \
38 __asm__ __volatile__( \
39 "nop;nop;nop;nop;nop;nop;nop\n\t" \
50 #define CACHE_UPDATED 2
52 static inline void cache_wback_all(void)
54 unsigned long addr
, data
, i
, j
;
57 for (i
= 0; i
< CACHE_OC_NUM_ENTRIES
; i
++){
58 for (j
= 0; j
< CACHE_OC_NUM_WAYS
; j
++) {
59 addr
= CACHE_OC_ADDRESS_ARRAY
| (j
<< CACHE_OC_WAY_SHIFT
)
60 | (i
<< CACHE_OC_ENTRY_SHIFT
);
62 if (data
& CACHE_UPDATED
) {
63 data
&= ~CACHE_UPDATED
;
72 #define CACHE_ENABLE 0
73 #define CACHE_DISABLE 1
75 int cache_control(unsigned int cmd
)
82 if (ccr
& CCR_CACHE_ENABLE
)
85 if (cmd
== CACHE_DISABLE
)
86 outl(CCR_CACHE_STOP
, CCR
);
88 outl(CCR_CACHE_INIT
, CCR
);
94 void flush_dcache_range(unsigned long start
, unsigned long end
)
98 start
&= ~(L1_CACHE_BYTES
- 1);
99 for (v
= start
; v
< end
; v
+= L1_CACHE_BYTES
) {
100 asm volatile ("ocbwb %0" : /* no output */
105 void invalidate_dcache_range(unsigned long start
, unsigned long end
)
109 start
&= ~(L1_CACHE_BYTES
- 1);
110 for (v
= start
; v
< end
; v
+= L1_CACHE_BYTES
) {
111 asm volatile ("ocbi %0" : /* no output */