arch/sh/include/asm/cpu_sh7706.h

   1 #ifndef _ASM_CPU_SH7706_H_
   2 #define _ASM_CPU_SH7706_H_
   3
   4 #define CACHE_OC_NUM_WAYS       4
   5 #define CCR_CACHE_INIT  0x0000000D
   6
   7 /* MMU and Cache control */
   8 #define MMUCR   0xFFFFFFE0
   9 #define CCR             0xFFFFFFEC
  10
  11 /* PFC */
  12 #define PACR            0xA4050100
  13 #define PBCR            0xA4050102
  14 #define PCCR            0xA4050104
  15 #define PETCR           0xA4050106
  16
  17 /* Port Data Registers */
  18 #define PADR            0xA4050120
  19 #define PBDR            0xA4050122
  20 #define PCDR            0xA4050124
  21
  22 /* BSC */
  23 #define FRQCR   0xffffff80
  24 #define BCR1    0xffffff60
  25 #define BCR2    0xffffff62
  26 #define WCR1    0xffffff64
  27 #define WCR2    0xffffff66
  28 #define MCR             0xffffff68
  29
  30 /* SDRAM controller */
  31 #define DCR             0xffffff6a
  32 #define RTCSR   0xffffff6e
  33 #define RTCNT   0xffffff70
  34 #define RTCOR   0xffffff72
  35 #define RFCR    0xffffff74
  36 #define SDMR    0xFFFFD000
  37 #define CS3_R   0xFFFFE460
  38
  39 /* SCIF */
  40 #define SCSMR_2         0xA4000150
  41 #define SCIF0_BASE      SCSMR_2
  42
  43 /* Timer */
  44 #define TSTR0           0xFFFFFE92
  45 #define TSTR            TSTR0
  46 #define TCNT0           0xFFFFFE98
  47 #define TCR0            0xFFFFFE9C
  48
  49 /* On chip oscillator circuits */
  50 #define WTCNT   0xFFFFFF84
  51 #define WTCSR   0xFFFFFF86
  52
  53 #endif  /* _ASM_CPU_SH7706_H_ */