arch/x86/Kconfig

   1 menu "x86 architecture"
   2         depends on X86
   3
   4 config SYS_ARCH
   5         default "x86"
   6
   7 choice
   8         prompt "Mainboard vendor"
   9         default VENDOR_EMULATION
  10
  11 config VENDOR_ADVANTECH
  12         bool "advantech"
  13
  14 config VENDOR_CONGATEC
  15         bool "congatec"
  16
  17 config VENDOR_COREBOOT
  18         bool "coreboot"
  19
  20 config VENDOR_DFI
  21         bool "dfi"
  22
  23 config VENDOR_EFI
  24         bool "efi"
  25
  26 config VENDOR_EMULATION
  27         bool "emulation"
  28
  29 config VENDOR_GOOGLE
  30         bool "Google"
  31
  32 config VENDOR_INTEL
  33         bool "Intel"
  34
  35 endchoice
  36
  37 # board-specific options below
  38 source "board/advantech/Kconfig"
  39 source "board/congatec/Kconfig"
  40 source "board/coreboot/Kconfig"
  41 source "board/dfi/Kconfig"
  42 source "board/efi/Kconfig"
  43 source "board/emulation/Kconfig"
  44 source "board/google/Kconfig"
  45 source "board/intel/Kconfig"
  46
  47 # platform-specific options below
  48 source "arch/x86/cpu/baytrail/Kconfig"
  49 source "arch/x86/cpu/broadwell/Kconfig"
  50 source "arch/x86/cpu/coreboot/Kconfig"
  51 source "arch/x86/cpu/ivybridge/Kconfig"
  52 source "arch/x86/cpu/qemu/Kconfig"
  53 source "arch/x86/cpu/quark/Kconfig"
  54 source "arch/x86/cpu/queensbay/Kconfig"
  55
  56 # architecture-specific options below
  57
  58 config AHCI
  59         default y
  60
  61 config SYS_MALLOC_F_LEN
  62         default 0x800
  63
  64 config RAMBASE
  65         hex
  66         default 0x100000
  67
  68 config XIP_ROM_SIZE
  69         hex
  70         depends on X86_RESET_VECTOR
  71         default ROM_SIZE
  72
  73 config CPU_ADDR_BITS
  74         int
  75         default 36
  76
  77 config HPET_ADDRESS
  78         hex
  79         default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
  80
  81 config SMM_TSEG
  82         bool
  83         default n
  84
  85 config SMM_TSEG_SIZE
  86         hex
  87
  88 config X86_RESET_VECTOR
  89         bool
  90         default n
  91
  92 config RESET_SEG_START
  93         hex
  94         depends on X86_RESET_VECTOR
  95         default 0xffff0000
  96
  97 config RESET_SEG_SIZE
  98         hex
  99         depends on X86_RESET_VECTOR
 100         default 0x10000
 101
 102 config RESET_VEC_LOC
 103         hex
 104         depends on X86_RESET_VECTOR
 105         default 0xfffffff0
 106
 107 config SYS_X86_START16
 108         hex
 109         depends on X86_RESET_VECTOR
 110         default 0xfffff800
 111
 112 config BOARD_ROMSIZE_KB_512
 113         bool
 114 config BOARD_ROMSIZE_KB_1024
 115         bool
 116 config BOARD_ROMSIZE_KB_2048
 117         bool
 118 config BOARD_ROMSIZE_KB_4096
 119         bool
 120 config BOARD_ROMSIZE_KB_8192
 121         bool
 122 config BOARD_ROMSIZE_KB_16384
 123         bool
 124
 125 choice
 126         prompt "ROM chip size"
 127         depends on X86_RESET_VECTOR
 128         default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
 129         default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
 130         default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
 131         default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
 132         default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
 133         default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
 134         help
 135           Select the size of the ROM chip you intend to flash U-Boot on.
 136
 137           The build system will take care of creating a u-boot.rom file
 138           of the matching size.
 139
 140 config UBOOT_ROMSIZE_KB_512
 141         bool "512 KB"
 142         help
 143           Choose this option if you have a 512 KB ROM chip.
 144
 145 config UBOOT_ROMSIZE_KB_1024
 146         bool "1024 KB (1 MB)"
 147         help
 148           Choose this option if you have a 1024 KB (1 MB) ROM chip.
 149
 150 config UBOOT_ROMSIZE_KB_2048
 151         bool "2048 KB (2 MB)"
 152         help
 153           Choose this option if you have a 2048 KB (2 MB) ROM chip.
 154
 155 config UBOOT_ROMSIZE_KB_4096
 156         bool "4096 KB (4 MB)"
 157         help
 158           Choose this option if you have a 4096 KB (4 MB) ROM chip.
 159
 160 config UBOOT_ROMSIZE_KB_8192
 161         bool "8192 KB (8 MB)"
 162         help
 163           Choose this option if you have a 8192 KB (8 MB) ROM chip.
 164
 165 config UBOOT_ROMSIZE_KB_16384
 166         bool "16384 KB (16 MB)"
 167         help
 168           Choose this option if you have a 16384 KB (16 MB) ROM chip.
 169
 170 endchoice
 171
 172 # Map the config names to an integer (KB).
 173 config UBOOT_ROMSIZE_KB
 174         int
 175         default 512 if UBOOT_ROMSIZE_KB_512
 176         default 1024 if UBOOT_ROMSIZE_KB_1024
 177         default 2048 if UBOOT_ROMSIZE_KB_2048
 178         default 4096 if UBOOT_ROMSIZE_KB_4096
 179         default 8192 if UBOOT_ROMSIZE_KB_8192
 180         default 16384 if UBOOT_ROMSIZE_KB_16384
 181
 182 # Map the config names to a hex value (bytes).
 183 config ROM_SIZE
 184         hex
 185         default 0x80000 if UBOOT_ROMSIZE_KB_512
 186         default 0x100000 if UBOOT_ROMSIZE_KB_1024
 187         default 0x200000 if UBOOT_ROMSIZE_KB_2048
 188         default 0x400000 if UBOOT_ROMSIZE_KB_4096
 189         default 0x800000 if UBOOT_ROMSIZE_KB_8192
 190         default 0xc00000 if UBOOT_ROMSIZE_KB_12288
 191         default 0x1000000 if UBOOT_ROMSIZE_KB_16384
 192
 193 config HAVE_INTEL_ME
 194         bool "Platform requires Intel Management Engine"
 195         help
 196           Newer higher-end devices have an Intel Management Engine (ME)
 197           which is a very large binary blob (typically 1.5MB) which is
 198           required for the platform to work. This enforces a particular
 199           SPI flash format. You will need to supply the me.bin file in
 200           your board directory.
 201
 202 config X86_RAMTEST
 203         bool "Perform a simple RAM test after SDRAM initialisation"
 204         help
 205           If there is something wrong with SDRAM then the platform will
 206           often crash within U-Boot or the kernel. This option enables a
 207           very simple RAM test that quickly checks whether the SDRAM seems
 208           to work correctly. It is not exhaustive but can save time by
 209           detecting obvious failures.
 210
 211 config HAVE_FSP
 212         bool "Add an Firmware Support Package binary"
 213         depends on !EFI
 214         help
 215           Select this option to add an Firmware Support Package binary to
 216           the resulting U-Boot image. It is a binary blob which U-Boot uses
 217           to set up SDRAM and other chipset specific initialization.
 218
 219           Note: Without this binary U-Boot will not be able to set up its
 220           SDRAM so will not boot.
 221
 222 config FSP_FILE
 223         string "Firmware Support Package binary filename"
 224         depends on HAVE_FSP
 225         default "fsp.bin"
 226         help
 227           The filename of the file to use as Firmware Support Package binary
 228           in the board directory.
 229
 230 config FSP_ADDR
 231         hex "Firmware Support Package binary location"
 232         depends on HAVE_FSP
 233         default 0xfffc0000
 234         help
 235           FSP is not Position Independent Code (PIC) and the whole FSP has to
 236           be rebased if it is placed at a location which is different from the
 237           perferred base address specified during the FSP build. Use Intel's
 238           Binary Configuration Tool (BCT) to do the rebase.
 239
 240           The default base address of 0xfffc0000 indicates that the binary must
 241           be located at offset 0xc0000 from the beginning of a 1MB flash device.
 242
 243 config FSP_TEMP_RAM_ADDR
 244         hex
 245         depends on HAVE_FSP
 246         default 0x2000000
 247         help
 248           Stack top address which is used in fsp_init() after DRAM is ready and
 249           CAR is disabled.
 250
 251 config FSP_SYS_MALLOC_F_LEN
 252         hex
 253         depends on HAVE_FSP
 254         default 0x100000
 255         help
 256           Additional size of malloc() pool before relocation.
 257
 258 config FSP_USE_UPD
 259         bool
 260         depends on HAVE_FSP
 261         default y
 262         help
 263           Most FSPs use UPD data region for some FSP customization. But there
 264           are still some FSPs that might not even have UPD. For such FSPs,
 265           override this to n in their platform Kconfig files.
 266
 267 config FSP_BROKEN_HOB
 268         bool
 269         depends on HAVE_FSP
 270         help
 271           Indicate some buggy FSPs that does not report memory used by FSP
 272           itself as reserved in the resource descriptor HOB. Select this to
 273           tell U-Boot to do some additional work to ensure U-Boot relocation
 274           do not overwrite the important boot service data which is used by
 275           FSP, otherwise the subsequent call to fsp_notify() will fail.
 276
 277 config ENABLE_MRC_CACHE
 278         bool "Enable MRC cache"
 279         depends on !EFI && !SYS_COREBOOT
 280         help
 281           Enable this feature to cause MRC data to be cached in NV storage
 282           to be used for speeding up boot time on future reboots and/or
 283           power cycles.
 284
 285           For platforms that use Intel FSP for the memory initialization,
 286           please check FSP output HOB via U-Boot command 'fsp hob' to see
 287           if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
 288           If such GUID does not exist, MRC cache is not avaiable on such
 289           platform (eg: Intel Queensbay), which means selecting this option
 290           here does not make any difference.
 291
 292 config HAVE_MRC
 293         bool "Add a System Agent binary"
 294         depends on !HAVE_FSP
 295         help
 296           Select this option to add a System Agent binary to
 297           the resulting U-Boot image. MRC stands for Memory Reference Code.
 298           It is a binary blob which U-Boot uses to set up SDRAM.
 299
 300           Note: Without this binary U-Boot will not be able to set up its
 301           SDRAM so will not boot.
 302
 303 config CACHE_MRC_BIN
 304         bool
 305         depends on HAVE_MRC
 306         default n
 307         help
 308           Enable caching for the memory reference code binary. This uses an
 309           MTRR (memory type range register) to turn on caching for the section
 310           of SPI flash that contains the memory reference code. This makes
 311           SDRAM init run faster.
 312
 313 config CACHE_MRC_SIZE_KB
 314         int
 315         depends on HAVE_MRC
 316         default 512
 317         help
 318           Sets the size of the cached area for the memory reference code.
 319           This ends at the end of SPI flash (address 0xffffffff) and is
 320           measured in KB. Typically this is set to 512, providing for 0.5MB
 321           of cached space.
 322
 323 config DCACHE_RAM_BASE
 324         hex
 325         depends on HAVE_MRC
 326         help
 327           Sets the base of the data cache area in memory space. This is the
 328           start address of the cache-as-RAM (CAR) area and the address varies
 329           depending on the CPU. Once CAR is set up, read/write memory becomes
 330           available at this address and can be used temporarily until SDRAM
 331           is working.
 332
 333 config DCACHE_RAM_SIZE
 334         hex
 335         depends on HAVE_MRC
 336         default 0x40000
 337         help
 338           Sets the total size of the data cache area in memory space. This
 339           sets the size of the cache-as-RAM (CAR) area. Note that much of the
 340           CAR space is required by the MRC. The CAR space available to U-Boot
 341           is normally at the start and typically extends to 1/4 or 1/2 of the
 342           available size.
 343
 344 config DCACHE_RAM_MRC_VAR_SIZE
 345         hex
 346         depends on HAVE_MRC
 347         help
 348           This is the amount of CAR (Cache as RAM) reserved for use by the
 349           memory reference code. This depends on the implementation of the
 350           memory reference code and must be set correctly or the board will
 351           not boot.
 352
 353 config HAVE_REFCODE
 354         bool "Add a Reference Code binary"
 355         help
 356           Select this option to add a Reference Code binary to the resulting
 357           U-Boot image. This is an Intel binary blob that handles system
 358           initialisation, in this case the PCH and System Agent.
 359
 360           Note: Without this binary (on platforms that need it such as
 361           broadwell) U-Boot will be missing some critical setup steps.
 362           Various peripherals may fail to work.
 363
 364 config SMP
 365         bool "Enable Symmetric Multiprocessing"
 366         default n
 367         help
 368           Enable use of more than one CPU in U-Boot and the Operating System
 369           when loaded. Each CPU will be started up and information can be
 370           obtained using the 'cpu' command. If this option is disabled, then
 371           only one CPU will be enabled regardless of the number of CPUs
 372           available.
 373
 374 config MAX_CPUS
 375         int "Maximum number of CPUs permitted"
 376         depends on SMP
 377         default 4
 378         help
 379           When using multi-CPU chips it is possible for U-Boot to start up
 380           more than one CPU. The stack memory used by all of these CPUs is
 381           pre-allocated so at present U-Boot wants to know the maximum
 382           number of CPUs that may be present. Set this to at least as high
 383           as the number of CPUs in your system (it uses about 4KB of RAM for
 384           each CPU).
 385
 386 config AP_STACK_SIZE
 387         hex
 388         depends on SMP
 389         default 0x1000
 390         help
 391           Each additional CPU started by U-Boot requires its own stack. This
 392           option sets the stack size used by each CPU and directly affects
 393           the memory used by this initialisation process. Typically 4KB is
 394           enough space.
 395
 396 config HAVE_VGA_BIOS
 397         bool "Add a VGA BIOS image"
 398         help
 399           Select this option if you have a VGA BIOS image that you would
 400           like to add to your ROM.
 401
 402 config VGA_BIOS_FILE
 403         string "VGA BIOS image filename"
 404         depends on HAVE_VGA_BIOS
 405         default "vga.bin"
 406         help
 407           The filename of the VGA BIOS image in the board directory.
 408
 409 config VGA_BIOS_ADDR
 410         hex "VGA BIOS image location"
 411         depends on HAVE_VGA_BIOS
 412         default 0xfff90000
 413         help
 414           The location of VGA BIOS image in the SPI flash. For example, base
 415           address of 0xfff90000 indicates that the image will be put at offset
 416           0x90000 from the beginning of a 1MB flash device.
 417
 418 menu "System tables"
 419         depends on !EFI && !SYS_COREBOOT
 420
 421 config GENERATE_PIRQ_TABLE
 422         bool "Generate a PIRQ table"
 423         default n
 424         help
 425           Generate a PIRQ routing table for this board. The PIRQ routing table
 426           is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
 427           at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
 428           It specifies the interrupt router information as well how all the PCI
 429           devices' interrupt pins are wired to PIRQs.
 430
 431 config GENERATE_SFI_TABLE
 432         bool "Generate a SFI (Simple Firmware Interface) table"
 433         help
 434           The Simple Firmware Interface (SFI) provides a lightweight method
 435           for platform firmware to pass information to the operating system
 436           via static tables in memory.  Kernel SFI support is required to
 437           boot on SFI-only platforms.  If you have ACPI tables then these are
 438           used instead.
 439
 440           U-Boot writes this table in write_sfi_table() just before booting
 441           the OS.
 442
 443           For more information, see http://simplefirmware.org
 444
 445 config GENERATE_MP_TABLE
 446         bool "Generate an MP (Multi-Processor) table"
 447         default n
 448         help
 449           Generate an MP (Multi-Processor) table for this board. The MP table
 450           provides a way for the operating system to support for symmetric
 451           multiprocessing as well as symmetric I/O interrupt handling with
 452           the local APIC and I/O APIC.
 453
 454 config GENERATE_ACPI_TABLE
 455         bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
 456         default n
 457         select QFW if QEMU
 458         help
 459           The Advanced Configuration and Power Interface (ACPI) specification
 460           provides an open standard for device configuration and management
 461           by the operating system. It defines platform-independent interfaces
 462           for configuration and power management monitoring.
 463
 464 config GENERATE_SMBIOS_TABLE
 465         bool "Generate an SMBIOS (System Management BIOS) table"
 466         default y
 467         help
 468           The System Management BIOS (SMBIOS) specification addresses how
 469           motherboard and system vendors present management information about
 470           their products in a standard format by extending the BIOS interface
 471           on Intel architecture systems.
 472
 473           Check http://www.dmtf.org/standards/smbios for details.
 474
 475 config SMBIOS_MANUFACTURER
 476         string "SMBIOS Manufacturer"
 477         depends on GENERATE_SMBIOS_TABLE
 478         default SYS_VENDOR
 479         help
 480           The board manufacturer to store in SMBIOS structures.
 481           Change this to override the default one (CONFIG_SYS_VENDOR).
 482
 483 config SMBIOS_PRODUCT_NAME
 484         string "SMBIOS Product Name"
 485         depends on GENERATE_SMBIOS_TABLE
 486         default SYS_BOARD
 487         help
 488           The product name to store in SMBIOS structures.
 489           Change this to override the default one (CONFIG_SYS_BOARD).
 490
 491 endmenu
 492
 493 config MAX_PIRQ_LINKS
 494         int
 495         default 8
 496         help
 497           This variable specifies the number of PIRQ interrupt links which are
 498           routable. On most older chipsets, this is 4, PIRQA through PIRQD.
 499           Some newer chipsets offer more than four links, commonly up to PIRQH.
 500
 501 config IRQ_SLOT_COUNT
 502         int
 503         default 128
 504         help
 505           U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
 506           which in turns forms a table of exact 4KiB. The default value 128
 507           should be enough for most boards. If this does not fit your board,
 508           change it according to your needs.
 509
 510 config PCIE_ECAM_BASE
 511         hex
 512         default 0xe0000000
 513         help
 514           This is the memory-mapped address of PCI configuration space, which
 515           is only available through the Enhanced Configuration Access
 516           Mechanism (ECAM) with PCI Express. It can be set up almost
 517           anywhere. Before it is set up, it is possible to access PCI
 518           configuration space through I/O access, but memory access is more
 519           convenient. Using this, PCI can be scanned and configured. This
 520           should be set to a region that does not conflict with memory
 521           assigned to PCI devices - i.e. the memory and prefetch regions, as
 522           passed to pci_set_region().
 523
 524 config PCIE_ECAM_SIZE
 525         hex
 526         default 0x10000000
 527         help
 528           This is the size of memory-mapped address of PCI configuration space,
 529           which is only available through the Enhanced Configuration Access
 530           Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
 531           so a default 0x10000000 size covers all of the 256 buses which is the
 532           maximum number of PCI buses as defined by the PCI specification.
 533
 534 config I8259_PIC
 535         bool
 536         default y
 537         help
 538           Intel 8259 ISA compatible chipset incorporates two 8259 (master and
 539           slave) interrupt controllers. Include this to have U-Boot set up
 540           the interrupt correctly.
 541
 542 config I8254_TIMER
 543         bool
 544         default y
 545         help
 546           Intel 8254 timer contains three counters which have fixed uses.
 547           Include this to have U-Boot set up the timer correctly.
 548
 549 config I8042_KEYB
 550         default y
 551
 552 config DM_KEYBOARD
 553         default y
 554
 555 config SEABIOS
 556         bool "Support booting SeaBIOS"
 557         help
 558           SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
 559           It can run in an emulator or natively on X86 hardware with the use
 560           of coreboot/U-Boot. By turning on this option, U-Boot prepares
 561           all the configuration tables that are necessary to boot SeaBIOS.
 562
 563           Check http://www.seabios.org/SeaBIOS for details.
 564
 565 config HIGH_TABLE_SIZE
 566         hex "Size of configuration tables which reside in high memory"
 567         default 0x10000
 568         depends on SEABIOS
 569         help
 570           SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
 571           configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
 572           puts a copy of configuration tables in high memory region which
 573           is reserved on the stack before relocation. The region size is
 574           determined by this option.
 575
 576           Increse it if the default size does not fit the board's needs.
 577           This is most likely due to a large ACPI DSDT table is used.
 578
 579 source "arch/x86/lib/efi/Kconfig"
 580
 581 endmenu