3 * Copyright (C) 2008-2009 coresystems GmbH
5 * SPDX-License-Identifier: GPL-2.0
12 #include <asm/pch_common.h>
14 #include <asm/arch/pch.h>
16 DECLARE_GLOBAL_DATA_PTR
;
18 static void common_sata_init(struct udevice
*dev
, unsigned int port_map
)
23 /* Set IDE I/O Configuration */
24 reg32
= SIG_MODE_PRI_NORMAL
| FAST_PCB1
| FAST_PCB0
| PCB1
| PCB0
;
25 dm_pci_write_config32(dev
, IDE_CONFIG
, reg32
);
28 dm_pci_read_config16(dev
, 0x92, ®16
);
31 dm_pci_write_config16(dev
, 0x92, reg16
);
33 /* SATA Initialization register */
35 dm_pci_write_config32(dev
, 0x94, ((port_map
^ 0x3f) << 24) | 0x183);
38 static void bd82x6x_sata_init(struct udevice
*dev
, struct udevice
*pch
)
40 unsigned int port_map
, speed_support
, port_tx
;
41 const void *blob
= gd
->fdt_blob
;
42 int node
= dev_of_offset(dev
);
47 debug("SATA: Initializing...\n");
49 /* SATA configuration */
50 port_map
= fdtdec_get_int(blob
, node
, "intel,sata-port-map", 0);
51 speed_support
= fdtdec_get_int(blob
, node
,
52 "sata_interface_speed_support", 0);
54 mode
= fdt_getprop(blob
, node
, "intel,sata-mode", NULL
);
55 if (!mode
|| !strcmp(mode
, "ahci")) {
58 debug("SATA: Controller in AHCI mode\n");
61 dm_pci_write_config16(dev
, IDE_TIM_PRI
, IDE_DECODE_ENABLE
|
62 IDE_ISP_3_CLOCKS
| IDE_RCT_1_CLOCKS
|
63 IDE_PPE0
| IDE_IE0
| IDE_TIME0
);
64 dm_pci_write_config16(dev
, IDE_TIM_SEC
, IDE_DECODE_ENABLE
|
65 IDE_ISP_5_CLOCKS
| IDE_RCT_4_CLOCKS
);
68 dm_pci_write_config16(dev
, IDE_SDMA_CNT
, IDE_PSDE0
);
69 dm_pci_write_config16(dev
, IDE_SDMA_TIM
, 0x0001);
71 common_sata_init(dev
, 0x8000 | port_map
);
73 /* Initialize AHCI memory-mapped space */
74 abar
= dm_pci_read_bar32(dev
, 5);
75 debug("ABAR: %08lx\n", abar
);
76 /* CAP (HBA Capabilities) : enable power management */
77 reg32
= readl(abar
+ 0x00);
78 reg32
|= 0x0c006000; /* set PSC+SSC+SALP+SSS */
79 reg32
&= ~0x00020060; /* clear SXS+EMS+PMS */
80 /* Set ISS, if available */
83 reg32
|= (speed_support
& 0x03) << 20;
85 writel(reg32
, abar
+ 0x00);
86 /* PI (Ports implemented) */
87 writel(port_map
, abar
+ 0x0c);
88 (void) readl(abar
+ 0x0c); /* Read back 1 */
89 (void) readl(abar
+ 0x0c); /* Read back 2 */
90 /* CAP2 (HBA Capabilities Extended)*/
91 reg32
= readl(abar
+ 0x24);
93 writel(reg32
, abar
+ 0x24);
94 /* VSP (Vendor Specific Register */
95 reg32
= readl(abar
+ 0xa0);
97 writel(reg32
, abar
+ 0xa0);
98 } else if (!strcmp(mode
, "combined")) {
99 debug("SATA: Controller in combined mode\n");
101 /* No AHCI: clear AHCI base */
102 dm_pci_write_bar32(dev
, 5, 0x00000000);
103 /* And without AHCI BAR no memory decoding */
104 dm_pci_read_config16(dev
, PCI_COMMAND
, ®16
);
105 reg16
&= ~PCI_COMMAND_MEMORY
;
106 dm_pci_write_config16(dev
, PCI_COMMAND
, reg16
);
108 dm_pci_write_config8(dev
, 0x09, 0x80);
111 dm_pci_write_config16(dev
, IDE_TIM_PRI
, IDE_DECODE_ENABLE
|
112 IDE_ISP_5_CLOCKS
| IDE_RCT_4_CLOCKS
);
113 dm_pci_write_config16(dev
, IDE_TIM_SEC
, IDE_DECODE_ENABLE
|
114 IDE_ISP_3_CLOCKS
| IDE_RCT_1_CLOCKS
|
115 IDE_PPE0
| IDE_IE0
| IDE_TIME0
);
118 dm_pci_write_config16(dev
, IDE_SDMA_CNT
, IDE_SSDE0
);
119 dm_pci_write_config16(dev
, IDE_SDMA_TIM
, 0x0200);
121 common_sata_init(dev
, port_map
);
123 debug("SATA: Controller in plain-ide mode\n");
125 /* No AHCI: clear AHCI base */
126 dm_pci_write_bar32(dev
, 5, 0x00000000);
128 /* And without AHCI BAR no memory decoding */
129 dm_pci_read_config16(dev
, PCI_COMMAND
, ®16
);
130 reg16
&= ~PCI_COMMAND_MEMORY
;
131 dm_pci_write_config16(dev
, PCI_COMMAND
, reg16
);
134 * Native mode capable on both primary and secondary (0xa)
135 * OR'ed with enabled (0x50) = 0xf
137 dm_pci_write_config8(dev
, 0x09, 0x8f);
140 dm_pci_write_config16(dev
, IDE_TIM_PRI
, IDE_DECODE_ENABLE
|
141 IDE_ISP_3_CLOCKS
| IDE_RCT_1_CLOCKS
|
142 IDE_PPE0
| IDE_IE0
| IDE_TIME0
);
143 dm_pci_write_config16(dev
, IDE_TIM_SEC
, IDE_DECODE_ENABLE
|
144 IDE_SITRE
| IDE_ISP_3_CLOCKS
|
145 IDE_RCT_1_CLOCKS
| IDE_IE0
| IDE_TIME0
);
148 dm_pci_write_config16(dev
, IDE_SDMA_CNT
, IDE_SSDE0
| IDE_PSDE0
);
149 dm_pci_write_config16(dev
, IDE_SDMA_TIM
, 0x0201);
151 common_sata_init(dev
, port_map
);
154 /* Set Gen3 Transmitter settings if needed */
155 port_tx
= fdtdec_get_int(blob
, node
, "intel,sata-port0-gen3-tx", 0);
157 pch_iobp_update(pch
, SATA_IOBP_SP0G3IR
, 0, port_tx
);
159 port_tx
= fdtdec_get_int(blob
, node
, "intel,sata-port1-gen3-tx", 0);
161 pch_iobp_update(pch
, SATA_IOBP_SP1G3IR
, 0, port_tx
);
163 /* Additional Programming Requirements */
164 pch_common_sir_write(dev
, 0x04, 0x00001600);
165 pch_common_sir_write(dev
, 0x28, 0xa0000033);
166 reg32
= pch_common_sir_read(dev
, 0x54);
169 pch_common_sir_write(dev
, 0x54, reg32
);
170 pch_common_sir_write(dev
, 0x64, 0xcccc8484);
171 reg32
= pch_common_sir_read(dev
, 0x68);
174 pch_common_sir_write(dev
, 0x68, reg32
);
175 reg32
= pch_common_sir_read(dev
, 0x78);
178 pch_common_sir_write(dev
, 0x78, reg32
);
179 pch_common_sir_write(dev
, 0x84, 0x001c7000);
180 pch_common_sir_write(dev
, 0x88, 0x88338822);
181 pch_common_sir_write(dev
, 0xa0, 0x001c7000);
182 pch_common_sir_write(dev
, 0xc4, 0x0c0c0c0c);
183 pch_common_sir_write(dev
, 0xc8, 0x0c0c0c0c);
184 pch_common_sir_write(dev
, 0xd4, 0x10000000);
186 pch_iobp_update(pch
, 0xea004001, 0x3fffffff, 0xc0000000);
187 pch_iobp_update(pch
, 0xea00408a, 0xfffffcff, 0x00000100);
190 static void bd82x6x_sata_enable(struct udevice
*dev
)
192 const void *blob
= gd
->fdt_blob
;
193 int node
= dev_of_offset(dev
);
199 * Set SATA controller mode early so the resource allocator can
200 * properly assign IO/Memory resources for the controller.
202 mode
= fdt_getprop(blob
, node
, "intel,sata-mode", NULL
);
203 if (mode
&& !strcmp(mode
, "ahci"))
205 port_map
= fdtdec_get_int(blob
, node
, "intel,sata-port-map", 0);
207 map
|= (port_map
^ 0x3f) << 8;
208 dm_pci_write_config16(dev
, 0x90, map
);
211 static int bd82x6x_sata_probe(struct udevice
*dev
)
216 ret
= uclass_first_device_err(UCLASS_PCH
, &pch
);
220 if (!(gd
->flags
& GD_FLG_RELOC
))
221 bd82x6x_sata_enable(dev
);
223 bd82x6x_sata_init(dev
, pch
);
228 static const struct udevice_id bd82x6x_ahci_ids
[] = {
229 { .compatible
= "intel,pantherpoint-ahci" },
233 U_BOOT_DRIVER(ahci_ivybridge_drv
) = {
234 .name
= "ahci_ivybridge",
236 .of_match
= bd82x6x_ahci_ids
,
237 .probe
= bd82x6x_sata_probe
,