1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2020 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
97 .typedef const struct reloc_howto_struct reloc_howto_type;
99 .typedef struct reloc_cache_entry
101 . {* A pointer into the canonical table of pointers. *}
102 . struct bfd_symbol **sym_ptr_ptr;
104 . {* offset in section. *}
105 . bfd_size_type address;
107 . {* addend for relocation value. *}
110 . {* Pointer to how to perform the required relocation. *}
111 . reloc_howto_type *howto;
121 Here is a description of each of the fields within an <<arelent>>:
125 The symbol table pointer points to a pointer to the symbol
126 associated with the relocation request. It is the pointer
127 into the table returned by the back end's
128 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
129 referenced through a pointer to a pointer so that tools like
130 the linker can fix up all the symbols of the same name by
131 modifying only one pointer. The relocation routine looks in
132 the symbol and uses the base of the section the symbol is
133 attached to and the value of the symbol as the initial
134 relocation offset. If the symbol pointer is zero, then the
135 section provided is looked up.
139 The <<address>> field gives the offset in bytes from the base of
140 the section data which owns the relocation record to the first
141 byte of relocatable information. The actual data relocated
142 will be relative to this point; for example, a relocation
143 type which modifies the bottom two bytes of a four byte word
144 would not touch the first byte pointed to in a big endian
149 The <<addend>> is a value provided by the back end to be added (!)
150 to the relocation offset. Its interpretation is dependent upon
151 the howto. For example, on the 68k the code:
156 | return foo[0x12345678];
159 Could be compiled into:
162 | moveb @@#12345678,d0
167 This could create a reloc pointing to <<foo>>, but leave the
168 offset in the data, something like:
170 |RELOCATION RECORDS FOR [.text]:
174 |00000000 4e56 fffc ; linkw fp,#-4
175 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
176 |0000000a 49c0 ; extbl d0
177 |0000000c 4e5e ; unlk fp
180 Using coff and an 88k, some instructions don't have enough
181 space in them to represent the full address range, and
182 pointers have to be loaded in two parts. So you'd get something like:
184 | or.u r13,r0,hi16(_foo+0x12345678)
185 | ld.b r2,r13,lo16(_foo+0x12345678)
188 This should create two relocs, both pointing to <<_foo>>, and with
189 0x12340000 in their addend field. The data would consist of:
191 |RELOCATION RECORDS FOR [.text]:
193 |00000002 HVRT16 _foo+0x12340000
194 |00000006 LVRT16 _foo+0x12340000
196 |00000000 5da05678 ; or.u r13,r0,0x5678
197 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
198 |00000008 f400c001 ; jmp r1
200 The relocation routine digs out the value from the data, adds
201 it to the addend to get the original offset, and then adds the
202 value of <<_foo>>. Note that all 32 bits have to be kept around
203 somewhere, to cope with carry from bit 15 to bit 16.
205 One further example is the sparc and the a.out format. The
206 sparc has a similar problem to the 88k, in that some
207 instructions don't have room for an entire offset, but on the
208 sparc the parts are created in odd sized lumps. The designers of
209 the a.out format chose to not use the data within the section
210 for storing part of the offset; all the offset is kept within
211 the reloc. Anything in the data should be ignored.
214 | sethi %hi(_foo+0x12345678),%g2
215 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
219 Both relocs contain a pointer to <<foo>>, and the offsets
222 |RELOCATION RECORDS FOR [.text]:
224 |00000004 HI22 _foo+0x12345678
225 |00000008 LO10 _foo+0x12345678
227 |00000000 9de3bf90 ; save %sp,-112,%sp
228 |00000004 05000000 ; sethi %hi(_foo+0),%g2
229 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
230 |0000000c 81c7e008 ; ret
231 |00000010 81e80000 ; restore
235 The <<howto>> field can be imagined as a
236 relocation instruction. It is a pointer to a structure which
237 contains information on what to do with all of the other
238 information in the reloc record and data section. A back end
239 would normally have a relocation instruction set and turn
240 relocations into pointers to the correct structure on input -
241 but it would be possible to create each howto field on demand.
247 <<enum complain_overflow>>
249 Indicates what sort of overflow checking should be done when
250 performing a relocation.
254 .enum complain_overflow
256 . {* Do not complain on overflow. *}
257 . complain_overflow_dont,
259 . {* Complain if the value overflows when considered as a signed
260 . number one bit larger than the field. ie. A bitfield of N bits
261 . is allowed to represent -2**n to 2**n-1. *}
262 . complain_overflow_bitfield,
264 . {* Complain if the value overflows when considered as a signed
266 . complain_overflow_signed,
268 . {* Complain if the value overflows when considered as an
269 . unsigned number. *}
270 . complain_overflow_unsigned
279 The <<reloc_howto_type>> is a structure which contains all the
280 information that libbfd needs to know to tie up a back end's data.
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's idea of
287 . an external reloc number is stored in this field. *}
290 . {* The encoded size of the item to be relocated. This is *not* a
291 . power-of-two measure. Use bfd_get_reloc_size to find the size
292 . of the item in bytes. *}
293 . unsigned int size:3;
295 . {* The number of bits in the field to be relocated. This is used
296 . when doing overflow checking. *}
297 . unsigned int bitsize:7;
299 . {* The value the final relocation is shifted right by. This drops
300 . unwanted data from the relocation. *}
301 . unsigned int rightshift:6;
303 . {* The bit position of the reloc value in the destination.
304 . The relocated value is left shifted by this amount. *}
305 . unsigned int bitpos:6;
307 . {* What type of overflow error should be checked for when
309 . ENUM_BITFIELD (complain_overflow) complain_on_overflow:2;
311 . {* The relocation value should be negated before applying. *}
312 . unsigned int negate:1;
314 . {* The relocation is relative to the item being relocated. *}
315 . unsigned int pc_relative:1;
317 . {* Some formats record a relocation addend in the section contents
318 . rather than with the relocation. For ELF formats this is the
319 . distinction between USE_REL and USE_RELA (though the code checks
320 . for USE_REL == 1/0). The value of this field is TRUE if the
321 . addend is recorded with the section contents; when performing a
322 . partial link (ld -r) the section contents (the data) will be
323 . modified. The value of this field is FALSE if addends are
324 . recorded with the relocation (in arelent.addend); when performing
325 . a partial link the relocation will be modified.
326 . All relocations for all ELF USE_RELA targets should set this field
327 . to FALSE (values of TRUE should be looked on with suspicion).
328 . However, the converse is not true: not all relocations of all ELF
329 . USE_REL targets set this field to TRUE. Why this is so is peculiar
330 . to each particular target. For relocs that aren't used in partial
331 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
332 . unsigned int partial_inplace:1;
334 . {* When some formats create PC relative instructions, they leave
335 . the value of the pc of the place being relocated in the offset
336 . slot of the instruction, so that a PC relative relocation can
337 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
338 . Some formats leave the displacement part of an instruction
339 . empty (e.g., ELF); this flag signals the fact. *}
340 . unsigned int pcrel_offset:1;
342 . {* src_mask selects the part of the instruction (or data) to be used
343 . in the relocation sum. If the target relocations don't have an
344 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
345 . dst_mask to extract the addend from the section contents. If
346 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
347 . field should normally be zero. Non-zero values for ELF USE_RELA
348 . targets should be viewed with suspicion as normally the value in
349 . the dst_mask part of the section contents should be ignored. *}
352 . {* dst_mask selects which parts of the instruction (or data) are
353 . replaced with a relocated value. *}
356 . {* If this field is non null, then the supplied function is
357 . called rather than the normal function. This allows really
358 . strange relocation methods to be accommodated. *}
359 . bfd_reloc_status_type (*special_function)
360 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
363 . {* The textual name of the relocation type. *}
374 The HOWTO macro fills in a reloc_howto_type (a typedef for
375 const struct reloc_howto_struct).
377 .#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \
378 . inplace, src_mask, dst_mask, pcrel_off) \
379 . { (unsigned) type, size < 0 ? -size : size, bits, right, left, ovf, \
380 . size < 0, pcrel, inplace, pcrel_off, src_mask, dst_mask, func, name }
383 This is used to fill in an empty howto entry in an array.
385 .#define EMPTY_HOWTO(C) \
386 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
387 . NULL, FALSE, 0, 0, FALSE)
396 unsigned int bfd_get_reloc_size (reloc_howto_type *);
399 For a reloc_howto_type that operates on a fixed number of bytes,
400 this returns the number of bytes operated on.
404 bfd_get_reloc_size (reloc_howto_type
*howto
)
424 How relocs are tied together in an <<asection>>:
426 .typedef struct relent_chain
429 . struct relent_chain *next;
435 /* N_ONES produces N one bits, without undefined behaviour for N
436 between zero and the number of bits in a bfd_vma. */
437 #define N_ONES(n) ((n) == 0 ? 0 : ((bfd_vma) 1 << ((n) - 1) << 1) - 1)
444 bfd_reloc_status_type bfd_check_overflow
445 (enum complain_overflow how,
446 unsigned int bitsize,
447 unsigned int rightshift,
448 unsigned int addrsize,
452 Perform overflow checking on @var{relocation} which has
453 @var{bitsize} significant bits and will be shifted right by
454 @var{rightshift} bits, on a machine with addresses containing
455 @var{addrsize} significant bits. The result is either of
456 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
460 bfd_reloc_status_type
461 bfd_check_overflow (enum complain_overflow how
,
462 unsigned int bitsize
,
463 unsigned int rightshift
,
464 unsigned int addrsize
,
467 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
468 bfd_reloc_status_type flag
= bfd_reloc_ok
;
473 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
474 we'll be permissive: extra bits in the field mask will
475 automatically extend the address mask for purposes of the
477 fieldmask
= N_ONES (bitsize
);
478 signmask
= ~fieldmask
;
479 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
480 a
= (relocation
& addrmask
) >> rightshift
;
484 case complain_overflow_dont
:
487 case complain_overflow_signed
:
488 /* If any sign bits are set, all sign bits must be set. That
489 is, A must be a valid negative address after shifting. */
490 signmask
= ~ (fieldmask
>> 1);
493 case complain_overflow_bitfield
:
494 /* Bitfields are sometimes signed, sometimes unsigned. We
495 explicitly allow an address wrap too, which means a bitfield
496 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
497 if the value has some, but not all, bits set outside the
500 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
501 flag
= bfd_reloc_overflow
;
504 case complain_overflow_unsigned
:
505 /* We have an overflow if the address does not fit in the field. */
506 if ((a
& signmask
) != 0)
507 flag
= bfd_reloc_overflow
;
519 bfd_reloc_offset_in_range
522 bfd_boolean bfd_reloc_offset_in_range
523 (reloc_howto_type *howto,
526 bfd_size_type offset);
529 Returns TRUE if the reloc described by @var{HOWTO} can be
530 applied at @var{OFFSET} octets in @var{SECTION}.
534 /* HOWTO describes a relocation, at offset OCTET. Return whether the
535 relocation field is within SECTION of ABFD. */
538 bfd_reloc_offset_in_range (reloc_howto_type
*howto
,
543 bfd_size_type octet_end
= bfd_get_section_limit_octets (abfd
, section
);
544 bfd_size_type reloc_size
= bfd_get_reloc_size (howto
);
546 /* The reloc field must be contained entirely within the section.
547 Allow zero length fields (marker relocs or NONE relocs where no
548 relocation will be performed) at the end of the section. */
549 return octet
<= octet_end
&& octet
+ reloc_size
<= octet_end
;
552 /* Read and return the section contents at DATA converted to a host
553 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
556 read_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
)
561 return bfd_get_8 (abfd
, data
);
564 return bfd_get_16 (abfd
, data
);
567 return bfd_get_32 (abfd
, data
);
574 return bfd_get_64 (abfd
, data
);
578 return bfd_get_24 (abfd
, data
);
586 /* Convert VAL to target format and write to DATA. The number of
587 bytes written is given by the HOWTO. */
590 write_reloc (bfd
*abfd
, bfd_vma val
, bfd_byte
*data
, reloc_howto_type
*howto
)
595 bfd_put_8 (abfd
, val
, data
);
599 bfd_put_16 (abfd
, val
, data
);
603 bfd_put_32 (abfd
, val
, data
);
611 bfd_put_64 (abfd
, val
, data
);
616 bfd_put_24 (abfd
, val
, data
);
624 /* Apply RELOCATION value to target bytes at DATA, according to
628 apply_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
,
631 bfd_vma val
= read_reloc (abfd
, data
, howto
);
634 relocation
= -relocation
;
636 val
= ((val
& ~howto
->dst_mask
)
637 | (((val
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
639 write_reloc (abfd
, val
, data
, howto
);
644 bfd_perform_relocation
647 bfd_reloc_status_type bfd_perform_relocation
649 arelent *reloc_entry,
651 asection *input_section,
653 char **error_message);
656 If @var{output_bfd} is supplied to this function, the
657 generated image will be relocatable; the relocations are
658 copied to the output file after they have been changed to
659 reflect the new state of the world. There are two ways of
660 reflecting the results of partial linkage in an output file:
661 by modifying the output data in place, and by modifying the
662 relocation record. Some native formats (e.g., basic a.out and
663 basic coff) have no way of specifying an addend in the
664 relocation type, so the addend has to go in the output data.
665 This is no big deal since in these formats the output data
666 slot will always be big enough for the addend. Complex reloc
667 types with addends were invented to solve just this problem.
668 The @var{error_message} argument is set to an error message if
669 this return @code{bfd_reloc_dangerous}.
673 bfd_reloc_status_type
674 bfd_perform_relocation (bfd
*abfd
,
675 arelent
*reloc_entry
,
677 asection
*input_section
,
679 char **error_message
)
682 bfd_reloc_status_type flag
= bfd_reloc_ok
;
683 bfd_size_type octets
;
684 bfd_vma output_base
= 0;
685 reloc_howto_type
*howto
= reloc_entry
->howto
;
686 asection
*reloc_target_output_section
;
689 symbol
= *(reloc_entry
->sym_ptr_ptr
);
691 /* If we are not producing relocatable output, return an error if
692 the symbol is not defined. An undefined weak symbol is
693 considered to have a value of zero (SVR4 ABI, p. 4-27). */
694 if (bfd_is_und_section (symbol
->section
)
695 && (symbol
->flags
& BSF_WEAK
) == 0
696 && output_bfd
== NULL
)
697 flag
= bfd_reloc_undefined
;
699 /* If there is a function supplied to handle this relocation type,
700 call it. It'll return `bfd_reloc_continue' if further processing
702 if (howto
&& howto
->special_function
)
704 bfd_reloc_status_type cont
;
706 /* Note - we do not call bfd_reloc_offset_in_range here as the
707 reloc_entry->address field might actually be valid for the
708 backend concerned. It is up to the special_function itself
709 to call bfd_reloc_offset_in_range if needed. */
710 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
711 input_section
, output_bfd
,
713 if (cont
!= bfd_reloc_continue
)
717 if (bfd_is_abs_section (symbol
->section
)
718 && output_bfd
!= NULL
)
720 reloc_entry
->address
+= input_section
->output_offset
;
724 /* PR 17512: file: 0f67f69d. */
726 return bfd_reloc_undefined
;
728 /* Is the address of the relocation really within the section? */
729 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
730 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
731 return bfd_reloc_outofrange
;
733 /* Work out which section the relocation is targeted at and the
734 initial relocation command value. */
736 /* Get symbol value. (Common symbols are special.) */
737 if (bfd_is_com_section (symbol
->section
))
740 relocation
= symbol
->value
;
742 reloc_target_output_section
= symbol
->section
->output_section
;
744 /* Convert input-section-relative symbol value to absolute. */
745 if ((output_bfd
&& ! howto
->partial_inplace
)
746 || reloc_target_output_section
== NULL
)
749 output_base
= reloc_target_output_section
->vma
;
751 output_base
+= symbol
->section
->output_offset
;
753 /* If symbol addresses are in octets, convert to bytes. */
754 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
755 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
756 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
758 relocation
+= output_base
;
760 /* Add in supplied addend. */
761 relocation
+= reloc_entry
->addend
;
763 /* Here the variable relocation holds the final address of the
764 symbol we are relocating against, plus any addend. */
766 if (howto
->pc_relative
)
768 /* This is a PC relative relocation. We want to set RELOCATION
769 to the distance between the address of the symbol and the
770 location. RELOCATION is already the address of the symbol.
772 We start by subtracting the address of the section containing
775 If pcrel_offset is set, we must further subtract the position
776 of the location within the section. Some targets arrange for
777 the addend to be the negative of the position of the location
778 within the section; for example, i386-aout does this. For
779 i386-aout, pcrel_offset is FALSE. Some other targets do not
780 include the position of the location; for example, ELF.
781 For those targets, pcrel_offset is TRUE.
783 If we are producing relocatable output, then we must ensure
784 that this reloc will be correctly computed when the final
785 relocation is done. If pcrel_offset is FALSE we want to wind
786 up with the negative of the location within the section,
787 which means we must adjust the existing addend by the change
788 in the location within the section. If pcrel_offset is TRUE
789 we do not want to adjust the existing addend at all.
791 FIXME: This seems logical to me, but for the case of
792 producing relocatable output it is not what the code
793 actually does. I don't want to change it, because it seems
794 far too likely that something will break. */
797 input_section
->output_section
->vma
+ input_section
->output_offset
;
799 if (howto
->pcrel_offset
)
800 relocation
-= reloc_entry
->address
;
803 if (output_bfd
!= NULL
)
805 if (! howto
->partial_inplace
)
807 /* This is a partial relocation, and we want to apply the relocation
808 to the reloc entry rather than the raw data. Modify the reloc
809 inplace to reflect what we now know. */
810 reloc_entry
->addend
= relocation
;
811 reloc_entry
->address
+= input_section
->output_offset
;
816 /* This is a partial relocation, but inplace, so modify the
819 If we've relocated with a symbol with a section, change
820 into a ref to the section belonging to the symbol. */
822 reloc_entry
->address
+= input_section
->output_offset
;
825 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
826 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
827 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
829 /* For m68k-coff, the addend was being subtracted twice during
830 relocation with -r. Removing the line below this comment
831 fixes that problem; see PR 2953.
833 However, Ian wrote the following, regarding removing the line below,
834 which explains why it is still enabled: --djm
836 If you put a patch like that into BFD you need to check all the COFF
837 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
838 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
839 problem in a different way. There may very well be a reason that the
840 code works as it does.
842 Hmmm. The first obvious point is that bfd_perform_relocation should
843 not have any tests that depend upon the flavour. It's seem like
844 entirely the wrong place for such a thing. The second obvious point
845 is that the current code ignores the reloc addend when producing
846 relocatable output for COFF. That's peculiar. In fact, I really
847 have no idea what the point of the line you want to remove is.
849 A typical COFF reloc subtracts the old value of the symbol and adds in
850 the new value to the location in the object file (if it's a pc
851 relative reloc it adds the difference between the symbol value and the
852 location). When relocating we need to preserve that property.
854 BFD handles this by setting the addend to the negative of the old
855 value of the symbol. Unfortunately it handles common symbols in a
856 non-standard way (it doesn't subtract the old value) but that's a
857 different story (we can't change it without losing backward
858 compatibility with old object files) (coff-i386 does subtract the old
859 value, to be compatible with existing coff-i386 targets, like SCO).
861 So everything works fine when not producing relocatable output. When
862 we are producing relocatable output, logically we should do exactly
863 what we do when not producing relocatable output. Therefore, your
864 patch is correct. In fact, it should probably always just set
865 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
866 add the value into the object file. This won't hurt the COFF code,
867 which doesn't use the addend; I'm not sure what it will do to other
868 formats (the thing to check for would be whether any formats both use
869 the addend and set partial_inplace).
871 When I wanted to make coff-i386 produce relocatable output, I ran
872 into the problem that you are running into: I wanted to remove that
873 line. Rather than risk it, I made the coff-i386 relocs use a special
874 function; it's coff_i386_reloc in coff-i386.c. The function
875 specifically adds the addend field into the object file, knowing that
876 bfd_perform_relocation is not going to. If you remove that line, then
877 coff-i386.c will wind up adding the addend field in twice. It's
878 trivial to fix; it just needs to be done.
880 The problem with removing the line is just that it may break some
881 working code. With BFD it's hard to be sure of anything. The right
882 way to deal with this is simply to build and test at least all the
883 supported COFF targets. It should be straightforward if time and disk
884 space consuming. For each target:
886 2) generate some executable, and link it using -r (I would
887 probably use paranoia.o and link against newlib/libc.a, which
888 for all the supported targets would be available in
889 /usr/cygnus/progressive/H-host/target/lib/libc.a).
890 3) make the change to reloc.c
891 4) rebuild the linker
893 6) if the resulting object files are the same, you have at least
895 7) if they are different you have to figure out which version is
898 relocation
-= reloc_entry
->addend
;
899 reloc_entry
->addend
= 0;
903 reloc_entry
->addend
= relocation
;
908 /* FIXME: This overflow checking is incomplete, because the value
909 might have overflowed before we get here. For a correct check we
910 need to compute the value in a size larger than bitsize, but we
911 can't reasonably do that for a reloc the same size as a host
913 FIXME: We should also do overflow checking on the result after
914 adding in the value contained in the object file. */
915 if (howto
->complain_on_overflow
!= complain_overflow_dont
916 && flag
== bfd_reloc_ok
)
917 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
920 bfd_arch_bits_per_address (abfd
),
923 /* Either we are relocating all the way, or we don't want to apply
924 the relocation to the reloc entry (probably because there isn't
925 any room in the output format to describe addends to relocs). */
927 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
928 (OSF version 1.3, compiler version 3.11). It miscompiles the
942 x <<= (unsigned long) s.i0;
946 printf ("succeeded (%lx)\n", x);
950 relocation
>>= (bfd_vma
) howto
->rightshift
;
952 /* Shift everything up to where it's going to be used. */
953 relocation
<<= (bfd_vma
) howto
->bitpos
;
955 /* Wait for the day when all have the mask in them. */
958 i instruction to be left alone
959 o offset within instruction
960 r relocation offset to apply
969 (( i i i i i o o o o o from bfd_get<size>
970 and S S S S S) to get the size offset we want
971 + r r r r r r r r r r) to get the final value to place
972 and D D D D D to chop to right size
973 -----------------------
976 ( i i i i i o o o o o from bfd_get<size>
977 and N N N N N ) get instruction
978 -----------------------
984 -----------------------
985 = R R R R R R R R R R put into bfd_put<size>
988 data
= (bfd_byte
*) data
+ octets
;
989 apply_reloc (abfd
, data
, howto
, relocation
);
995 bfd_install_relocation
998 bfd_reloc_status_type bfd_install_relocation
1000 arelent *reloc_entry,
1001 void *data, bfd_vma data_start,
1002 asection *input_section,
1003 char **error_message);
1006 This looks remarkably like <<bfd_perform_relocation>>, except it
1007 does not expect that the section contents have been filled in.
1008 I.e., it's suitable for use when creating, rather than applying
1011 For now, this function should be considered reserved for the
1015 bfd_reloc_status_type
1016 bfd_install_relocation (bfd
*abfd
,
1017 arelent
*reloc_entry
,
1019 bfd_vma data_start_offset
,
1020 asection
*input_section
,
1021 char **error_message
)
1024 bfd_reloc_status_type flag
= bfd_reloc_ok
;
1025 bfd_size_type octets
;
1026 bfd_vma output_base
= 0;
1027 reloc_howto_type
*howto
= reloc_entry
->howto
;
1028 asection
*reloc_target_output_section
;
1032 symbol
= *(reloc_entry
->sym_ptr_ptr
);
1034 /* If there is a function supplied to handle this relocation type,
1035 call it. It'll return `bfd_reloc_continue' if further processing
1037 if (howto
&& howto
->special_function
)
1039 bfd_reloc_status_type cont
;
1041 /* Note - we do not call bfd_reloc_offset_in_range here as the
1042 reloc_entry->address field might actually be valid for the
1043 backend concerned. It is up to the special_function itself
1044 to call bfd_reloc_offset_in_range if needed. */
1045 /* XXX - The special_function calls haven't been fixed up to deal
1046 with creating new relocations and section contents. */
1047 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1048 /* XXX - Non-portable! */
1049 ((bfd_byte
*) data_start
1050 - data_start_offset
),
1051 input_section
, abfd
, error_message
);
1052 if (cont
!= bfd_reloc_continue
)
1056 if (bfd_is_abs_section (symbol
->section
))
1058 reloc_entry
->address
+= input_section
->output_offset
;
1059 return bfd_reloc_ok
;
1062 /* No need to check for howto != NULL if !bfd_is_abs_section as
1063 it will have been checked in `bfd_perform_relocation already'. */
1065 /* Is the address of the relocation really within the section? */
1066 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
1067 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
1068 return bfd_reloc_outofrange
;
1070 /* Work out which section the relocation is targeted at and the
1071 initial relocation command value. */
1073 /* Get symbol value. (Common symbols are special.) */
1074 if (bfd_is_com_section (symbol
->section
))
1077 relocation
= symbol
->value
;
1079 reloc_target_output_section
= symbol
->section
->output_section
;
1081 /* Convert input-section-relative symbol value to absolute. */
1082 if (! howto
->partial_inplace
)
1085 output_base
= reloc_target_output_section
->vma
;
1087 output_base
+= symbol
->section
->output_offset
;
1089 /* If symbol addresses are in octets, convert to bytes. */
1090 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
1091 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
1092 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
1094 relocation
+= output_base
;
1096 /* Add in supplied addend. */
1097 relocation
+= reloc_entry
->addend
;
1099 /* Here the variable relocation holds the final address of the
1100 symbol we are relocating against, plus any addend. */
1102 if (howto
->pc_relative
)
1104 /* This is a PC relative relocation. We want to set RELOCATION
1105 to the distance between the address of the symbol and the
1106 location. RELOCATION is already the address of the symbol.
1108 We start by subtracting the address of the section containing
1111 If pcrel_offset is set, we must further subtract the position
1112 of the location within the section. Some targets arrange for
1113 the addend to be the negative of the position of the location
1114 within the section; for example, i386-aout does this. For
1115 i386-aout, pcrel_offset is FALSE. Some other targets do not
1116 include the position of the location; for example, ELF.
1117 For those targets, pcrel_offset is TRUE.
1119 If we are producing relocatable output, then we must ensure
1120 that this reloc will be correctly computed when the final
1121 relocation is done. If pcrel_offset is FALSE we want to wind
1122 up with the negative of the location within the section,
1123 which means we must adjust the existing addend by the change
1124 in the location within the section. If pcrel_offset is TRUE
1125 we do not want to adjust the existing addend at all.
1127 FIXME: This seems logical to me, but for the case of
1128 producing relocatable output it is not what the code
1129 actually does. I don't want to change it, because it seems
1130 far too likely that something will break. */
1133 input_section
->output_section
->vma
+ input_section
->output_offset
;
1135 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1136 relocation
-= reloc_entry
->address
;
1139 if (! howto
->partial_inplace
)
1141 /* This is a partial relocation, and we want to apply the relocation
1142 to the reloc entry rather than the raw data. Modify the reloc
1143 inplace to reflect what we now know. */
1144 reloc_entry
->addend
= relocation
;
1145 reloc_entry
->address
+= input_section
->output_offset
;
1150 /* This is a partial relocation, but inplace, so modify the
1153 If we've relocated with a symbol with a section, change
1154 into a ref to the section belonging to the symbol. */
1155 reloc_entry
->address
+= input_section
->output_offset
;
1158 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1159 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1160 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1163 /* For m68k-coff, the addend was being subtracted twice during
1164 relocation with -r. Removing the line below this comment
1165 fixes that problem; see PR 2953.
1167 However, Ian wrote the following, regarding removing the line below,
1168 which explains why it is still enabled: --djm
1170 If you put a patch like that into BFD you need to check all the COFF
1171 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1172 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1173 problem in a different way. There may very well be a reason that the
1174 code works as it does.
1176 Hmmm. The first obvious point is that bfd_install_relocation should
1177 not have any tests that depend upon the flavour. It's seem like
1178 entirely the wrong place for such a thing. The second obvious point
1179 is that the current code ignores the reloc addend when producing
1180 relocatable output for COFF. That's peculiar. In fact, I really
1181 have no idea what the point of the line you want to remove is.
1183 A typical COFF reloc subtracts the old value of the symbol and adds in
1184 the new value to the location in the object file (if it's a pc
1185 relative reloc it adds the difference between the symbol value and the
1186 location). When relocating we need to preserve that property.
1188 BFD handles this by setting the addend to the negative of the old
1189 value of the symbol. Unfortunately it handles common symbols in a
1190 non-standard way (it doesn't subtract the old value) but that's a
1191 different story (we can't change it without losing backward
1192 compatibility with old object files) (coff-i386 does subtract the old
1193 value, to be compatible with existing coff-i386 targets, like SCO).
1195 So everything works fine when not producing relocatable output. When
1196 we are producing relocatable output, logically we should do exactly
1197 what we do when not producing relocatable output. Therefore, your
1198 patch is correct. In fact, it should probably always just set
1199 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1200 add the value into the object file. This won't hurt the COFF code,
1201 which doesn't use the addend; I'm not sure what it will do to other
1202 formats (the thing to check for would be whether any formats both use
1203 the addend and set partial_inplace).
1205 When I wanted to make coff-i386 produce relocatable output, I ran
1206 into the problem that you are running into: I wanted to remove that
1207 line. Rather than risk it, I made the coff-i386 relocs use a special
1208 function; it's coff_i386_reloc in coff-i386.c. The function
1209 specifically adds the addend field into the object file, knowing that
1210 bfd_install_relocation is not going to. If you remove that line, then
1211 coff-i386.c will wind up adding the addend field in twice. It's
1212 trivial to fix; it just needs to be done.
1214 The problem with removing the line is just that it may break some
1215 working code. With BFD it's hard to be sure of anything. The right
1216 way to deal with this is simply to build and test at least all the
1217 supported COFF targets. It should be straightforward if time and disk
1218 space consuming. For each target:
1220 2) generate some executable, and link it using -r (I would
1221 probably use paranoia.o and link against newlib/libc.a, which
1222 for all the supported targets would be available in
1223 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1224 3) make the change to reloc.c
1225 4) rebuild the linker
1227 6) if the resulting object files are the same, you have at least
1229 7) if they are different you have to figure out which version is
1231 relocation
-= reloc_entry
->addend
;
1232 /* FIXME: There should be no target specific code here... */
1233 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1234 reloc_entry
->addend
= 0;
1238 reloc_entry
->addend
= relocation
;
1242 /* FIXME: This overflow checking is incomplete, because the value
1243 might have overflowed before we get here. For a correct check we
1244 need to compute the value in a size larger than bitsize, but we
1245 can't reasonably do that for a reloc the same size as a host
1247 FIXME: We should also do overflow checking on the result after
1248 adding in the value contained in the object file. */
1249 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1250 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1253 bfd_arch_bits_per_address (abfd
),
1256 /* Either we are relocating all the way, or we don't want to apply
1257 the relocation to the reloc entry (probably because there isn't
1258 any room in the output format to describe addends to relocs). */
1260 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1261 (OSF version 1.3, compiler version 3.11). It miscompiles the
1275 x <<= (unsigned long) s.i0;
1277 printf ("failed\n");
1279 printf ("succeeded (%lx)\n", x);
1283 relocation
>>= (bfd_vma
) howto
->rightshift
;
1285 /* Shift everything up to where it's going to be used. */
1286 relocation
<<= (bfd_vma
) howto
->bitpos
;
1288 /* Wait for the day when all have the mask in them. */
1291 i instruction to be left alone
1292 o offset within instruction
1293 r relocation offset to apply
1302 (( i i i i i o o o o o from bfd_get<size>
1303 and S S S S S) to get the size offset we want
1304 + r r r r r r r r r r) to get the final value to place
1305 and D D D D D to chop to right size
1306 -----------------------
1309 ( i i i i i o o o o o from bfd_get<size>
1310 and N N N N N ) get instruction
1311 -----------------------
1317 -----------------------
1318 = R R R R R R R R R R put into bfd_put<size>
1321 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1322 apply_reloc (abfd
, data
, howto
, relocation
);
1326 /* This relocation routine is used by some of the backend linkers.
1327 They do not construct asymbol or arelent structures, so there is no
1328 reason for them to use bfd_perform_relocation. Also,
1329 bfd_perform_relocation is so hacked up it is easier to write a new
1330 function than to try to deal with it.
1332 This routine does a final relocation. Whether it is useful for a
1333 relocatable link depends upon how the object format defines
1336 FIXME: This routine ignores any special_function in the HOWTO,
1337 since the existing special_function values have been written for
1338 bfd_perform_relocation.
1340 HOWTO is the reloc howto information.
1341 INPUT_BFD is the BFD which the reloc applies to.
1342 INPUT_SECTION is the section which the reloc applies to.
1343 CONTENTS is the contents of the section.
1344 ADDRESS is the address of the reloc within INPUT_SECTION.
1345 VALUE is the value of the symbol the reloc refers to.
1346 ADDEND is the addend of the reloc. */
1348 bfd_reloc_status_type
1349 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1351 asection
*input_section
,
1358 bfd_size_type octets
= (address
1359 * bfd_octets_per_byte (input_bfd
, input_section
));
1361 /* Sanity check the address. */
1362 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, octets
))
1363 return bfd_reloc_outofrange
;
1365 /* This function assumes that we are dealing with a basic relocation
1366 against a symbol. We want to compute the value of the symbol to
1367 relocate to. This is just VALUE, the value of the symbol, plus
1368 ADDEND, any addend associated with the reloc. */
1369 relocation
= value
+ addend
;
1371 /* If the relocation is PC relative, we want to set RELOCATION to
1372 the distance between the symbol (currently in RELOCATION) and the
1373 location we are relocating. Some targets (e.g., i386-aout)
1374 arrange for the contents of the section to be the negative of the
1375 offset of the location within the section; for such targets
1376 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1377 the contents of the section as zero; for such targets
1378 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1379 subtract out the offset of the location within the section (which
1380 is just ADDRESS). */
1381 if (howto
->pc_relative
)
1383 relocation
-= (input_section
->output_section
->vma
1384 + input_section
->output_offset
);
1385 if (howto
->pcrel_offset
)
1386 relocation
-= address
;
1389 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1393 /* Relocate a given location using a given value and howto. */
1395 bfd_reloc_status_type
1396 _bfd_relocate_contents (reloc_howto_type
*howto
,
1402 bfd_reloc_status_type flag
;
1403 unsigned int rightshift
= howto
->rightshift
;
1404 unsigned int bitpos
= howto
->bitpos
;
1407 relocation
= -relocation
;
1409 /* Get the value we are going to relocate. */
1410 x
= read_reloc (input_bfd
, location
, howto
);
1412 /* Check for overflow. FIXME: We may drop bits during the addition
1413 which we don't check for. We must either check at every single
1414 operation, which would be tedious, or we must do the computations
1415 in a type larger than bfd_vma, which would be inefficient. */
1416 flag
= bfd_reloc_ok
;
1417 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1419 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1422 /* Get the values to be added together. For signed and unsigned
1423 relocations, we assume that all values should be truncated to
1424 the size of an address. For bitfields, all the bits matter.
1425 See also bfd_check_overflow. */
1426 fieldmask
= N_ONES (howto
->bitsize
);
1427 signmask
= ~fieldmask
;
1428 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1429 | (fieldmask
<< rightshift
));
1430 a
= (relocation
& addrmask
) >> rightshift
;
1431 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1432 addrmask
>>= rightshift
;
1434 switch (howto
->complain_on_overflow
)
1436 case complain_overflow_signed
:
1437 /* If any sign bits are set, all sign bits must be set.
1438 That is, A must be a valid negative address after
1440 signmask
= ~(fieldmask
>> 1);
1443 case complain_overflow_bitfield
:
1444 /* Much like the signed check, but for a field one bit
1445 wider. We allow a bitfield to represent numbers in the
1446 range -2**n to 2**n-1, where n is the number of bits in the
1447 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1448 can't overflow, which is exactly what we want. */
1450 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1451 flag
= bfd_reloc_overflow
;
1453 /* We only need this next bit of code if the sign bit of B
1454 is below the sign bit of A. This would only happen if
1455 SRC_MASK had fewer bits than BITSIZE. Note that if
1456 SRC_MASK has more bits than BITSIZE, we can get into
1457 trouble; we would need to verify that B is in range, as
1458 we do for A above. */
1459 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1462 /* Set all the bits above the sign bit. */
1465 /* Now we can do the addition. */
1468 /* See if the result has the correct sign. Bits above the
1469 sign bit are junk now; ignore them. If the sum is
1470 positive, make sure we did not have all negative inputs;
1471 if the sum is negative, make sure we did not have all
1472 positive inputs. The test below looks only at the sign
1473 bits, and it really just
1474 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1476 We mask with addrmask here to explicitly allow an address
1477 wrap-around. The Linux kernel relies on it, and it is
1478 the only way to write assembler code which can run when
1479 loaded at a location 0x80000000 away from the location at
1480 which it is linked. */
1481 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1482 flag
= bfd_reloc_overflow
;
1485 case complain_overflow_unsigned
:
1486 /* Checking for an unsigned overflow is relatively easy:
1487 trim the addresses and add, and trim the result as well.
1488 Overflow is normally indicated when the result does not
1489 fit in the field. However, we also need to consider the
1490 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1491 input is 0x80000000, and bfd_vma is only 32 bits; then we
1492 will get sum == 0, but there is an overflow, since the
1493 inputs did not fit in the field. Instead of doing a
1494 separate test, we can check for this by or-ing in the
1495 operands when testing for the sum overflowing its final
1497 sum
= (a
+ b
) & addrmask
;
1498 if ((a
| b
| sum
) & signmask
)
1499 flag
= bfd_reloc_overflow
;
1507 /* Put RELOCATION in the right bits. */
1508 relocation
>>= (bfd_vma
) rightshift
;
1509 relocation
<<= (bfd_vma
) bitpos
;
1511 /* Add RELOCATION to the right bits of X. */
1512 x
= ((x
& ~howto
->dst_mask
)
1513 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1515 /* Put the relocated value back in the object file. */
1516 write_reloc (input_bfd
, x
, location
, howto
);
1520 /* Clear a given location using a given howto, by applying a fixed relocation
1521 value and discarding any in-place addend. This is used for fixed-up
1522 relocations against discarded symbols, to make ignorable debug or unwind
1523 information more obvious. */
1525 bfd_reloc_status_type
1526 _bfd_clear_contents (reloc_howto_type
*howto
,
1528 asection
*input_section
,
1535 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, off
))
1536 return bfd_reloc_outofrange
;
1538 /* Get the value we are going to relocate. */
1539 location
= buf
+ off
;
1540 x
= read_reloc (input_bfd
, location
, howto
);
1542 /* Zero out the unwanted bits of X. */
1543 x
&= ~howto
->dst_mask
;
1545 /* For a range list, use 1 instead of 0 as placeholder. 0
1546 would terminate the list, hiding any later entries. */
1547 if (strcmp (bfd_section_name (input_section
), ".debug_ranges") == 0
1548 && (howto
->dst_mask
& 1) != 0)
1551 /* Put the relocated value back in the object file. */
1552 write_reloc (input_bfd
, x
, location
, howto
);
1553 return bfd_reloc_ok
;
1559 howto manager, , typedef arelent, Relocations
1564 When an application wants to create a relocation, but doesn't
1565 know what the target machine might call it, it can find out by
1566 using this bit of code.
1575 The insides of a reloc code. The idea is that, eventually, there
1576 will be one enumerator for every type of relocation we ever do.
1577 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1578 return a howto pointer.
1580 This does mean that the application must determine the correct
1581 enumerator value; you can't get a howto pointer from a random set
1602 Basic absolute relocations of N bits.
1617 PC-relative relocations. Sometimes these are relative to the address
1618 of the relocation itself; sometimes they are relative to the start of
1619 the section containing the relocation. It depends on the specific target.
1624 Section relative relocations. Some targets need this for DWARF2.
1627 BFD_RELOC_32_GOT_PCREL
1629 BFD_RELOC_16_GOT_PCREL
1631 BFD_RELOC_8_GOT_PCREL
1637 BFD_RELOC_LO16_GOTOFF
1639 BFD_RELOC_HI16_GOTOFF
1641 BFD_RELOC_HI16_S_GOTOFF
1645 BFD_RELOC_64_PLT_PCREL
1647 BFD_RELOC_32_PLT_PCREL
1649 BFD_RELOC_24_PLT_PCREL
1651 BFD_RELOC_16_PLT_PCREL
1653 BFD_RELOC_8_PLT_PCREL
1661 BFD_RELOC_LO16_PLTOFF
1663 BFD_RELOC_HI16_PLTOFF
1665 BFD_RELOC_HI16_S_PLTOFF
1679 BFD_RELOC_68K_GLOB_DAT
1681 BFD_RELOC_68K_JMP_SLOT
1683 BFD_RELOC_68K_RELATIVE
1685 BFD_RELOC_68K_TLS_GD32
1687 BFD_RELOC_68K_TLS_GD16
1689 BFD_RELOC_68K_TLS_GD8
1691 BFD_RELOC_68K_TLS_LDM32
1693 BFD_RELOC_68K_TLS_LDM16
1695 BFD_RELOC_68K_TLS_LDM8
1697 BFD_RELOC_68K_TLS_LDO32
1699 BFD_RELOC_68K_TLS_LDO16
1701 BFD_RELOC_68K_TLS_LDO8
1703 BFD_RELOC_68K_TLS_IE32
1705 BFD_RELOC_68K_TLS_IE16
1707 BFD_RELOC_68K_TLS_IE8
1709 BFD_RELOC_68K_TLS_LE32
1711 BFD_RELOC_68K_TLS_LE16
1713 BFD_RELOC_68K_TLS_LE8
1715 Relocations used by 68K ELF.
1718 BFD_RELOC_32_BASEREL
1720 BFD_RELOC_16_BASEREL
1722 BFD_RELOC_LO16_BASEREL
1724 BFD_RELOC_HI16_BASEREL
1726 BFD_RELOC_HI16_S_BASEREL
1732 Linkage-table relative.
1737 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1740 BFD_RELOC_32_PCREL_S2
1742 BFD_RELOC_16_PCREL_S2
1744 BFD_RELOC_23_PCREL_S2
1746 These PC-relative relocations are stored as word displacements --
1747 i.e., byte displacements shifted right two bits. The 30-bit word
1748 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1749 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1750 signed 16-bit displacement is used on the MIPS, and the 23-bit
1751 displacement is used on the Alpha.
1758 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1759 the target word. These are used on the SPARC.
1766 For systems that allocate a Global Pointer register, these are
1767 displacements off that register. These relocation types are
1768 handled specially, because the value the register will have is
1769 decided relatively late.
1774 BFD_RELOC_SPARC_WDISP22
1780 BFD_RELOC_SPARC_GOT10
1782 BFD_RELOC_SPARC_GOT13
1784 BFD_RELOC_SPARC_GOT22
1786 BFD_RELOC_SPARC_PC10
1788 BFD_RELOC_SPARC_PC22
1790 BFD_RELOC_SPARC_WPLT30
1792 BFD_RELOC_SPARC_COPY
1794 BFD_RELOC_SPARC_GLOB_DAT
1796 BFD_RELOC_SPARC_JMP_SLOT
1798 BFD_RELOC_SPARC_RELATIVE
1800 BFD_RELOC_SPARC_UA16
1802 BFD_RELOC_SPARC_UA32
1804 BFD_RELOC_SPARC_UA64
1806 BFD_RELOC_SPARC_GOTDATA_HIX22
1808 BFD_RELOC_SPARC_GOTDATA_LOX10
1810 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1812 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1814 BFD_RELOC_SPARC_GOTDATA_OP
1816 BFD_RELOC_SPARC_JMP_IREL
1818 BFD_RELOC_SPARC_IRELATIVE
1820 SPARC ELF relocations. There is probably some overlap with other
1821 relocation types already defined.
1824 BFD_RELOC_SPARC_BASE13
1826 BFD_RELOC_SPARC_BASE22
1828 I think these are specific to SPARC a.out (e.g., Sun 4).
1838 BFD_RELOC_SPARC_OLO10
1840 BFD_RELOC_SPARC_HH22
1842 BFD_RELOC_SPARC_HM10
1844 BFD_RELOC_SPARC_LM22
1846 BFD_RELOC_SPARC_PC_HH22
1848 BFD_RELOC_SPARC_PC_HM10
1850 BFD_RELOC_SPARC_PC_LM22
1852 BFD_RELOC_SPARC_WDISP16
1854 BFD_RELOC_SPARC_WDISP19
1862 BFD_RELOC_SPARC_DISP64
1865 BFD_RELOC_SPARC_PLT32
1867 BFD_RELOC_SPARC_PLT64
1869 BFD_RELOC_SPARC_HIX22
1871 BFD_RELOC_SPARC_LOX10
1879 BFD_RELOC_SPARC_REGISTER
1883 BFD_RELOC_SPARC_SIZE32
1885 BFD_RELOC_SPARC_SIZE64
1887 BFD_RELOC_SPARC_WDISP10
1892 BFD_RELOC_SPARC_REV32
1894 SPARC little endian relocation
1896 BFD_RELOC_SPARC_TLS_GD_HI22
1898 BFD_RELOC_SPARC_TLS_GD_LO10
1900 BFD_RELOC_SPARC_TLS_GD_ADD
1902 BFD_RELOC_SPARC_TLS_GD_CALL
1904 BFD_RELOC_SPARC_TLS_LDM_HI22
1906 BFD_RELOC_SPARC_TLS_LDM_LO10
1908 BFD_RELOC_SPARC_TLS_LDM_ADD
1910 BFD_RELOC_SPARC_TLS_LDM_CALL
1912 BFD_RELOC_SPARC_TLS_LDO_HIX22
1914 BFD_RELOC_SPARC_TLS_LDO_LOX10
1916 BFD_RELOC_SPARC_TLS_LDO_ADD
1918 BFD_RELOC_SPARC_TLS_IE_HI22
1920 BFD_RELOC_SPARC_TLS_IE_LO10
1922 BFD_RELOC_SPARC_TLS_IE_LD
1924 BFD_RELOC_SPARC_TLS_IE_LDX
1926 BFD_RELOC_SPARC_TLS_IE_ADD
1928 BFD_RELOC_SPARC_TLS_LE_HIX22
1930 BFD_RELOC_SPARC_TLS_LE_LOX10
1932 BFD_RELOC_SPARC_TLS_DTPMOD32
1934 BFD_RELOC_SPARC_TLS_DTPMOD64
1936 BFD_RELOC_SPARC_TLS_DTPOFF32
1938 BFD_RELOC_SPARC_TLS_DTPOFF64
1940 BFD_RELOC_SPARC_TLS_TPOFF32
1942 BFD_RELOC_SPARC_TLS_TPOFF64
1944 SPARC TLS relocations
1953 BFD_RELOC_SPU_IMM10W
1957 BFD_RELOC_SPU_IMM16W
1961 BFD_RELOC_SPU_PCREL9a
1963 BFD_RELOC_SPU_PCREL9b
1965 BFD_RELOC_SPU_PCREL16
1975 BFD_RELOC_SPU_ADD_PIC
1980 BFD_RELOC_ALPHA_GPDISP_HI16
1982 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
1983 "addend" in some special way.
1984 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
1985 writing; when reading, it will be the absolute section symbol. The
1986 addend is the displacement in bytes of the "lda" instruction from
1987 the "ldah" instruction (which is at the address of this reloc).
1989 BFD_RELOC_ALPHA_GPDISP_LO16
1991 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
1992 with GPDISP_HI16 relocs. The addend is ignored when writing the
1993 relocations out, and is filled in with the file's GP value on
1994 reading, for convenience.
1997 BFD_RELOC_ALPHA_GPDISP
1999 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2000 relocation except that there is no accompanying GPDISP_LO16
2004 BFD_RELOC_ALPHA_LITERAL
2006 BFD_RELOC_ALPHA_ELF_LITERAL
2008 BFD_RELOC_ALPHA_LITUSE
2010 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2011 the assembler turns it into a LDQ instruction to load the address of
2012 the symbol, and then fills in a register in the real instruction.
2014 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2015 section symbol. The addend is ignored when writing, but is filled
2016 in with the file's GP value on reading, for convenience, as with the
2019 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2020 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2021 but it generates output not based on the position within the .got
2022 section, but relative to the GP value chosen for the file during the
2025 The LITUSE reloc, on the instruction using the loaded address, gives
2026 information to the linker that it might be able to use to optimize
2027 away some literal section references. The symbol is ignored (read
2028 as the absolute section symbol), and the "addend" indicates the type
2029 of instruction using the register:
2030 1 - "memory" fmt insn
2031 2 - byte-manipulation (byte offset reg)
2032 3 - jsr (target of branch)
2035 BFD_RELOC_ALPHA_HINT
2037 The HINT relocation indicates a value that should be filled into the
2038 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2039 prediction logic which may be provided on some processors.
2042 BFD_RELOC_ALPHA_LINKAGE
2044 The LINKAGE relocation outputs a linkage pair in the object file,
2045 which is filled by the linker.
2048 BFD_RELOC_ALPHA_CODEADDR
2050 The CODEADDR relocation outputs a STO_CA in the object file,
2051 which is filled by the linker.
2054 BFD_RELOC_ALPHA_GPREL_HI16
2056 BFD_RELOC_ALPHA_GPREL_LO16
2058 The GPREL_HI/LO relocations together form a 32-bit offset from the
2062 BFD_RELOC_ALPHA_BRSGP
2064 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2065 share a common GP, and the target address is adjusted for
2066 STO_ALPHA_STD_GPLOAD.
2071 The NOP relocation outputs a NOP if the longword displacement
2072 between two procedure entry points is < 2^21.
2077 The BSR relocation outputs a BSR if the longword displacement
2078 between two procedure entry points is < 2^21.
2083 The LDA relocation outputs a LDA if the longword displacement
2084 between two procedure entry points is < 2^16.
2089 The BOH relocation outputs a BSR if the longword displacement
2090 between two procedure entry points is < 2^21, or else a hint.
2093 BFD_RELOC_ALPHA_TLSGD
2095 BFD_RELOC_ALPHA_TLSLDM
2097 BFD_RELOC_ALPHA_DTPMOD64
2099 BFD_RELOC_ALPHA_GOTDTPREL16
2101 BFD_RELOC_ALPHA_DTPREL64
2103 BFD_RELOC_ALPHA_DTPREL_HI16
2105 BFD_RELOC_ALPHA_DTPREL_LO16
2107 BFD_RELOC_ALPHA_DTPREL16
2109 BFD_RELOC_ALPHA_GOTTPREL16
2111 BFD_RELOC_ALPHA_TPREL64
2113 BFD_RELOC_ALPHA_TPREL_HI16
2115 BFD_RELOC_ALPHA_TPREL_LO16
2117 BFD_RELOC_ALPHA_TPREL16
2119 Alpha thread-local storage relocations.
2124 BFD_RELOC_MICROMIPS_JMP
2126 The MIPS jump instruction.
2129 BFD_RELOC_MIPS16_JMP
2131 The MIPS16 jump instruction.
2134 BFD_RELOC_MIPS16_GPREL
2136 MIPS16 GP relative reloc.
2141 High 16 bits of 32-bit value; simple reloc.
2146 High 16 bits of 32-bit value but the low 16 bits will be sign
2147 extended and added to form the final result. If the low 16
2148 bits form a negative number, we need to add one to the high value
2149 to compensate for the borrow when the low bits are added.
2157 BFD_RELOC_HI16_PCREL
2159 High 16 bits of 32-bit pc-relative value
2161 BFD_RELOC_HI16_S_PCREL
2163 High 16 bits of 32-bit pc-relative value, adjusted
2165 BFD_RELOC_LO16_PCREL
2167 Low 16 bits of pc-relative value
2170 BFD_RELOC_MIPS16_GOT16
2172 BFD_RELOC_MIPS16_CALL16
2174 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2175 16-bit immediate fields
2177 BFD_RELOC_MIPS16_HI16
2179 MIPS16 high 16 bits of 32-bit value.
2181 BFD_RELOC_MIPS16_HI16_S
2183 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2184 extended and added to form the final result. If the low 16
2185 bits form a negative number, we need to add one to the high value
2186 to compensate for the borrow when the low bits are added.
2188 BFD_RELOC_MIPS16_LO16
2193 BFD_RELOC_MIPS16_TLS_GD
2195 BFD_RELOC_MIPS16_TLS_LDM
2197 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2199 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2201 BFD_RELOC_MIPS16_TLS_GOTTPREL
2203 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2205 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2207 MIPS16 TLS relocations
2210 BFD_RELOC_MIPS_LITERAL
2212 BFD_RELOC_MICROMIPS_LITERAL
2214 Relocation against a MIPS literal section.
2217 BFD_RELOC_MICROMIPS_7_PCREL_S1
2219 BFD_RELOC_MICROMIPS_10_PCREL_S1
2221 BFD_RELOC_MICROMIPS_16_PCREL_S1
2223 microMIPS PC-relative relocations.
2226 BFD_RELOC_MIPS16_16_PCREL_S1
2228 MIPS16 PC-relative relocation.
2231 BFD_RELOC_MIPS_21_PCREL_S2
2233 BFD_RELOC_MIPS_26_PCREL_S2
2235 BFD_RELOC_MIPS_18_PCREL_S3
2237 BFD_RELOC_MIPS_19_PCREL_S2
2239 MIPS PC-relative relocations.
2242 BFD_RELOC_MICROMIPS_GPREL16
2244 BFD_RELOC_MICROMIPS_HI16
2246 BFD_RELOC_MICROMIPS_HI16_S
2248 BFD_RELOC_MICROMIPS_LO16
2250 microMIPS versions of generic BFD relocs.
2253 BFD_RELOC_MIPS_GOT16
2255 BFD_RELOC_MICROMIPS_GOT16
2257 BFD_RELOC_MIPS_CALL16
2259 BFD_RELOC_MICROMIPS_CALL16
2261 BFD_RELOC_MIPS_GOT_HI16
2263 BFD_RELOC_MICROMIPS_GOT_HI16
2265 BFD_RELOC_MIPS_GOT_LO16
2267 BFD_RELOC_MICROMIPS_GOT_LO16
2269 BFD_RELOC_MIPS_CALL_HI16
2271 BFD_RELOC_MICROMIPS_CALL_HI16
2273 BFD_RELOC_MIPS_CALL_LO16
2275 BFD_RELOC_MICROMIPS_CALL_LO16
2279 BFD_RELOC_MICROMIPS_SUB
2281 BFD_RELOC_MIPS_GOT_PAGE
2283 BFD_RELOC_MICROMIPS_GOT_PAGE
2285 BFD_RELOC_MIPS_GOT_OFST
2287 BFD_RELOC_MICROMIPS_GOT_OFST
2289 BFD_RELOC_MIPS_GOT_DISP
2291 BFD_RELOC_MICROMIPS_GOT_DISP
2293 BFD_RELOC_MIPS_SHIFT5
2295 BFD_RELOC_MIPS_SHIFT6
2297 BFD_RELOC_MIPS_INSERT_A
2299 BFD_RELOC_MIPS_INSERT_B
2301 BFD_RELOC_MIPS_DELETE
2303 BFD_RELOC_MIPS_HIGHEST
2305 BFD_RELOC_MICROMIPS_HIGHEST
2307 BFD_RELOC_MIPS_HIGHER
2309 BFD_RELOC_MICROMIPS_HIGHER
2311 BFD_RELOC_MIPS_SCN_DISP
2313 BFD_RELOC_MICROMIPS_SCN_DISP
2315 BFD_RELOC_MIPS_REL16
2317 BFD_RELOC_MIPS_RELGOT
2321 BFD_RELOC_MICROMIPS_JALR
2323 BFD_RELOC_MIPS_TLS_DTPMOD32
2325 BFD_RELOC_MIPS_TLS_DTPREL32
2327 BFD_RELOC_MIPS_TLS_DTPMOD64
2329 BFD_RELOC_MIPS_TLS_DTPREL64
2331 BFD_RELOC_MIPS_TLS_GD
2333 BFD_RELOC_MICROMIPS_TLS_GD
2335 BFD_RELOC_MIPS_TLS_LDM
2337 BFD_RELOC_MICROMIPS_TLS_LDM
2339 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2341 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2343 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2345 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2347 BFD_RELOC_MIPS_TLS_GOTTPREL
2349 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2351 BFD_RELOC_MIPS_TLS_TPREL32
2353 BFD_RELOC_MIPS_TLS_TPREL64
2355 BFD_RELOC_MIPS_TLS_TPREL_HI16
2357 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2359 BFD_RELOC_MIPS_TLS_TPREL_LO16
2361 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2365 MIPS ELF relocations.
2371 BFD_RELOC_MIPS_JUMP_SLOT
2373 MIPS ELF relocations (VxWorks and PLT extensions).
2377 BFD_RELOC_MOXIE_10_PCREL
2379 Moxie ELF relocations.
2391 BFD_RELOC_FT32_RELAX
2399 BFD_RELOC_FT32_DIFF32
2401 FT32 ELF relocations.
2405 BFD_RELOC_FRV_LABEL16
2407 BFD_RELOC_FRV_LABEL24
2413 BFD_RELOC_FRV_GPREL12
2415 BFD_RELOC_FRV_GPRELU12
2417 BFD_RELOC_FRV_GPREL32
2419 BFD_RELOC_FRV_GPRELHI
2421 BFD_RELOC_FRV_GPRELLO
2429 BFD_RELOC_FRV_FUNCDESC
2431 BFD_RELOC_FRV_FUNCDESC_GOT12
2433 BFD_RELOC_FRV_FUNCDESC_GOTHI
2435 BFD_RELOC_FRV_FUNCDESC_GOTLO
2437 BFD_RELOC_FRV_FUNCDESC_VALUE
2439 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2441 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2443 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2445 BFD_RELOC_FRV_GOTOFF12
2447 BFD_RELOC_FRV_GOTOFFHI
2449 BFD_RELOC_FRV_GOTOFFLO
2451 BFD_RELOC_FRV_GETTLSOFF
2453 BFD_RELOC_FRV_TLSDESC_VALUE
2455 BFD_RELOC_FRV_GOTTLSDESC12
2457 BFD_RELOC_FRV_GOTTLSDESCHI
2459 BFD_RELOC_FRV_GOTTLSDESCLO
2461 BFD_RELOC_FRV_TLSMOFF12
2463 BFD_RELOC_FRV_TLSMOFFHI
2465 BFD_RELOC_FRV_TLSMOFFLO
2467 BFD_RELOC_FRV_GOTTLSOFF12
2469 BFD_RELOC_FRV_GOTTLSOFFHI
2471 BFD_RELOC_FRV_GOTTLSOFFLO
2473 BFD_RELOC_FRV_TLSOFF
2475 BFD_RELOC_FRV_TLSDESC_RELAX
2477 BFD_RELOC_FRV_GETTLSOFF_RELAX
2479 BFD_RELOC_FRV_TLSOFF_RELAX
2481 BFD_RELOC_FRV_TLSMOFF
2483 Fujitsu Frv Relocations.
2487 BFD_RELOC_MN10300_GOTOFF24
2489 This is a 24bit GOT-relative reloc for the mn10300.
2491 BFD_RELOC_MN10300_GOT32
2493 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2496 BFD_RELOC_MN10300_GOT24
2498 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2501 BFD_RELOC_MN10300_GOT16
2503 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2506 BFD_RELOC_MN10300_COPY
2508 Copy symbol at runtime.
2510 BFD_RELOC_MN10300_GLOB_DAT
2514 BFD_RELOC_MN10300_JMP_SLOT
2518 BFD_RELOC_MN10300_RELATIVE
2520 Adjust by program base.
2522 BFD_RELOC_MN10300_SYM_DIFF
2524 Together with another reloc targeted at the same location,
2525 allows for a value that is the difference of two symbols
2526 in the same section.
2528 BFD_RELOC_MN10300_ALIGN
2530 The addend of this reloc is an alignment power that must
2531 be honoured at the offset's location, regardless of linker
2534 BFD_RELOC_MN10300_TLS_GD
2536 BFD_RELOC_MN10300_TLS_LD
2538 BFD_RELOC_MN10300_TLS_LDO
2540 BFD_RELOC_MN10300_TLS_GOTIE
2542 BFD_RELOC_MN10300_TLS_IE
2544 BFD_RELOC_MN10300_TLS_LE
2546 BFD_RELOC_MN10300_TLS_DTPMOD
2548 BFD_RELOC_MN10300_TLS_DTPOFF
2550 BFD_RELOC_MN10300_TLS_TPOFF
2552 Various TLS-related relocations.
2554 BFD_RELOC_MN10300_32_PCREL
2556 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2559 BFD_RELOC_MN10300_16_PCREL
2561 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2572 BFD_RELOC_386_GLOB_DAT
2574 BFD_RELOC_386_JUMP_SLOT
2576 BFD_RELOC_386_RELATIVE
2578 BFD_RELOC_386_GOTOFF
2582 BFD_RELOC_386_TLS_TPOFF
2584 BFD_RELOC_386_TLS_IE
2586 BFD_RELOC_386_TLS_GOTIE
2588 BFD_RELOC_386_TLS_LE
2590 BFD_RELOC_386_TLS_GD
2592 BFD_RELOC_386_TLS_LDM
2594 BFD_RELOC_386_TLS_LDO_32
2596 BFD_RELOC_386_TLS_IE_32
2598 BFD_RELOC_386_TLS_LE_32
2600 BFD_RELOC_386_TLS_DTPMOD32
2602 BFD_RELOC_386_TLS_DTPOFF32
2604 BFD_RELOC_386_TLS_TPOFF32
2606 BFD_RELOC_386_TLS_GOTDESC
2608 BFD_RELOC_386_TLS_DESC_CALL
2610 BFD_RELOC_386_TLS_DESC
2612 BFD_RELOC_386_IRELATIVE
2614 BFD_RELOC_386_GOT32X
2616 i386/elf relocations
2619 BFD_RELOC_X86_64_GOT32
2621 BFD_RELOC_X86_64_PLT32
2623 BFD_RELOC_X86_64_COPY
2625 BFD_RELOC_X86_64_GLOB_DAT
2627 BFD_RELOC_X86_64_JUMP_SLOT
2629 BFD_RELOC_X86_64_RELATIVE
2631 BFD_RELOC_X86_64_GOTPCREL
2633 BFD_RELOC_X86_64_32S
2635 BFD_RELOC_X86_64_DTPMOD64
2637 BFD_RELOC_X86_64_DTPOFF64
2639 BFD_RELOC_X86_64_TPOFF64
2641 BFD_RELOC_X86_64_TLSGD
2643 BFD_RELOC_X86_64_TLSLD
2645 BFD_RELOC_X86_64_DTPOFF32
2647 BFD_RELOC_X86_64_GOTTPOFF
2649 BFD_RELOC_X86_64_TPOFF32
2651 BFD_RELOC_X86_64_GOTOFF64
2653 BFD_RELOC_X86_64_GOTPC32
2655 BFD_RELOC_X86_64_GOT64
2657 BFD_RELOC_X86_64_GOTPCREL64
2659 BFD_RELOC_X86_64_GOTPC64
2661 BFD_RELOC_X86_64_GOTPLT64
2663 BFD_RELOC_X86_64_PLTOFF64
2665 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2667 BFD_RELOC_X86_64_TLSDESC_CALL
2669 BFD_RELOC_X86_64_TLSDESC
2671 BFD_RELOC_X86_64_IRELATIVE
2673 BFD_RELOC_X86_64_PC32_BND
2675 BFD_RELOC_X86_64_PLT32_BND
2677 BFD_RELOC_X86_64_GOTPCRELX
2679 BFD_RELOC_X86_64_REX_GOTPCRELX
2681 x86-64/elf relocations
2684 BFD_RELOC_NS32K_IMM_8
2686 BFD_RELOC_NS32K_IMM_16
2688 BFD_RELOC_NS32K_IMM_32
2690 BFD_RELOC_NS32K_IMM_8_PCREL
2692 BFD_RELOC_NS32K_IMM_16_PCREL
2694 BFD_RELOC_NS32K_IMM_32_PCREL
2696 BFD_RELOC_NS32K_DISP_8
2698 BFD_RELOC_NS32K_DISP_16
2700 BFD_RELOC_NS32K_DISP_32
2702 BFD_RELOC_NS32K_DISP_8_PCREL
2704 BFD_RELOC_NS32K_DISP_16_PCREL
2706 BFD_RELOC_NS32K_DISP_32_PCREL
2711 BFD_RELOC_PDP11_DISP_8_PCREL
2713 BFD_RELOC_PDP11_DISP_6_PCREL
2718 BFD_RELOC_PJ_CODE_HI16
2720 BFD_RELOC_PJ_CODE_LO16
2722 BFD_RELOC_PJ_CODE_DIR16
2724 BFD_RELOC_PJ_CODE_DIR32
2726 BFD_RELOC_PJ_CODE_REL16
2728 BFD_RELOC_PJ_CODE_REL32
2730 Picojava relocs. Not all of these appear in object files.
2741 BFD_RELOC_PPC_B16_BRTAKEN
2743 BFD_RELOC_PPC_B16_BRNTAKEN
2747 BFD_RELOC_PPC_BA16_BRTAKEN
2749 BFD_RELOC_PPC_BA16_BRNTAKEN
2753 BFD_RELOC_PPC_GLOB_DAT
2755 BFD_RELOC_PPC_JMP_SLOT
2757 BFD_RELOC_PPC_RELATIVE
2759 BFD_RELOC_PPC_LOCAL24PC
2761 BFD_RELOC_PPC_EMB_NADDR32
2763 BFD_RELOC_PPC_EMB_NADDR16
2765 BFD_RELOC_PPC_EMB_NADDR16_LO
2767 BFD_RELOC_PPC_EMB_NADDR16_HI
2769 BFD_RELOC_PPC_EMB_NADDR16_HA
2771 BFD_RELOC_PPC_EMB_SDAI16
2773 BFD_RELOC_PPC_EMB_SDA2I16
2775 BFD_RELOC_PPC_EMB_SDA2REL
2777 BFD_RELOC_PPC_EMB_SDA21
2779 BFD_RELOC_PPC_EMB_MRKREF
2781 BFD_RELOC_PPC_EMB_RELSEC16
2783 BFD_RELOC_PPC_EMB_RELST_LO
2785 BFD_RELOC_PPC_EMB_RELST_HI
2787 BFD_RELOC_PPC_EMB_RELST_HA
2789 BFD_RELOC_PPC_EMB_BIT_FLD
2791 BFD_RELOC_PPC_EMB_RELSDA
2793 BFD_RELOC_PPC_VLE_REL8
2795 BFD_RELOC_PPC_VLE_REL15
2797 BFD_RELOC_PPC_VLE_REL24
2799 BFD_RELOC_PPC_VLE_LO16A
2801 BFD_RELOC_PPC_VLE_LO16D
2803 BFD_RELOC_PPC_VLE_HI16A
2805 BFD_RELOC_PPC_VLE_HI16D
2807 BFD_RELOC_PPC_VLE_HA16A
2809 BFD_RELOC_PPC_VLE_HA16D
2811 BFD_RELOC_PPC_VLE_SDA21
2813 BFD_RELOC_PPC_VLE_SDA21_LO
2815 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2817 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2819 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2821 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2823 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2825 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2827 BFD_RELOC_PPC_16DX_HA
2829 BFD_RELOC_PPC_REL16DX_HA
2831 BFD_RELOC_PPC64_HIGHER
2833 BFD_RELOC_PPC64_HIGHER_S
2835 BFD_RELOC_PPC64_HIGHEST
2837 BFD_RELOC_PPC64_HIGHEST_S
2839 BFD_RELOC_PPC64_TOC16_LO
2841 BFD_RELOC_PPC64_TOC16_HI
2843 BFD_RELOC_PPC64_TOC16_HA
2847 BFD_RELOC_PPC64_PLTGOT16
2849 BFD_RELOC_PPC64_PLTGOT16_LO
2851 BFD_RELOC_PPC64_PLTGOT16_HI
2853 BFD_RELOC_PPC64_PLTGOT16_HA
2855 BFD_RELOC_PPC64_ADDR16_DS
2857 BFD_RELOC_PPC64_ADDR16_LO_DS
2859 BFD_RELOC_PPC64_GOT16_DS
2861 BFD_RELOC_PPC64_GOT16_LO_DS
2863 BFD_RELOC_PPC64_PLT16_LO_DS
2865 BFD_RELOC_PPC64_SECTOFF_DS
2867 BFD_RELOC_PPC64_SECTOFF_LO_DS
2869 BFD_RELOC_PPC64_TOC16_DS
2871 BFD_RELOC_PPC64_TOC16_LO_DS
2873 BFD_RELOC_PPC64_PLTGOT16_DS
2875 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2877 BFD_RELOC_PPC64_ADDR16_HIGH
2879 BFD_RELOC_PPC64_ADDR16_HIGHA
2881 BFD_RELOC_PPC64_REL16_HIGH
2883 BFD_RELOC_PPC64_REL16_HIGHA
2885 BFD_RELOC_PPC64_REL16_HIGHER
2887 BFD_RELOC_PPC64_REL16_HIGHERA
2889 BFD_RELOC_PPC64_REL16_HIGHEST
2891 BFD_RELOC_PPC64_REL16_HIGHESTA
2893 BFD_RELOC_PPC64_ADDR64_LOCAL
2895 BFD_RELOC_PPC64_ENTRY
2897 BFD_RELOC_PPC64_REL24_NOTOC
2901 BFD_RELOC_PPC64_D34_LO
2903 BFD_RELOC_PPC64_D34_HI30
2905 BFD_RELOC_PPC64_D34_HA30
2907 BFD_RELOC_PPC64_PCREL34
2909 BFD_RELOC_PPC64_GOT_PCREL34
2911 BFD_RELOC_PPC64_PLT_PCREL34
2913 BFD_RELOC_PPC64_ADDR16_HIGHER34
2915 BFD_RELOC_PPC64_ADDR16_HIGHERA34
2917 BFD_RELOC_PPC64_ADDR16_HIGHEST34
2919 BFD_RELOC_PPC64_ADDR16_HIGHESTA34
2921 BFD_RELOC_PPC64_REL16_HIGHER34
2923 BFD_RELOC_PPC64_REL16_HIGHERA34
2925 BFD_RELOC_PPC64_REL16_HIGHEST34
2927 BFD_RELOC_PPC64_REL16_HIGHESTA34
2931 BFD_RELOC_PPC64_PCREL28
2933 Power(rs6000) and PowerPC relocations.
2942 BFD_RELOC_PPC_DTPMOD
2944 BFD_RELOC_PPC_TPREL16
2946 BFD_RELOC_PPC_TPREL16_LO
2948 BFD_RELOC_PPC_TPREL16_HI
2950 BFD_RELOC_PPC_TPREL16_HA
2954 BFD_RELOC_PPC_DTPREL16
2956 BFD_RELOC_PPC_DTPREL16_LO
2958 BFD_RELOC_PPC_DTPREL16_HI
2960 BFD_RELOC_PPC_DTPREL16_HA
2962 BFD_RELOC_PPC_DTPREL
2964 BFD_RELOC_PPC_GOT_TLSGD16
2966 BFD_RELOC_PPC_GOT_TLSGD16_LO
2968 BFD_RELOC_PPC_GOT_TLSGD16_HI
2970 BFD_RELOC_PPC_GOT_TLSGD16_HA
2972 BFD_RELOC_PPC_GOT_TLSLD16
2974 BFD_RELOC_PPC_GOT_TLSLD16_LO
2976 BFD_RELOC_PPC_GOT_TLSLD16_HI
2978 BFD_RELOC_PPC_GOT_TLSLD16_HA
2980 BFD_RELOC_PPC_GOT_TPREL16
2982 BFD_RELOC_PPC_GOT_TPREL16_LO
2984 BFD_RELOC_PPC_GOT_TPREL16_HI
2986 BFD_RELOC_PPC_GOT_TPREL16_HA
2988 BFD_RELOC_PPC_GOT_DTPREL16
2990 BFD_RELOC_PPC_GOT_DTPREL16_LO
2992 BFD_RELOC_PPC_GOT_DTPREL16_HI
2994 BFD_RELOC_PPC_GOT_DTPREL16_HA
2996 BFD_RELOC_PPC64_TPREL16_DS
2998 BFD_RELOC_PPC64_TPREL16_LO_DS
3000 BFD_RELOC_PPC64_TPREL16_HIGH
3002 BFD_RELOC_PPC64_TPREL16_HIGHA
3004 BFD_RELOC_PPC64_TPREL16_HIGHER
3006 BFD_RELOC_PPC64_TPREL16_HIGHERA
3008 BFD_RELOC_PPC64_TPREL16_HIGHEST
3010 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3012 BFD_RELOC_PPC64_DTPREL16_DS
3014 BFD_RELOC_PPC64_DTPREL16_LO_DS
3016 BFD_RELOC_PPC64_DTPREL16_HIGH
3018 BFD_RELOC_PPC64_DTPREL16_HIGHA
3020 BFD_RELOC_PPC64_DTPREL16_HIGHER
3022 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3024 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3026 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3028 BFD_RELOC_PPC64_TPREL34
3030 BFD_RELOC_PPC64_DTPREL34
3032 BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
3034 BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
3036 BFD_RELOC_PPC64_GOT_TPREL_PCREL34
3038 BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
3040 BFD_RELOC_PPC64_TLS_PCREL
3042 PowerPC and PowerPC64 thread-local storage relocations.
3047 IBM 370/390 relocations
3052 The type of reloc used to build a constructor table - at the moment
3053 probably a 32 bit wide absolute relocation, but the target can choose.
3054 It generally does map to one of the other relocation types.
3057 BFD_RELOC_ARM_PCREL_BRANCH
3059 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3060 not stored in the instruction.
3062 BFD_RELOC_ARM_PCREL_BLX
3064 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3065 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3066 field in the instruction.
3068 BFD_RELOC_THUMB_PCREL_BLX
3070 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3071 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3072 field in the instruction.
3074 BFD_RELOC_ARM_PCREL_CALL
3076 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3078 BFD_RELOC_ARM_PCREL_JUMP
3080 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3083 BFD_RELOC_THUMB_PCREL_BRANCH5
3085 ARM 5-bit pc-relative branch for Branch Future instructions.
3088 BFD_RELOC_THUMB_PCREL_BFCSEL
3090 ARM 6-bit pc-relative branch for BFCSEL instruction.
3093 BFD_RELOC_ARM_THUMB_BF17
3095 ARM 17-bit pc-relative branch for Branch Future instructions.
3098 BFD_RELOC_ARM_THUMB_BF13
3100 ARM 13-bit pc-relative branch for BFCSEL instruction.
3103 BFD_RELOC_ARM_THUMB_BF19
3105 ARM 19-bit pc-relative branch for Branch Future Link instruction.
3108 BFD_RELOC_ARM_THUMB_LOOP12
3110 ARM 12-bit pc-relative branch for Low Overhead Loop instructions.
3113 BFD_RELOC_THUMB_PCREL_BRANCH7
3115 BFD_RELOC_THUMB_PCREL_BRANCH9
3117 BFD_RELOC_THUMB_PCREL_BRANCH12
3119 BFD_RELOC_THUMB_PCREL_BRANCH20
3121 BFD_RELOC_THUMB_PCREL_BRANCH23
3123 BFD_RELOC_THUMB_PCREL_BRANCH25
3125 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3126 The lowest bit must be zero and is not stored in the instruction.
3127 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3128 "nn" one smaller in all cases. Note further that BRANCH23
3129 corresponds to R_ARM_THM_CALL.
3132 BFD_RELOC_ARM_OFFSET_IMM
3134 12-bit immediate offset, used in ARM-format ldr and str instructions.
3137 BFD_RELOC_ARM_THUMB_OFFSET
3139 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3142 BFD_RELOC_ARM_TARGET1
3144 Pc-relative or absolute relocation depending on target. Used for
3145 entries in .init_array sections.
3147 BFD_RELOC_ARM_ROSEGREL32
3149 Read-only segment base relative address.
3151 BFD_RELOC_ARM_SBREL32
3153 Data segment base relative address.
3155 BFD_RELOC_ARM_TARGET2
3157 This reloc is used for references to RTTI data from exception handling
3158 tables. The actual definition depends on the target. It may be a
3159 pc-relative or some form of GOT-indirect relocation.
3161 BFD_RELOC_ARM_PREL31
3163 31-bit PC relative address.
3169 BFD_RELOC_ARM_MOVW_PCREL
3171 BFD_RELOC_ARM_MOVT_PCREL
3173 BFD_RELOC_ARM_THUMB_MOVW
3175 BFD_RELOC_ARM_THUMB_MOVT
3177 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3179 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3181 Low and High halfword relocations for MOVW and MOVT instructions.
3184 BFD_RELOC_ARM_GOTFUNCDESC
3186 BFD_RELOC_ARM_GOTOFFFUNCDESC
3188 BFD_RELOC_ARM_FUNCDESC
3190 BFD_RELOC_ARM_FUNCDESC_VALUE
3192 BFD_RELOC_ARM_TLS_GD32_FDPIC
3194 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3196 BFD_RELOC_ARM_TLS_IE32_FDPIC
3198 ARM FDPIC specific relocations.
3201 BFD_RELOC_ARM_JUMP_SLOT
3203 BFD_RELOC_ARM_GLOB_DAT
3209 BFD_RELOC_ARM_RELATIVE
3211 BFD_RELOC_ARM_GOTOFF
3215 BFD_RELOC_ARM_GOT_PREL
3217 Relocations for setting up GOTs and PLTs for shared libraries.
3220 BFD_RELOC_ARM_TLS_GD32
3222 BFD_RELOC_ARM_TLS_LDO32
3224 BFD_RELOC_ARM_TLS_LDM32
3226 BFD_RELOC_ARM_TLS_DTPOFF32
3228 BFD_RELOC_ARM_TLS_DTPMOD32
3230 BFD_RELOC_ARM_TLS_TPOFF32
3232 BFD_RELOC_ARM_TLS_IE32
3234 BFD_RELOC_ARM_TLS_LE32
3236 BFD_RELOC_ARM_TLS_GOTDESC
3238 BFD_RELOC_ARM_TLS_CALL
3240 BFD_RELOC_ARM_THM_TLS_CALL
3242 BFD_RELOC_ARM_TLS_DESCSEQ
3244 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3246 BFD_RELOC_ARM_TLS_DESC
3248 ARM thread-local storage relocations.
3251 BFD_RELOC_ARM_ALU_PC_G0_NC
3253 BFD_RELOC_ARM_ALU_PC_G0
3255 BFD_RELOC_ARM_ALU_PC_G1_NC
3257 BFD_RELOC_ARM_ALU_PC_G1
3259 BFD_RELOC_ARM_ALU_PC_G2
3261 BFD_RELOC_ARM_LDR_PC_G0
3263 BFD_RELOC_ARM_LDR_PC_G1
3265 BFD_RELOC_ARM_LDR_PC_G2
3267 BFD_RELOC_ARM_LDRS_PC_G0
3269 BFD_RELOC_ARM_LDRS_PC_G1
3271 BFD_RELOC_ARM_LDRS_PC_G2
3273 BFD_RELOC_ARM_LDC_PC_G0
3275 BFD_RELOC_ARM_LDC_PC_G1
3277 BFD_RELOC_ARM_LDC_PC_G2
3279 BFD_RELOC_ARM_ALU_SB_G0_NC
3281 BFD_RELOC_ARM_ALU_SB_G0
3283 BFD_RELOC_ARM_ALU_SB_G1_NC
3285 BFD_RELOC_ARM_ALU_SB_G1
3287 BFD_RELOC_ARM_ALU_SB_G2
3289 BFD_RELOC_ARM_LDR_SB_G0
3291 BFD_RELOC_ARM_LDR_SB_G1
3293 BFD_RELOC_ARM_LDR_SB_G2
3295 BFD_RELOC_ARM_LDRS_SB_G0
3297 BFD_RELOC_ARM_LDRS_SB_G1
3299 BFD_RELOC_ARM_LDRS_SB_G2
3301 BFD_RELOC_ARM_LDC_SB_G0
3303 BFD_RELOC_ARM_LDC_SB_G1
3305 BFD_RELOC_ARM_LDC_SB_G2
3307 ARM group relocations.
3312 Annotation of BX instructions.
3315 BFD_RELOC_ARM_IRELATIVE
3317 ARM support for STT_GNU_IFUNC.
3320 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3322 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3324 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3326 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3328 Thumb1 relocations to support execute-only code.
3331 BFD_RELOC_ARM_IMMEDIATE
3333 BFD_RELOC_ARM_ADRL_IMMEDIATE
3335 BFD_RELOC_ARM_T32_IMMEDIATE
3337 BFD_RELOC_ARM_T32_ADD_IMM
3339 BFD_RELOC_ARM_T32_IMM12
3341 BFD_RELOC_ARM_T32_ADD_PC12
3343 BFD_RELOC_ARM_SHIFT_IMM
3353 BFD_RELOC_ARM_CP_OFF_IMM
3355 BFD_RELOC_ARM_CP_OFF_IMM_S2
3357 BFD_RELOC_ARM_T32_CP_OFF_IMM
3359 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3361 BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
3363 BFD_RELOC_ARM_ADR_IMM
3365 BFD_RELOC_ARM_LDR_IMM
3367 BFD_RELOC_ARM_LITERAL
3369 BFD_RELOC_ARM_IN_POOL
3371 BFD_RELOC_ARM_OFFSET_IMM8
3373 BFD_RELOC_ARM_T32_OFFSET_U8
3375 BFD_RELOC_ARM_T32_OFFSET_IMM
3377 BFD_RELOC_ARM_HWLITERAL
3379 BFD_RELOC_ARM_THUMB_ADD
3381 BFD_RELOC_ARM_THUMB_IMM
3383 BFD_RELOC_ARM_THUMB_SHIFT
3385 These relocs are only used within the ARM assembler. They are not
3386 (at present) written to any object files.
3389 BFD_RELOC_SH_PCDISP8BY2
3391 BFD_RELOC_SH_PCDISP12BY2
3399 BFD_RELOC_SH_DISP12BY2
3401 BFD_RELOC_SH_DISP12BY4
3403 BFD_RELOC_SH_DISP12BY8
3407 BFD_RELOC_SH_DISP20BY8
3411 BFD_RELOC_SH_IMM4BY2
3413 BFD_RELOC_SH_IMM4BY4
3417 BFD_RELOC_SH_IMM8BY2
3419 BFD_RELOC_SH_IMM8BY4
3421 BFD_RELOC_SH_PCRELIMM8BY2
3423 BFD_RELOC_SH_PCRELIMM8BY4
3425 BFD_RELOC_SH_SWITCH16
3427 BFD_RELOC_SH_SWITCH32
3441 BFD_RELOC_SH_LOOP_START
3443 BFD_RELOC_SH_LOOP_END
3447 BFD_RELOC_SH_GLOB_DAT
3449 BFD_RELOC_SH_JMP_SLOT
3451 BFD_RELOC_SH_RELATIVE
3455 BFD_RELOC_SH_GOT_LOW16
3457 BFD_RELOC_SH_GOT_MEDLOW16
3459 BFD_RELOC_SH_GOT_MEDHI16
3461 BFD_RELOC_SH_GOT_HI16
3463 BFD_RELOC_SH_GOTPLT_LOW16
3465 BFD_RELOC_SH_GOTPLT_MEDLOW16
3467 BFD_RELOC_SH_GOTPLT_MEDHI16
3469 BFD_RELOC_SH_GOTPLT_HI16
3471 BFD_RELOC_SH_PLT_LOW16
3473 BFD_RELOC_SH_PLT_MEDLOW16
3475 BFD_RELOC_SH_PLT_MEDHI16
3477 BFD_RELOC_SH_PLT_HI16
3479 BFD_RELOC_SH_GOTOFF_LOW16
3481 BFD_RELOC_SH_GOTOFF_MEDLOW16
3483 BFD_RELOC_SH_GOTOFF_MEDHI16
3485 BFD_RELOC_SH_GOTOFF_HI16
3487 BFD_RELOC_SH_GOTPC_LOW16
3489 BFD_RELOC_SH_GOTPC_MEDLOW16
3491 BFD_RELOC_SH_GOTPC_MEDHI16
3493 BFD_RELOC_SH_GOTPC_HI16
3497 BFD_RELOC_SH_GLOB_DAT64
3499 BFD_RELOC_SH_JMP_SLOT64
3501 BFD_RELOC_SH_RELATIVE64
3503 BFD_RELOC_SH_GOT10BY4
3505 BFD_RELOC_SH_GOT10BY8
3507 BFD_RELOC_SH_GOTPLT10BY4
3509 BFD_RELOC_SH_GOTPLT10BY8
3511 BFD_RELOC_SH_GOTPLT32
3513 BFD_RELOC_SH_SHMEDIA_CODE
3519 BFD_RELOC_SH_IMMS6BY32
3525 BFD_RELOC_SH_IMMS10BY2
3527 BFD_RELOC_SH_IMMS10BY4
3529 BFD_RELOC_SH_IMMS10BY8
3535 BFD_RELOC_SH_IMM_LOW16
3537 BFD_RELOC_SH_IMM_LOW16_PCREL
3539 BFD_RELOC_SH_IMM_MEDLOW16
3541 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3543 BFD_RELOC_SH_IMM_MEDHI16
3545 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3547 BFD_RELOC_SH_IMM_HI16
3549 BFD_RELOC_SH_IMM_HI16_PCREL
3553 BFD_RELOC_SH_TLS_GD_32
3555 BFD_RELOC_SH_TLS_LD_32
3557 BFD_RELOC_SH_TLS_LDO_32
3559 BFD_RELOC_SH_TLS_IE_32
3561 BFD_RELOC_SH_TLS_LE_32
3563 BFD_RELOC_SH_TLS_DTPMOD32
3565 BFD_RELOC_SH_TLS_DTPOFF32
3567 BFD_RELOC_SH_TLS_TPOFF32
3571 BFD_RELOC_SH_GOTOFF20
3573 BFD_RELOC_SH_GOTFUNCDESC
3575 BFD_RELOC_SH_GOTFUNCDESC20
3577 BFD_RELOC_SH_GOTOFFFUNCDESC
3579 BFD_RELOC_SH_GOTOFFFUNCDESC20
3581 BFD_RELOC_SH_FUNCDESC
3583 Renesas / SuperH SH relocs. Not all of these appear in object files.
3606 BFD_RELOC_ARC_SECTOFF
3608 BFD_RELOC_ARC_S21H_PCREL
3610 BFD_RELOC_ARC_S21W_PCREL
3612 BFD_RELOC_ARC_S25H_PCREL
3614 BFD_RELOC_ARC_S25W_PCREL
3618 BFD_RELOC_ARC_SDA_LDST
3620 BFD_RELOC_ARC_SDA_LDST1
3622 BFD_RELOC_ARC_SDA_LDST2
3624 BFD_RELOC_ARC_SDA16_LD
3626 BFD_RELOC_ARC_SDA16_LD1
3628 BFD_RELOC_ARC_SDA16_LD2
3630 BFD_RELOC_ARC_S13_PCREL
3636 BFD_RELOC_ARC_32_ME_S
3638 BFD_RELOC_ARC_N32_ME
3640 BFD_RELOC_ARC_SECTOFF_ME
3642 BFD_RELOC_ARC_SDA32_ME
3646 BFD_RELOC_AC_SECTOFF_U8
3648 BFD_RELOC_AC_SECTOFF_U8_1
3650 BFD_RELOC_AC_SECTOFF_U8_2
3652 BFD_RELOC_AC_SECTOFF_S9
3654 BFD_RELOC_AC_SECTOFF_S9_1
3656 BFD_RELOC_AC_SECTOFF_S9_2
3658 BFD_RELOC_ARC_SECTOFF_ME_1
3660 BFD_RELOC_ARC_SECTOFF_ME_2
3662 BFD_RELOC_ARC_SECTOFF_1
3664 BFD_RELOC_ARC_SECTOFF_2
3666 BFD_RELOC_ARC_SDA_12
3668 BFD_RELOC_ARC_SDA16_ST2
3670 BFD_RELOC_ARC_32_PCREL
3676 BFD_RELOC_ARC_GOTPC32
3682 BFD_RELOC_ARC_GLOB_DAT
3684 BFD_RELOC_ARC_JMP_SLOT
3686 BFD_RELOC_ARC_RELATIVE
3688 BFD_RELOC_ARC_GOTOFF
3692 BFD_RELOC_ARC_S21W_PCREL_PLT
3694 BFD_RELOC_ARC_S25H_PCREL_PLT
3696 BFD_RELOC_ARC_TLS_DTPMOD
3698 BFD_RELOC_ARC_TLS_TPOFF
3700 BFD_RELOC_ARC_TLS_GD_GOT
3702 BFD_RELOC_ARC_TLS_GD_LD
3704 BFD_RELOC_ARC_TLS_GD_CALL
3706 BFD_RELOC_ARC_TLS_IE_GOT
3708 BFD_RELOC_ARC_TLS_DTPOFF
3710 BFD_RELOC_ARC_TLS_DTPOFF_S9
3712 BFD_RELOC_ARC_TLS_LE_S9
3714 BFD_RELOC_ARC_TLS_LE_32
3716 BFD_RELOC_ARC_S25W_PCREL_PLT
3718 BFD_RELOC_ARC_S21H_PCREL_PLT
3720 BFD_RELOC_ARC_NPS_CMEM16
3722 BFD_RELOC_ARC_JLI_SECTOFF
3727 BFD_RELOC_BFIN_16_IMM
3729 ADI Blackfin 16 bit immediate absolute reloc.
3731 BFD_RELOC_BFIN_16_HIGH
3733 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3735 BFD_RELOC_BFIN_4_PCREL
3737 ADI Blackfin 'a' part of LSETUP.
3739 BFD_RELOC_BFIN_5_PCREL
3743 BFD_RELOC_BFIN_16_LOW
3745 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3747 BFD_RELOC_BFIN_10_PCREL
3751 BFD_RELOC_BFIN_11_PCREL
3753 ADI Blackfin 'b' part of LSETUP.
3755 BFD_RELOC_BFIN_12_PCREL_JUMP
3759 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3761 ADI Blackfin Short jump, pcrel.
3763 BFD_RELOC_BFIN_24_PCREL_CALL_X
3765 ADI Blackfin Call.x not implemented.
3767 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3769 ADI Blackfin Long Jump pcrel.
3771 BFD_RELOC_BFIN_GOT17M4
3773 BFD_RELOC_BFIN_GOTHI
3775 BFD_RELOC_BFIN_GOTLO
3777 BFD_RELOC_BFIN_FUNCDESC
3779 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3781 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3783 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3785 BFD_RELOC_BFIN_FUNCDESC_VALUE
3787 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3789 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3791 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3793 BFD_RELOC_BFIN_GOTOFF17M4
3795 BFD_RELOC_BFIN_GOTOFFHI
3797 BFD_RELOC_BFIN_GOTOFFLO
3799 ADI Blackfin FD-PIC relocations.
3803 ADI Blackfin GOT relocation.
3805 BFD_RELOC_BFIN_PLTPC
3807 ADI Blackfin PLTPC relocation.
3809 BFD_ARELOC_BFIN_PUSH
3811 ADI Blackfin arithmetic relocation.
3813 BFD_ARELOC_BFIN_CONST
3815 ADI Blackfin arithmetic relocation.
3819 ADI Blackfin arithmetic relocation.
3823 ADI Blackfin arithmetic relocation.
3825 BFD_ARELOC_BFIN_MULT
3827 ADI Blackfin arithmetic relocation.
3831 ADI Blackfin arithmetic relocation.
3835 ADI Blackfin arithmetic relocation.
3837 BFD_ARELOC_BFIN_LSHIFT
3839 ADI Blackfin arithmetic relocation.
3841 BFD_ARELOC_BFIN_RSHIFT
3843 ADI Blackfin arithmetic relocation.
3847 ADI Blackfin arithmetic relocation.
3851 ADI Blackfin arithmetic relocation.
3855 ADI Blackfin arithmetic relocation.
3857 BFD_ARELOC_BFIN_LAND
3859 ADI Blackfin arithmetic relocation.
3863 ADI Blackfin arithmetic relocation.
3867 ADI Blackfin arithmetic relocation.
3871 ADI Blackfin arithmetic relocation.
3873 BFD_ARELOC_BFIN_COMP
3875 ADI Blackfin arithmetic relocation.
3877 BFD_ARELOC_BFIN_PAGE
3879 ADI Blackfin arithmetic relocation.
3881 BFD_ARELOC_BFIN_HWPAGE
3883 ADI Blackfin arithmetic relocation.
3885 BFD_ARELOC_BFIN_ADDR
3887 ADI Blackfin arithmetic relocation.
3890 BFD_RELOC_D10V_10_PCREL_R
3892 Mitsubishi D10V relocs.
3893 This is a 10-bit reloc with the right 2 bits
3896 BFD_RELOC_D10V_10_PCREL_L
3898 Mitsubishi D10V relocs.
3899 This is a 10-bit reloc with the right 2 bits
3900 assumed to be 0. This is the same as the previous reloc
3901 except it is in the left container, i.e.,
3902 shifted left 15 bits.
3906 This is an 18-bit reloc with the right 2 bits
3909 BFD_RELOC_D10V_18_PCREL
3911 This is an 18-bit reloc with the right 2 bits
3917 Mitsubishi D30V relocs.
3918 This is a 6-bit absolute reloc.
3920 BFD_RELOC_D30V_9_PCREL
3922 This is a 6-bit pc-relative reloc with
3923 the right 3 bits assumed to be 0.
3925 BFD_RELOC_D30V_9_PCREL_R
3927 This is a 6-bit pc-relative reloc with
3928 the right 3 bits assumed to be 0. Same
3929 as the previous reloc but on the right side
3934 This is a 12-bit absolute reloc with the
3935 right 3 bitsassumed to be 0.
3937 BFD_RELOC_D30V_15_PCREL
3939 This is a 12-bit pc-relative reloc with
3940 the right 3 bits assumed to be 0.
3942 BFD_RELOC_D30V_15_PCREL_R
3944 This is a 12-bit pc-relative reloc with
3945 the right 3 bits assumed to be 0. Same
3946 as the previous reloc but on the right side
3951 This is an 18-bit absolute reloc with
3952 the right 3 bits assumed to be 0.
3954 BFD_RELOC_D30V_21_PCREL
3956 This is an 18-bit pc-relative reloc with
3957 the right 3 bits assumed to be 0.
3959 BFD_RELOC_D30V_21_PCREL_R
3961 This is an 18-bit pc-relative reloc with
3962 the right 3 bits assumed to be 0. Same
3963 as the previous reloc but on the right side
3968 This is a 32-bit absolute reloc.
3970 BFD_RELOC_D30V_32_PCREL
3972 This is a 32-bit pc-relative reloc.
3975 BFD_RELOC_DLX_HI16_S
3990 BFD_RELOC_M32C_RL_JUMP
3992 BFD_RELOC_M32C_RL_1ADDR
3994 BFD_RELOC_M32C_RL_2ADDR
3996 Renesas M16C/M32C Relocations.
4001 Renesas M32R (formerly Mitsubishi M32R) relocs.
4002 This is a 24 bit absolute address.
4004 BFD_RELOC_M32R_10_PCREL
4006 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
4008 BFD_RELOC_M32R_18_PCREL
4010 This is an 18-bit reloc with the right 2 bits assumed to be 0.
4012 BFD_RELOC_M32R_26_PCREL
4014 This is a 26-bit reloc with the right 2 bits assumed to be 0.
4016 BFD_RELOC_M32R_HI16_ULO
4018 This is a 16-bit reloc containing the high 16 bits of an address
4019 used when the lower 16 bits are treated as unsigned.
4021 BFD_RELOC_M32R_HI16_SLO
4023 This is a 16-bit reloc containing the high 16 bits of an address
4024 used when the lower 16 bits are treated as signed.
4028 This is a 16-bit reloc containing the lower 16 bits of an address.
4030 BFD_RELOC_M32R_SDA16
4032 This is a 16-bit reloc containing the small data area offset for use in
4033 add3, load, and store instructions.
4035 BFD_RELOC_M32R_GOT24
4037 BFD_RELOC_M32R_26_PLTREL
4041 BFD_RELOC_M32R_GLOB_DAT
4043 BFD_RELOC_M32R_JMP_SLOT
4045 BFD_RELOC_M32R_RELATIVE
4047 BFD_RELOC_M32R_GOTOFF
4049 BFD_RELOC_M32R_GOTOFF_HI_ULO
4051 BFD_RELOC_M32R_GOTOFF_HI_SLO
4053 BFD_RELOC_M32R_GOTOFF_LO
4055 BFD_RELOC_M32R_GOTPC24
4057 BFD_RELOC_M32R_GOT16_HI_ULO
4059 BFD_RELOC_M32R_GOT16_HI_SLO
4061 BFD_RELOC_M32R_GOT16_LO
4063 BFD_RELOC_M32R_GOTPC_HI_ULO
4065 BFD_RELOC_M32R_GOTPC_HI_SLO
4067 BFD_RELOC_M32R_GOTPC_LO
4076 This is a 20 bit absolute address.
4078 BFD_RELOC_NDS32_9_PCREL
4080 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4082 BFD_RELOC_NDS32_WORD_9_PCREL
4084 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4086 BFD_RELOC_NDS32_15_PCREL
4088 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4090 BFD_RELOC_NDS32_17_PCREL
4092 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4094 BFD_RELOC_NDS32_25_PCREL
4096 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4098 BFD_RELOC_NDS32_HI20
4100 This is a 20-bit reloc containing the high 20 bits of an address
4101 used with the lower 12 bits
4103 BFD_RELOC_NDS32_LO12S3
4105 This is a 12-bit reloc containing the lower 12 bits of an address
4106 then shift right by 3. This is used with ldi,sdi...
4108 BFD_RELOC_NDS32_LO12S2
4110 This is a 12-bit reloc containing the lower 12 bits of an address
4111 then shift left by 2. This is used with lwi,swi...
4113 BFD_RELOC_NDS32_LO12S1
4115 This is a 12-bit reloc containing the lower 12 bits of an address
4116 then shift left by 1. This is used with lhi,shi...
4118 BFD_RELOC_NDS32_LO12S0
4120 This is a 12-bit reloc containing the lower 12 bits of an address
4121 then shift left by 0. This is used with lbisbi...
4123 BFD_RELOC_NDS32_LO12S0_ORI
4125 This is a 12-bit reloc containing the lower 12 bits of an address
4126 then shift left by 0. This is only used with branch relaxations
4128 BFD_RELOC_NDS32_SDA15S3
4130 This is a 15-bit reloc containing the small data area 18-bit signed offset
4131 and shift left by 3 for use in ldi, sdi...
4133 BFD_RELOC_NDS32_SDA15S2
4135 This is a 15-bit reloc containing the small data area 17-bit signed offset
4136 and shift left by 2 for use in lwi, swi...
4138 BFD_RELOC_NDS32_SDA15S1
4140 This is a 15-bit reloc containing the small data area 16-bit signed offset
4141 and shift left by 1 for use in lhi, shi...
4143 BFD_RELOC_NDS32_SDA15S0
4145 This is a 15-bit reloc containing the small data area 15-bit signed offset
4146 and shift left by 0 for use in lbi, sbi...
4148 BFD_RELOC_NDS32_SDA16S3
4150 This is a 16-bit reloc containing the small data area 16-bit signed offset
4153 BFD_RELOC_NDS32_SDA17S2
4155 This is a 17-bit reloc containing the small data area 17-bit signed offset
4156 and shift left by 2 for use in lwi.gp, swi.gp...
4158 BFD_RELOC_NDS32_SDA18S1
4160 This is a 18-bit reloc containing the small data area 18-bit signed offset
4161 and shift left by 1 for use in lhi.gp, shi.gp...
4163 BFD_RELOC_NDS32_SDA19S0
4165 This is a 19-bit reloc containing the small data area 19-bit signed offset
4166 and shift left by 0 for use in lbi.gp, sbi.gp...
4168 BFD_RELOC_NDS32_GOT20
4170 BFD_RELOC_NDS32_9_PLTREL
4172 BFD_RELOC_NDS32_25_PLTREL
4174 BFD_RELOC_NDS32_COPY
4176 BFD_RELOC_NDS32_GLOB_DAT
4178 BFD_RELOC_NDS32_JMP_SLOT
4180 BFD_RELOC_NDS32_RELATIVE
4182 BFD_RELOC_NDS32_GOTOFF
4184 BFD_RELOC_NDS32_GOTOFF_HI20
4186 BFD_RELOC_NDS32_GOTOFF_LO12
4188 BFD_RELOC_NDS32_GOTPC20
4190 BFD_RELOC_NDS32_GOT_HI20
4192 BFD_RELOC_NDS32_GOT_LO12
4194 BFD_RELOC_NDS32_GOTPC_HI20
4196 BFD_RELOC_NDS32_GOTPC_LO12
4200 BFD_RELOC_NDS32_INSN16
4202 BFD_RELOC_NDS32_LABEL
4204 BFD_RELOC_NDS32_LONGCALL1
4206 BFD_RELOC_NDS32_LONGCALL2
4208 BFD_RELOC_NDS32_LONGCALL3
4210 BFD_RELOC_NDS32_LONGJUMP1
4212 BFD_RELOC_NDS32_LONGJUMP2
4214 BFD_RELOC_NDS32_LONGJUMP3
4216 BFD_RELOC_NDS32_LOADSTORE
4218 BFD_RELOC_NDS32_9_FIXED
4220 BFD_RELOC_NDS32_15_FIXED
4222 BFD_RELOC_NDS32_17_FIXED
4224 BFD_RELOC_NDS32_25_FIXED
4226 BFD_RELOC_NDS32_LONGCALL4
4228 BFD_RELOC_NDS32_LONGCALL5
4230 BFD_RELOC_NDS32_LONGCALL6
4232 BFD_RELOC_NDS32_LONGJUMP4
4234 BFD_RELOC_NDS32_LONGJUMP5
4236 BFD_RELOC_NDS32_LONGJUMP6
4238 BFD_RELOC_NDS32_LONGJUMP7
4242 BFD_RELOC_NDS32_PLTREL_HI20
4244 BFD_RELOC_NDS32_PLTREL_LO12
4246 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4248 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4252 BFD_RELOC_NDS32_SDA12S2_DP
4254 BFD_RELOC_NDS32_SDA12S2_SP
4256 BFD_RELOC_NDS32_LO12S2_DP
4258 BFD_RELOC_NDS32_LO12S2_SP
4262 BFD_RELOC_NDS32_DWARF2_OP1
4264 BFD_RELOC_NDS32_DWARF2_OP2
4266 BFD_RELOC_NDS32_DWARF2_LEB
4268 for dwarf2 debug_line.
4270 BFD_RELOC_NDS32_UPDATE_TA
4272 for eliminate 16-bit instructions
4274 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4276 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4278 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4280 BFD_RELOC_NDS32_GOT_LO15
4282 BFD_RELOC_NDS32_GOT_LO19
4284 BFD_RELOC_NDS32_GOTOFF_LO15
4286 BFD_RELOC_NDS32_GOTOFF_LO19
4288 BFD_RELOC_NDS32_GOT15S2
4290 BFD_RELOC_NDS32_GOT17S2
4292 for PIC object relaxation
4297 This is a 5 bit absolute address.
4299 BFD_RELOC_NDS32_10_UPCREL
4301 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4303 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4305 If fp were omitted, fp can used as another gp.
4307 BFD_RELOC_NDS32_RELAX_ENTRY
4309 BFD_RELOC_NDS32_GOT_SUFF
4311 BFD_RELOC_NDS32_GOTOFF_SUFF
4313 BFD_RELOC_NDS32_PLT_GOT_SUFF
4315 BFD_RELOC_NDS32_MULCALL_SUFF
4319 BFD_RELOC_NDS32_PTR_COUNT
4321 BFD_RELOC_NDS32_PTR_RESOLVED
4323 BFD_RELOC_NDS32_PLTBLOCK
4325 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4327 BFD_RELOC_NDS32_RELAX_REGION_END
4329 BFD_RELOC_NDS32_MINUEND
4331 BFD_RELOC_NDS32_SUBTRAHEND
4333 BFD_RELOC_NDS32_DIFF8
4335 BFD_RELOC_NDS32_DIFF16
4337 BFD_RELOC_NDS32_DIFF32
4339 BFD_RELOC_NDS32_DIFF_ULEB128
4341 BFD_RELOC_NDS32_EMPTY
4343 relaxation relative relocation types
4345 BFD_RELOC_NDS32_25_ABS
4347 This is a 25 bit absolute address.
4349 BFD_RELOC_NDS32_DATA
4351 BFD_RELOC_NDS32_TRAN
4353 BFD_RELOC_NDS32_17IFC_PCREL
4355 BFD_RELOC_NDS32_10IFCU_PCREL
4357 For ex9 and ifc using.
4359 BFD_RELOC_NDS32_TPOFF
4361 BFD_RELOC_NDS32_GOTTPOFF
4363 BFD_RELOC_NDS32_TLS_LE_HI20
4365 BFD_RELOC_NDS32_TLS_LE_LO12
4367 BFD_RELOC_NDS32_TLS_LE_20
4369 BFD_RELOC_NDS32_TLS_LE_15S0
4371 BFD_RELOC_NDS32_TLS_LE_15S1
4373 BFD_RELOC_NDS32_TLS_LE_15S2
4375 BFD_RELOC_NDS32_TLS_LE_ADD
4377 BFD_RELOC_NDS32_TLS_LE_LS
4379 BFD_RELOC_NDS32_TLS_IE_HI20
4381 BFD_RELOC_NDS32_TLS_IE_LO12
4383 BFD_RELOC_NDS32_TLS_IE_LO12S2
4385 BFD_RELOC_NDS32_TLS_IEGP_HI20
4387 BFD_RELOC_NDS32_TLS_IEGP_LO12
4389 BFD_RELOC_NDS32_TLS_IEGP_LO12S2
4391 BFD_RELOC_NDS32_TLS_IEGP_LW
4393 BFD_RELOC_NDS32_TLS_DESC
4395 BFD_RELOC_NDS32_TLS_DESC_HI20
4397 BFD_RELOC_NDS32_TLS_DESC_LO12
4399 BFD_RELOC_NDS32_TLS_DESC_20
4401 BFD_RELOC_NDS32_TLS_DESC_SDA17S2
4403 BFD_RELOC_NDS32_TLS_DESC_ADD
4405 BFD_RELOC_NDS32_TLS_DESC_FUNC
4407 BFD_RELOC_NDS32_TLS_DESC_CALL
4409 BFD_RELOC_NDS32_TLS_DESC_MEM
4411 BFD_RELOC_NDS32_REMOVE
4413 BFD_RELOC_NDS32_GROUP
4419 For floating load store relaxation.
4423 BFD_RELOC_V850_9_PCREL
4425 This is a 9-bit reloc
4427 BFD_RELOC_V850_22_PCREL
4429 This is a 22-bit reloc
4432 BFD_RELOC_V850_SDA_16_16_OFFSET
4434 This is a 16 bit offset from the short data area pointer.
4436 BFD_RELOC_V850_SDA_15_16_OFFSET
4438 This is a 16 bit offset (of which only 15 bits are used) from the
4439 short data area pointer.
4441 BFD_RELOC_V850_ZDA_16_16_OFFSET
4443 This is a 16 bit offset from the zero data area pointer.
4445 BFD_RELOC_V850_ZDA_15_16_OFFSET
4447 This is a 16 bit offset (of which only 15 bits are used) from the
4448 zero data area pointer.
4450 BFD_RELOC_V850_TDA_6_8_OFFSET
4452 This is an 8 bit offset (of which only 6 bits are used) from the
4453 tiny data area pointer.
4455 BFD_RELOC_V850_TDA_7_8_OFFSET
4457 This is an 8bit offset (of which only 7 bits are used) from the tiny
4460 BFD_RELOC_V850_TDA_7_7_OFFSET
4462 This is a 7 bit offset from the tiny data area pointer.
4464 BFD_RELOC_V850_TDA_16_16_OFFSET
4466 This is a 16 bit offset from the tiny data area pointer.
4469 BFD_RELOC_V850_TDA_4_5_OFFSET
4471 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4474 BFD_RELOC_V850_TDA_4_4_OFFSET
4476 This is a 4 bit offset from the tiny data area pointer.
4478 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4480 This is a 16 bit offset from the short data area pointer, with the
4481 bits placed non-contiguously in the instruction.
4483 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4485 This is a 16 bit offset from the zero data area pointer, with the
4486 bits placed non-contiguously in the instruction.
4488 BFD_RELOC_V850_CALLT_6_7_OFFSET
4490 This is a 6 bit offset from the call table base pointer.
4492 BFD_RELOC_V850_CALLT_16_16_OFFSET
4494 This is a 16 bit offset from the call table base pointer.
4496 BFD_RELOC_V850_LONGCALL
4498 Used for relaxing indirect function calls.
4500 BFD_RELOC_V850_LONGJUMP
4502 Used for relaxing indirect jumps.
4504 BFD_RELOC_V850_ALIGN
4506 Used to maintain alignment whilst relaxing.
4508 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4510 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4513 BFD_RELOC_V850_16_PCREL
4515 This is a 16-bit reloc.
4517 BFD_RELOC_V850_17_PCREL
4519 This is a 17-bit reloc.
4523 This is a 23-bit reloc.
4525 BFD_RELOC_V850_32_PCREL
4527 This is a 32-bit reloc.
4529 BFD_RELOC_V850_32_ABS
4531 This is a 32-bit reloc.
4533 BFD_RELOC_V850_16_SPLIT_OFFSET
4535 This is a 16-bit reloc.
4537 BFD_RELOC_V850_16_S1
4539 This is a 16-bit reloc.
4541 BFD_RELOC_V850_LO16_S1
4543 Low 16 bits. 16 bit shifted by 1.
4545 BFD_RELOC_V850_CALLT_15_16_OFFSET
4547 This is a 16 bit offset from the call table base pointer.
4549 BFD_RELOC_V850_32_GOTPCREL
4553 BFD_RELOC_V850_16_GOT
4557 BFD_RELOC_V850_32_GOT
4561 BFD_RELOC_V850_22_PLT_PCREL
4565 BFD_RELOC_V850_32_PLT_PCREL
4573 BFD_RELOC_V850_GLOB_DAT
4577 BFD_RELOC_V850_JMP_SLOT
4581 BFD_RELOC_V850_RELATIVE
4585 BFD_RELOC_V850_16_GOTOFF
4589 BFD_RELOC_V850_32_GOTOFF
4604 This is a 8bit DP reloc for the tms320c30, where the most
4605 significant 8 bits of a 24 bit word are placed into the least
4606 significant 8 bits of the opcode.
4609 BFD_RELOC_TIC54X_PARTLS7
4611 This is a 7bit reloc for the tms320c54x, where the least
4612 significant 7 bits of a 16 bit word are placed into the least
4613 significant 7 bits of the opcode.
4616 BFD_RELOC_TIC54X_PARTMS9
4618 This is a 9bit DP reloc for the tms320c54x, where the most
4619 significant 9 bits of a 16 bit word are placed into the least
4620 significant 9 bits of the opcode.
4625 This is an extended address 23-bit reloc for the tms320c54x.
4628 BFD_RELOC_TIC54X_16_OF_23
4630 This is a 16-bit reloc for the tms320c54x, where the least
4631 significant 16 bits of a 23-bit extended address are placed into
4635 BFD_RELOC_TIC54X_MS7_OF_23
4637 This is a reloc for the tms320c54x, where the most
4638 significant 7 bits of a 23-bit extended address are placed into
4642 BFD_RELOC_C6000_PCR_S21
4644 BFD_RELOC_C6000_PCR_S12
4646 BFD_RELOC_C6000_PCR_S10
4648 BFD_RELOC_C6000_PCR_S7
4650 BFD_RELOC_C6000_ABS_S16
4652 BFD_RELOC_C6000_ABS_L16
4654 BFD_RELOC_C6000_ABS_H16
4656 BFD_RELOC_C6000_SBR_U15_B
4658 BFD_RELOC_C6000_SBR_U15_H
4660 BFD_RELOC_C6000_SBR_U15_W
4662 BFD_RELOC_C6000_SBR_S16
4664 BFD_RELOC_C6000_SBR_L16_B
4666 BFD_RELOC_C6000_SBR_L16_H
4668 BFD_RELOC_C6000_SBR_L16_W
4670 BFD_RELOC_C6000_SBR_H16_B
4672 BFD_RELOC_C6000_SBR_H16_H
4674 BFD_RELOC_C6000_SBR_H16_W
4676 BFD_RELOC_C6000_SBR_GOT_U15_W
4678 BFD_RELOC_C6000_SBR_GOT_L16_W
4680 BFD_RELOC_C6000_SBR_GOT_H16_W
4682 BFD_RELOC_C6000_DSBT_INDEX
4684 BFD_RELOC_C6000_PREL31
4686 BFD_RELOC_C6000_COPY
4688 BFD_RELOC_C6000_JUMP_SLOT
4690 BFD_RELOC_C6000_EHTYPE
4692 BFD_RELOC_C6000_PCR_H16
4694 BFD_RELOC_C6000_PCR_L16
4696 BFD_RELOC_C6000_ALIGN
4698 BFD_RELOC_C6000_FPHEAD
4700 BFD_RELOC_C6000_NOCMP
4702 TMS320C6000 relocations.
4707 This is a 48 bit reloc for the FR30 that stores 32 bits.
4711 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4714 BFD_RELOC_FR30_6_IN_4
4716 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4719 BFD_RELOC_FR30_8_IN_8
4721 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4724 BFD_RELOC_FR30_9_IN_8
4726 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4729 BFD_RELOC_FR30_10_IN_8
4731 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4734 BFD_RELOC_FR30_9_PCREL
4736 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4737 short offset into 8 bits.
4739 BFD_RELOC_FR30_12_PCREL
4741 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4742 short offset into 11 bits.
4745 BFD_RELOC_MCORE_PCREL_IMM8BY4
4747 BFD_RELOC_MCORE_PCREL_IMM11BY2
4749 BFD_RELOC_MCORE_PCREL_IMM4BY2
4751 BFD_RELOC_MCORE_PCREL_32
4753 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4757 Motorola Mcore relocations.
4766 BFD_RELOC_MEP_PCREL8A2
4768 BFD_RELOC_MEP_PCREL12A2
4770 BFD_RELOC_MEP_PCREL17A2
4772 BFD_RELOC_MEP_PCREL24A2
4774 BFD_RELOC_MEP_PCABS24A2
4786 BFD_RELOC_MEP_TPREL7
4788 BFD_RELOC_MEP_TPREL7A2
4790 BFD_RELOC_MEP_TPREL7A4
4792 BFD_RELOC_MEP_UIMM24
4794 BFD_RELOC_MEP_ADDR24A4
4796 BFD_RELOC_MEP_GNU_VTINHERIT
4798 BFD_RELOC_MEP_GNU_VTENTRY
4800 Toshiba Media Processor Relocations.
4804 BFD_RELOC_METAG_HIADDR16
4806 BFD_RELOC_METAG_LOADDR16
4808 BFD_RELOC_METAG_RELBRANCH
4810 BFD_RELOC_METAG_GETSETOFF
4812 BFD_RELOC_METAG_HIOG
4814 BFD_RELOC_METAG_LOOG
4816 BFD_RELOC_METAG_REL8
4818 BFD_RELOC_METAG_REL16
4820 BFD_RELOC_METAG_HI16_GOTOFF
4822 BFD_RELOC_METAG_LO16_GOTOFF
4824 BFD_RELOC_METAG_GETSET_GOTOFF
4826 BFD_RELOC_METAG_GETSET_GOT
4828 BFD_RELOC_METAG_HI16_GOTPC
4830 BFD_RELOC_METAG_LO16_GOTPC
4832 BFD_RELOC_METAG_HI16_PLT
4834 BFD_RELOC_METAG_LO16_PLT
4836 BFD_RELOC_METAG_RELBRANCH_PLT
4838 BFD_RELOC_METAG_GOTOFF
4842 BFD_RELOC_METAG_COPY
4844 BFD_RELOC_METAG_JMP_SLOT
4846 BFD_RELOC_METAG_RELATIVE
4848 BFD_RELOC_METAG_GLOB_DAT
4850 BFD_RELOC_METAG_TLS_GD
4852 BFD_RELOC_METAG_TLS_LDM
4854 BFD_RELOC_METAG_TLS_LDO_HI16
4856 BFD_RELOC_METAG_TLS_LDO_LO16
4858 BFD_RELOC_METAG_TLS_LDO
4860 BFD_RELOC_METAG_TLS_IE
4862 BFD_RELOC_METAG_TLS_IENONPIC
4864 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4866 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4868 BFD_RELOC_METAG_TLS_TPOFF
4870 BFD_RELOC_METAG_TLS_DTPMOD
4872 BFD_RELOC_METAG_TLS_DTPOFF
4874 BFD_RELOC_METAG_TLS_LE
4876 BFD_RELOC_METAG_TLS_LE_HI16
4878 BFD_RELOC_METAG_TLS_LE_LO16
4880 Imagination Technologies Meta relocations.
4885 BFD_RELOC_MMIX_GETA_1
4887 BFD_RELOC_MMIX_GETA_2
4889 BFD_RELOC_MMIX_GETA_3
4891 These are relocations for the GETA instruction.
4893 BFD_RELOC_MMIX_CBRANCH
4895 BFD_RELOC_MMIX_CBRANCH_J
4897 BFD_RELOC_MMIX_CBRANCH_1
4899 BFD_RELOC_MMIX_CBRANCH_2
4901 BFD_RELOC_MMIX_CBRANCH_3
4903 These are relocations for a conditional branch instruction.
4905 BFD_RELOC_MMIX_PUSHJ
4907 BFD_RELOC_MMIX_PUSHJ_1
4909 BFD_RELOC_MMIX_PUSHJ_2
4911 BFD_RELOC_MMIX_PUSHJ_3
4913 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4915 These are relocations for the PUSHJ instruction.
4919 BFD_RELOC_MMIX_JMP_1
4921 BFD_RELOC_MMIX_JMP_2
4923 BFD_RELOC_MMIX_JMP_3
4925 These are relocations for the JMP instruction.
4927 BFD_RELOC_MMIX_ADDR19
4929 This is a relocation for a relative address as in a GETA instruction or
4932 BFD_RELOC_MMIX_ADDR27
4934 This is a relocation for a relative address as in a JMP instruction.
4936 BFD_RELOC_MMIX_REG_OR_BYTE
4938 This is a relocation for an instruction field that may be a general
4939 register or a value 0..255.
4943 This is a relocation for an instruction field that may be a general
4946 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4948 This is a relocation for two instruction fields holding a register and
4949 an offset, the equivalent of the relocation.
4951 BFD_RELOC_MMIX_LOCAL
4953 This relocation is an assertion that the expression is not allocated as
4954 a global register. It does not modify contents.
4957 BFD_RELOC_AVR_7_PCREL
4959 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4960 short offset into 7 bits.
4962 BFD_RELOC_AVR_13_PCREL
4964 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4965 short offset into 12 bits.
4969 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4970 program memory address) into 16 bits.
4972 BFD_RELOC_AVR_LO8_LDI
4974 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4975 data memory address) into 8 bit immediate value of LDI insn.
4977 BFD_RELOC_AVR_HI8_LDI
4979 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4980 of data memory address) into 8 bit immediate value of LDI insn.
4982 BFD_RELOC_AVR_HH8_LDI
4984 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4985 of program memory address) into 8 bit immediate value of LDI insn.
4987 BFD_RELOC_AVR_MS8_LDI
4989 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4990 of 32 bit value) into 8 bit immediate value of LDI insn.
4992 BFD_RELOC_AVR_LO8_LDI_NEG
4994 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4995 (usually data memory address) into 8 bit immediate value of SUBI insn.
4997 BFD_RELOC_AVR_HI8_LDI_NEG
4999 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5000 (high 8 bit of data memory address) into 8 bit immediate value of
5003 BFD_RELOC_AVR_HH8_LDI_NEG
5005 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5006 (most high 8 bit of program memory address) into 8 bit immediate value
5007 of LDI or SUBI insn.
5009 BFD_RELOC_AVR_MS8_LDI_NEG
5011 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
5012 of 32 bit value) into 8 bit immediate value of LDI insn.
5014 BFD_RELOC_AVR_LO8_LDI_PM
5016 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
5017 command address) into 8 bit immediate value of LDI insn.
5019 BFD_RELOC_AVR_LO8_LDI_GS
5021 This is a 16 bit reloc for the AVR that stores 8 bit value
5022 (command address) into 8 bit immediate value of LDI insn. If the address
5023 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5026 BFD_RELOC_AVR_HI8_LDI_PM
5028 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5029 of command address) into 8 bit immediate value of LDI insn.
5031 BFD_RELOC_AVR_HI8_LDI_GS
5033 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5034 of command address) into 8 bit immediate value of LDI insn. If the address
5035 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5038 BFD_RELOC_AVR_HH8_LDI_PM
5040 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5041 of command address) into 8 bit immediate value of LDI insn.
5043 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5045 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5046 (usually command address) into 8 bit immediate value of SUBI insn.
5048 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5050 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5051 (high 8 bit of 16 bit command address) into 8 bit immediate value
5054 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5056 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5057 (high 6 bit of 22 bit command address) into 8 bit immediate
5062 This is a 32 bit reloc for the AVR that stores 23 bit value
5067 This is a 16 bit reloc for the AVR that stores all needed bits
5068 for absolute addressing with ldi with overflow check to linktime
5072 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5075 BFD_RELOC_AVR_6_ADIW
5077 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5082 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5083 in .byte lo8(symbol)
5087 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5088 in .byte hi8(symbol)
5092 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5093 in .byte hlo8(symbol)
5097 BFD_RELOC_AVR_DIFF16
5099 BFD_RELOC_AVR_DIFF32
5101 AVR relocations to mark the difference of two local symbols.
5102 These are only needed to support linker relaxation and can be ignored
5103 when not relaxing. The field is set to the value of the difference
5104 assuming no relaxation. The relocation encodes the position of the
5105 second symbol so the linker can determine whether to adjust the field
5108 BFD_RELOC_AVR_LDS_STS_16
5110 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5111 lds and sts instructions supported only tiny core.
5115 This is a 6 bit reloc for the AVR that stores an I/O register
5116 number for the IN and OUT instructions
5120 This is a 5 bit reloc for the AVR that stores an I/O register
5121 number for the SBIC, SBIS, SBI and CBI instructions
5124 BFD_RELOC_RISCV_HI20
5126 BFD_RELOC_RISCV_PCREL_HI20
5128 BFD_RELOC_RISCV_PCREL_LO12_I
5130 BFD_RELOC_RISCV_PCREL_LO12_S
5132 BFD_RELOC_RISCV_LO12_I
5134 BFD_RELOC_RISCV_LO12_S
5136 BFD_RELOC_RISCV_GPREL12_I
5138 BFD_RELOC_RISCV_GPREL12_S
5140 BFD_RELOC_RISCV_TPREL_HI20
5142 BFD_RELOC_RISCV_TPREL_LO12_I
5144 BFD_RELOC_RISCV_TPREL_LO12_S
5146 BFD_RELOC_RISCV_TPREL_ADD
5148 BFD_RELOC_RISCV_CALL
5150 BFD_RELOC_RISCV_CALL_PLT
5152 BFD_RELOC_RISCV_ADD8
5154 BFD_RELOC_RISCV_ADD16
5156 BFD_RELOC_RISCV_ADD32
5158 BFD_RELOC_RISCV_ADD64
5160 BFD_RELOC_RISCV_SUB8
5162 BFD_RELOC_RISCV_SUB16
5164 BFD_RELOC_RISCV_SUB32
5166 BFD_RELOC_RISCV_SUB64
5168 BFD_RELOC_RISCV_GOT_HI20
5170 BFD_RELOC_RISCV_TLS_GOT_HI20
5172 BFD_RELOC_RISCV_TLS_GD_HI20
5176 BFD_RELOC_RISCV_TLS_DTPMOD32
5178 BFD_RELOC_RISCV_TLS_DTPREL32
5180 BFD_RELOC_RISCV_TLS_DTPMOD64
5182 BFD_RELOC_RISCV_TLS_DTPREL64
5184 BFD_RELOC_RISCV_TLS_TPREL32
5186 BFD_RELOC_RISCV_TLS_TPREL64
5188 BFD_RELOC_RISCV_ALIGN
5190 BFD_RELOC_RISCV_RVC_BRANCH
5192 BFD_RELOC_RISCV_RVC_JUMP
5194 BFD_RELOC_RISCV_RVC_LUI
5196 BFD_RELOC_RISCV_GPREL_I
5198 BFD_RELOC_RISCV_GPREL_S
5200 BFD_RELOC_RISCV_TPREL_I
5202 BFD_RELOC_RISCV_TPREL_S
5204 BFD_RELOC_RISCV_RELAX
5208 BFD_RELOC_RISCV_SUB6
5210 BFD_RELOC_RISCV_SET6
5212 BFD_RELOC_RISCV_SET8
5214 BFD_RELOC_RISCV_SET16
5216 BFD_RELOC_RISCV_SET32
5218 BFD_RELOC_RISCV_32_PCREL
5225 BFD_RELOC_RL78_NEG16
5227 BFD_RELOC_RL78_NEG24
5229 BFD_RELOC_RL78_NEG32
5231 BFD_RELOC_RL78_16_OP
5233 BFD_RELOC_RL78_24_OP
5235 BFD_RELOC_RL78_32_OP
5243 BFD_RELOC_RL78_DIR3U_PCREL
5247 BFD_RELOC_RL78_GPRELB
5249 BFD_RELOC_RL78_GPRELW
5251 BFD_RELOC_RL78_GPRELL
5255 BFD_RELOC_RL78_OP_SUBTRACT
5257 BFD_RELOC_RL78_OP_NEG
5259 BFD_RELOC_RL78_OP_AND
5261 BFD_RELOC_RL78_OP_SHRA
5265 BFD_RELOC_RL78_ABS16
5267 BFD_RELOC_RL78_ABS16_REV
5269 BFD_RELOC_RL78_ABS32
5271 BFD_RELOC_RL78_ABS32_REV
5273 BFD_RELOC_RL78_ABS16U
5275 BFD_RELOC_RL78_ABS16UW
5277 BFD_RELOC_RL78_ABS16UL
5279 BFD_RELOC_RL78_RELAX
5289 BFD_RELOC_RL78_SADDR
5291 Renesas RL78 Relocations.
5314 BFD_RELOC_RX_DIR3U_PCREL
5326 BFD_RELOC_RX_OP_SUBTRACT
5334 BFD_RELOC_RX_ABS16_REV
5338 BFD_RELOC_RX_ABS32_REV
5342 BFD_RELOC_RX_ABS16UW
5344 BFD_RELOC_RX_ABS16UL
5348 Renesas RX Relocations.
5361 32 bit PC relative PLT address.
5365 Copy symbol at runtime.
5367 BFD_RELOC_390_GLOB_DAT
5371 BFD_RELOC_390_JMP_SLOT
5375 BFD_RELOC_390_RELATIVE
5377 Adjust by program base.
5381 32 bit PC relative offset to GOT.
5387 BFD_RELOC_390_PC12DBL
5389 PC relative 12 bit shifted by 1.
5391 BFD_RELOC_390_PLT12DBL
5393 12 bit PC rel. PLT shifted by 1.
5395 BFD_RELOC_390_PC16DBL
5397 PC relative 16 bit shifted by 1.
5399 BFD_RELOC_390_PLT16DBL
5401 16 bit PC rel. PLT shifted by 1.
5403 BFD_RELOC_390_PC24DBL
5405 PC relative 24 bit shifted by 1.
5407 BFD_RELOC_390_PLT24DBL
5409 24 bit PC rel. PLT shifted by 1.
5411 BFD_RELOC_390_PC32DBL
5413 PC relative 32 bit shifted by 1.
5415 BFD_RELOC_390_PLT32DBL
5417 32 bit PC rel. PLT shifted by 1.
5419 BFD_RELOC_390_GOTPCDBL
5421 32 bit PC rel. GOT shifted by 1.
5429 64 bit PC relative PLT address.
5431 BFD_RELOC_390_GOTENT
5433 32 bit rel. offset to GOT entry.
5435 BFD_RELOC_390_GOTOFF64
5437 64 bit offset to GOT.
5439 BFD_RELOC_390_GOTPLT12
5441 12-bit offset to symbol-entry within GOT, with PLT handling.
5443 BFD_RELOC_390_GOTPLT16
5445 16-bit offset to symbol-entry within GOT, with PLT handling.
5447 BFD_RELOC_390_GOTPLT32
5449 32-bit offset to symbol-entry within GOT, with PLT handling.
5451 BFD_RELOC_390_GOTPLT64
5453 64-bit offset to symbol-entry within GOT, with PLT handling.
5455 BFD_RELOC_390_GOTPLTENT
5457 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5459 BFD_RELOC_390_PLTOFF16
5461 16-bit rel. offset from the GOT to a PLT entry.
5463 BFD_RELOC_390_PLTOFF32
5465 32-bit rel. offset from the GOT to a PLT entry.
5467 BFD_RELOC_390_PLTOFF64
5469 64-bit rel. offset from the GOT to a PLT entry.
5472 BFD_RELOC_390_TLS_LOAD
5474 BFD_RELOC_390_TLS_GDCALL
5476 BFD_RELOC_390_TLS_LDCALL
5478 BFD_RELOC_390_TLS_GD32
5480 BFD_RELOC_390_TLS_GD64
5482 BFD_RELOC_390_TLS_GOTIE12
5484 BFD_RELOC_390_TLS_GOTIE32
5486 BFD_RELOC_390_TLS_GOTIE64
5488 BFD_RELOC_390_TLS_LDM32
5490 BFD_RELOC_390_TLS_LDM64
5492 BFD_RELOC_390_TLS_IE32
5494 BFD_RELOC_390_TLS_IE64
5496 BFD_RELOC_390_TLS_IEENT
5498 BFD_RELOC_390_TLS_LE32
5500 BFD_RELOC_390_TLS_LE64
5502 BFD_RELOC_390_TLS_LDO32
5504 BFD_RELOC_390_TLS_LDO64
5506 BFD_RELOC_390_TLS_DTPMOD
5508 BFD_RELOC_390_TLS_DTPOFF
5510 BFD_RELOC_390_TLS_TPOFF
5512 s390 tls relocations.
5519 BFD_RELOC_390_GOTPLT20
5521 BFD_RELOC_390_TLS_GOTIE20
5523 Long displacement extension.
5526 BFD_RELOC_390_IRELATIVE
5528 STT_GNU_IFUNC relocation.
5531 BFD_RELOC_SCORE_GPREL15
5534 Low 16 bit for load/store
5536 BFD_RELOC_SCORE_DUMMY2
5540 This is a 24-bit reloc with the right 1 bit assumed to be 0
5542 BFD_RELOC_SCORE_BRANCH
5544 This is a 19-bit reloc with the right 1 bit assumed to be 0
5546 BFD_RELOC_SCORE_IMM30
5548 This is a 32-bit reloc for 48-bit instructions.
5550 BFD_RELOC_SCORE_IMM32
5552 This is a 32-bit reloc for 48-bit instructions.
5554 BFD_RELOC_SCORE16_JMP
5556 This is a 11-bit reloc with the right 1 bit assumed to be 0
5558 BFD_RELOC_SCORE16_BRANCH
5560 This is a 8-bit reloc with the right 1 bit assumed to be 0
5562 BFD_RELOC_SCORE_BCMP
5564 This is a 9-bit reloc with the right 1 bit assumed to be 0
5566 BFD_RELOC_SCORE_GOT15
5568 BFD_RELOC_SCORE_GOT_LO16
5570 BFD_RELOC_SCORE_CALL15
5572 BFD_RELOC_SCORE_DUMMY_HI16
5574 Undocumented Score relocs
5579 Scenix IP2K - 9-bit register number / data address
5583 Scenix IP2K - 4-bit register/data bank number
5585 BFD_RELOC_IP2K_ADDR16CJP
5587 Scenix IP2K - low 13 bits of instruction word address
5589 BFD_RELOC_IP2K_PAGE3
5591 Scenix IP2K - high 3 bits of instruction word address
5593 BFD_RELOC_IP2K_LO8DATA
5595 BFD_RELOC_IP2K_HI8DATA
5597 BFD_RELOC_IP2K_EX8DATA
5599 Scenix IP2K - ext/low/high 8 bits of data address
5601 BFD_RELOC_IP2K_LO8INSN
5603 BFD_RELOC_IP2K_HI8INSN
5605 Scenix IP2K - low/high 8 bits of instruction word address
5607 BFD_RELOC_IP2K_PC_SKIP
5609 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5613 Scenix IP2K - 16 bit word address in text section.
5615 BFD_RELOC_IP2K_FR_OFFSET
5617 Scenix IP2K - 7-bit sp or dp offset
5619 BFD_RELOC_VPE4KMATH_DATA
5621 BFD_RELOC_VPE4KMATH_INSN
5623 Scenix VPE4K coprocessor - data/insn-space addressing
5626 BFD_RELOC_VTABLE_INHERIT
5628 BFD_RELOC_VTABLE_ENTRY
5630 These two relocations are used by the linker to determine which of
5631 the entries in a C++ virtual function table are actually used. When
5632 the --gc-sections option is given, the linker will zero out the entries
5633 that are not used, so that the code for those functions need not be
5634 included in the output.
5636 VTABLE_INHERIT is a zero-space relocation used to describe to the
5637 linker the inheritance tree of a C++ virtual function table. The
5638 relocation's symbol should be the parent class' vtable, and the
5639 relocation should be located at the child vtable.
5641 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5642 virtual function table entry. The reloc's symbol should refer to the
5643 table of the class mentioned in the code. Off of that base, an offset
5644 describes the entry that is being used. For Rela hosts, this offset
5645 is stored in the reloc's addend. For Rel hosts, we are forced to put
5646 this offset in the reloc's section offset.
5649 BFD_RELOC_IA64_IMM14
5651 BFD_RELOC_IA64_IMM22
5653 BFD_RELOC_IA64_IMM64
5655 BFD_RELOC_IA64_DIR32MSB
5657 BFD_RELOC_IA64_DIR32LSB
5659 BFD_RELOC_IA64_DIR64MSB
5661 BFD_RELOC_IA64_DIR64LSB
5663 BFD_RELOC_IA64_GPREL22
5665 BFD_RELOC_IA64_GPREL64I
5667 BFD_RELOC_IA64_GPREL32MSB
5669 BFD_RELOC_IA64_GPREL32LSB
5671 BFD_RELOC_IA64_GPREL64MSB
5673 BFD_RELOC_IA64_GPREL64LSB
5675 BFD_RELOC_IA64_LTOFF22
5677 BFD_RELOC_IA64_LTOFF64I
5679 BFD_RELOC_IA64_PLTOFF22
5681 BFD_RELOC_IA64_PLTOFF64I
5683 BFD_RELOC_IA64_PLTOFF64MSB
5685 BFD_RELOC_IA64_PLTOFF64LSB
5687 BFD_RELOC_IA64_FPTR64I
5689 BFD_RELOC_IA64_FPTR32MSB
5691 BFD_RELOC_IA64_FPTR32LSB
5693 BFD_RELOC_IA64_FPTR64MSB
5695 BFD_RELOC_IA64_FPTR64LSB
5697 BFD_RELOC_IA64_PCREL21B
5699 BFD_RELOC_IA64_PCREL21BI
5701 BFD_RELOC_IA64_PCREL21M
5703 BFD_RELOC_IA64_PCREL21F
5705 BFD_RELOC_IA64_PCREL22
5707 BFD_RELOC_IA64_PCREL60B
5709 BFD_RELOC_IA64_PCREL64I
5711 BFD_RELOC_IA64_PCREL32MSB
5713 BFD_RELOC_IA64_PCREL32LSB
5715 BFD_RELOC_IA64_PCREL64MSB
5717 BFD_RELOC_IA64_PCREL64LSB
5719 BFD_RELOC_IA64_LTOFF_FPTR22
5721 BFD_RELOC_IA64_LTOFF_FPTR64I
5723 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5725 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5727 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5729 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5731 BFD_RELOC_IA64_SEGREL32MSB
5733 BFD_RELOC_IA64_SEGREL32LSB
5735 BFD_RELOC_IA64_SEGREL64MSB
5737 BFD_RELOC_IA64_SEGREL64LSB
5739 BFD_RELOC_IA64_SECREL32MSB
5741 BFD_RELOC_IA64_SECREL32LSB
5743 BFD_RELOC_IA64_SECREL64MSB
5745 BFD_RELOC_IA64_SECREL64LSB
5747 BFD_RELOC_IA64_REL32MSB
5749 BFD_RELOC_IA64_REL32LSB
5751 BFD_RELOC_IA64_REL64MSB
5753 BFD_RELOC_IA64_REL64LSB
5755 BFD_RELOC_IA64_LTV32MSB
5757 BFD_RELOC_IA64_LTV32LSB
5759 BFD_RELOC_IA64_LTV64MSB
5761 BFD_RELOC_IA64_LTV64LSB
5763 BFD_RELOC_IA64_IPLTMSB
5765 BFD_RELOC_IA64_IPLTLSB
5769 BFD_RELOC_IA64_LTOFF22X
5771 BFD_RELOC_IA64_LDXMOV
5773 BFD_RELOC_IA64_TPREL14
5775 BFD_RELOC_IA64_TPREL22
5777 BFD_RELOC_IA64_TPREL64I
5779 BFD_RELOC_IA64_TPREL64MSB
5781 BFD_RELOC_IA64_TPREL64LSB
5783 BFD_RELOC_IA64_LTOFF_TPREL22
5785 BFD_RELOC_IA64_DTPMOD64MSB
5787 BFD_RELOC_IA64_DTPMOD64LSB
5789 BFD_RELOC_IA64_LTOFF_DTPMOD22
5791 BFD_RELOC_IA64_DTPREL14
5793 BFD_RELOC_IA64_DTPREL22
5795 BFD_RELOC_IA64_DTPREL64I
5797 BFD_RELOC_IA64_DTPREL32MSB
5799 BFD_RELOC_IA64_DTPREL32LSB
5801 BFD_RELOC_IA64_DTPREL64MSB
5803 BFD_RELOC_IA64_DTPREL64LSB
5805 BFD_RELOC_IA64_LTOFF_DTPREL22
5807 Intel IA64 Relocations.
5810 BFD_RELOC_M68HC11_HI8
5812 Motorola 68HC11 reloc.
5813 This is the 8 bit high part of an absolute address.
5815 BFD_RELOC_M68HC11_LO8
5817 Motorola 68HC11 reloc.
5818 This is the 8 bit low part of an absolute address.
5820 BFD_RELOC_M68HC11_3B
5822 Motorola 68HC11 reloc.
5823 This is the 3 bit of a value.
5825 BFD_RELOC_M68HC11_RL_JUMP
5827 Motorola 68HC11 reloc.
5828 This reloc marks the beginning of a jump/call instruction.
5829 It is used for linker relaxation to correctly identify beginning
5830 of instruction and change some branches to use PC-relative
5833 BFD_RELOC_M68HC11_RL_GROUP
5835 Motorola 68HC11 reloc.
5836 This reloc marks a group of several instructions that gcc generates
5837 and for which the linker relaxation pass can modify and/or remove
5840 BFD_RELOC_M68HC11_LO16
5842 Motorola 68HC11 reloc.
5843 This is the 16-bit lower part of an address. It is used for 'call'
5844 instruction to specify the symbol address without any special
5845 transformation (due to memory bank window).
5847 BFD_RELOC_M68HC11_PAGE
5849 Motorola 68HC11 reloc.
5850 This is a 8-bit reloc that specifies the page number of an address.
5851 It is used by 'call' instruction to specify the page number of
5854 BFD_RELOC_M68HC11_24
5856 Motorola 68HC11 reloc.
5857 This is a 24-bit reloc that represents the address with a 16-bit
5858 value and a 8-bit page number. The symbol address is transformed
5859 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5861 BFD_RELOC_M68HC12_5B
5863 Motorola 68HC12 reloc.
5864 This is the 5 bits of a value.
5866 BFD_RELOC_XGATE_RL_JUMP
5868 Freescale XGATE reloc.
5869 This reloc marks the beginning of a bra/jal instruction.
5871 BFD_RELOC_XGATE_RL_GROUP
5873 Freescale XGATE reloc.
5874 This reloc marks a group of several instructions that gcc generates
5875 and for which the linker relaxation pass can modify and/or remove
5878 BFD_RELOC_XGATE_LO16
5880 Freescale XGATE reloc.
5881 This is the 16-bit lower part of an address. It is used for the '16-bit'
5884 BFD_RELOC_XGATE_GPAGE
5886 Freescale XGATE reloc.
5890 Freescale XGATE reloc.
5892 BFD_RELOC_XGATE_PCREL_9
5894 Freescale XGATE reloc.
5895 This is a 9-bit pc-relative reloc.
5897 BFD_RELOC_XGATE_PCREL_10
5899 Freescale XGATE reloc.
5900 This is a 10-bit pc-relative reloc.
5902 BFD_RELOC_XGATE_IMM8_LO
5904 Freescale XGATE reloc.
5905 This is the 16-bit lower part of an address. It is used for the '16-bit'
5908 BFD_RELOC_XGATE_IMM8_HI
5910 Freescale XGATE reloc.
5911 This is the 16-bit higher part of an address. It is used for the '16-bit'
5914 BFD_RELOC_XGATE_IMM3
5916 Freescale XGATE reloc.
5917 This is a 3-bit pc-relative reloc.
5919 BFD_RELOC_XGATE_IMM4
5921 Freescale XGATE reloc.
5922 This is a 4-bit pc-relative reloc.
5924 BFD_RELOC_XGATE_IMM5
5926 Freescale XGATE reloc.
5927 This is a 5-bit pc-relative reloc.
5929 BFD_RELOC_M68HC12_9B
5931 Motorola 68HC12 reloc.
5932 This is the 9 bits of a value.
5934 BFD_RELOC_M68HC12_16B
5936 Motorola 68HC12 reloc.
5937 This is the 16 bits of a value.
5939 BFD_RELOC_M68HC12_9_PCREL
5941 Motorola 68HC12/XGATE reloc.
5942 This is a PCREL9 branch.
5944 BFD_RELOC_M68HC12_10_PCREL
5946 Motorola 68HC12/XGATE reloc.
5947 This is a PCREL10 branch.
5949 BFD_RELOC_M68HC12_LO8XG
5951 Motorola 68HC12/XGATE reloc.
5952 This is the 8 bit low part of an absolute address and immediately precedes
5953 a matching HI8XG part.
5955 BFD_RELOC_M68HC12_HI8XG
5957 Motorola 68HC12/XGATE reloc.
5958 This is the 8 bit high part of an absolute address and immediately follows
5959 a matching LO8XG part.
5961 BFD_RELOC_S12Z_15_PCREL
5963 Freescale S12Z reloc.
5964 This is a 15 bit relative address. If the most significant bits are all zero
5965 then it may be truncated to 8 bits.
5970 BFD_RELOC_CR16_NUM16
5972 BFD_RELOC_CR16_NUM32
5974 BFD_RELOC_CR16_NUM32a
5976 BFD_RELOC_CR16_REGREL0
5978 BFD_RELOC_CR16_REGREL4
5980 BFD_RELOC_CR16_REGREL4a
5982 BFD_RELOC_CR16_REGREL14
5984 BFD_RELOC_CR16_REGREL14a
5986 BFD_RELOC_CR16_REGREL16
5988 BFD_RELOC_CR16_REGREL20
5990 BFD_RELOC_CR16_REGREL20a
5992 BFD_RELOC_CR16_ABS20
5994 BFD_RELOC_CR16_ABS24
6000 BFD_RELOC_CR16_IMM16
6002 BFD_RELOC_CR16_IMM20
6004 BFD_RELOC_CR16_IMM24
6006 BFD_RELOC_CR16_IMM32
6008 BFD_RELOC_CR16_IMM32a
6010 BFD_RELOC_CR16_DISP4
6012 BFD_RELOC_CR16_DISP8
6014 BFD_RELOC_CR16_DISP16
6016 BFD_RELOC_CR16_DISP20
6018 BFD_RELOC_CR16_DISP24
6020 BFD_RELOC_CR16_DISP24a
6022 BFD_RELOC_CR16_SWITCH8
6024 BFD_RELOC_CR16_SWITCH16
6026 BFD_RELOC_CR16_SWITCH32
6028 BFD_RELOC_CR16_GOT_REGREL20
6030 BFD_RELOC_CR16_GOTC_REGREL20
6032 BFD_RELOC_CR16_GLOB_DAT
6034 NS CR16 Relocations.
6041 BFD_RELOC_CRX_REL8_CMP
6049 BFD_RELOC_CRX_REGREL12
6051 BFD_RELOC_CRX_REGREL22
6053 BFD_RELOC_CRX_REGREL28
6055 BFD_RELOC_CRX_REGREL32
6071 BFD_RELOC_CRX_SWITCH8
6073 BFD_RELOC_CRX_SWITCH16
6075 BFD_RELOC_CRX_SWITCH32
6080 BFD_RELOC_CRIS_BDISP8
6082 BFD_RELOC_CRIS_UNSIGNED_5
6084 BFD_RELOC_CRIS_SIGNED_6
6086 BFD_RELOC_CRIS_UNSIGNED_6
6088 BFD_RELOC_CRIS_SIGNED_8
6090 BFD_RELOC_CRIS_UNSIGNED_8
6092 BFD_RELOC_CRIS_SIGNED_16
6094 BFD_RELOC_CRIS_UNSIGNED_16
6096 BFD_RELOC_CRIS_LAPCQ_OFFSET
6098 BFD_RELOC_CRIS_UNSIGNED_4
6100 These relocs are only used within the CRIS assembler. They are not
6101 (at present) written to any object files.
6105 BFD_RELOC_CRIS_GLOB_DAT
6107 BFD_RELOC_CRIS_JUMP_SLOT
6109 BFD_RELOC_CRIS_RELATIVE
6111 Relocs used in ELF shared libraries for CRIS.
6113 BFD_RELOC_CRIS_32_GOT
6115 32-bit offset to symbol-entry within GOT.
6117 BFD_RELOC_CRIS_16_GOT
6119 16-bit offset to symbol-entry within GOT.
6121 BFD_RELOC_CRIS_32_GOTPLT
6123 32-bit offset to symbol-entry within GOT, with PLT handling.
6125 BFD_RELOC_CRIS_16_GOTPLT
6127 16-bit offset to symbol-entry within GOT, with PLT handling.
6129 BFD_RELOC_CRIS_32_GOTREL
6131 32-bit offset to symbol, relative to GOT.
6133 BFD_RELOC_CRIS_32_PLT_GOTREL
6135 32-bit offset to symbol with PLT entry, relative to GOT.
6137 BFD_RELOC_CRIS_32_PLT_PCREL
6139 32-bit offset to symbol with PLT entry, relative to this relocation.
6142 BFD_RELOC_CRIS_32_GOT_GD
6144 BFD_RELOC_CRIS_16_GOT_GD
6146 BFD_RELOC_CRIS_32_GD
6150 BFD_RELOC_CRIS_32_DTPREL
6152 BFD_RELOC_CRIS_16_DTPREL
6154 BFD_RELOC_CRIS_32_GOT_TPREL
6156 BFD_RELOC_CRIS_16_GOT_TPREL
6158 BFD_RELOC_CRIS_32_TPREL
6160 BFD_RELOC_CRIS_16_TPREL
6162 BFD_RELOC_CRIS_DTPMOD
6164 BFD_RELOC_CRIS_32_IE
6166 Relocs used in TLS code for CRIS.
6169 BFD_RELOC_OR1K_REL_26
6171 BFD_RELOC_OR1K_SLO16
6173 BFD_RELOC_OR1K_PCREL_PG21
6177 BFD_RELOC_OR1K_SLO13
6179 BFD_RELOC_OR1K_GOTPC_HI16
6181 BFD_RELOC_OR1K_GOTPC_LO16
6183 BFD_RELOC_OR1K_GOT16
6185 BFD_RELOC_OR1K_GOT_PG21
6187 BFD_RELOC_OR1K_GOT_LO13
6189 BFD_RELOC_OR1K_PLT26
6191 BFD_RELOC_OR1K_PLTA26
6193 BFD_RELOC_OR1K_GOTOFF_SLO16
6197 BFD_RELOC_OR1K_GLOB_DAT
6199 BFD_RELOC_OR1K_JMP_SLOT
6201 BFD_RELOC_OR1K_RELATIVE
6203 BFD_RELOC_OR1K_TLS_GD_HI16
6205 BFD_RELOC_OR1K_TLS_GD_LO16
6207 BFD_RELOC_OR1K_TLS_GD_PG21
6209 BFD_RELOC_OR1K_TLS_GD_LO13
6211 BFD_RELOC_OR1K_TLS_LDM_HI16
6213 BFD_RELOC_OR1K_TLS_LDM_LO16
6215 BFD_RELOC_OR1K_TLS_LDM_PG21
6217 BFD_RELOC_OR1K_TLS_LDM_LO13
6219 BFD_RELOC_OR1K_TLS_LDO_HI16
6221 BFD_RELOC_OR1K_TLS_LDO_LO16
6223 BFD_RELOC_OR1K_TLS_IE_HI16
6225 BFD_RELOC_OR1K_TLS_IE_AHI16
6227 BFD_RELOC_OR1K_TLS_IE_LO16
6229 BFD_RELOC_OR1K_TLS_IE_PG21
6231 BFD_RELOC_OR1K_TLS_IE_LO13
6233 BFD_RELOC_OR1K_TLS_LE_HI16
6235 BFD_RELOC_OR1K_TLS_LE_AHI16
6237 BFD_RELOC_OR1K_TLS_LE_LO16
6239 BFD_RELOC_OR1K_TLS_LE_SLO16
6241 BFD_RELOC_OR1K_TLS_TPOFF
6243 BFD_RELOC_OR1K_TLS_DTPOFF
6245 BFD_RELOC_OR1K_TLS_DTPMOD
6247 OpenRISC 1000 Relocations.
6250 BFD_RELOC_H8_DIR16A8
6252 BFD_RELOC_H8_DIR16R8
6254 BFD_RELOC_H8_DIR24A8
6256 BFD_RELOC_H8_DIR24R8
6258 BFD_RELOC_H8_DIR32A16
6260 BFD_RELOC_H8_DISP32A16
6265 BFD_RELOC_XSTORMY16_REL_12
6267 BFD_RELOC_XSTORMY16_12
6269 BFD_RELOC_XSTORMY16_24
6271 BFD_RELOC_XSTORMY16_FPTR16
6273 Sony Xstormy16 Relocations.
6278 Self-describing complex relocations.
6290 Infineon Relocations.
6293 BFD_RELOC_VAX_GLOB_DAT
6295 BFD_RELOC_VAX_JMP_SLOT
6297 BFD_RELOC_VAX_RELATIVE
6299 Relocations used by VAX ELF.
6304 Morpho MT - 16 bit immediate relocation.
6308 Morpho MT - Hi 16 bits of an address.
6312 Morpho MT - Low 16 bits of an address.
6314 BFD_RELOC_MT_GNU_VTINHERIT
6316 Morpho MT - Used to tell the linker which vtable entries are used.
6318 BFD_RELOC_MT_GNU_VTENTRY
6320 Morpho MT - Used to tell the linker which vtable entries are used.
6322 BFD_RELOC_MT_PCINSN8
6324 Morpho MT - 8 bit immediate relocation.
6327 BFD_RELOC_MSP430_10_PCREL
6329 BFD_RELOC_MSP430_16_PCREL
6333 BFD_RELOC_MSP430_16_PCREL_BYTE
6335 BFD_RELOC_MSP430_16_BYTE
6337 BFD_RELOC_MSP430_2X_PCREL
6339 BFD_RELOC_MSP430_RL_PCREL
6341 BFD_RELOC_MSP430_ABS8
6343 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6345 BFD_RELOC_MSP430X_PCR20_EXT_DST
6347 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6349 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6351 BFD_RELOC_MSP430X_ABS20_EXT_DST
6353 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6355 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6357 BFD_RELOC_MSP430X_ABS20_ADR_DST
6359 BFD_RELOC_MSP430X_PCR16
6361 BFD_RELOC_MSP430X_PCR20_CALL
6363 BFD_RELOC_MSP430X_ABS16
6365 BFD_RELOC_MSP430_ABS_HI16
6367 BFD_RELOC_MSP430_PREL31
6369 BFD_RELOC_MSP430_SYM_DIFF
6371 msp430 specific relocation codes
6378 BFD_RELOC_NIOS2_CALL26
6380 BFD_RELOC_NIOS2_IMM5
6382 BFD_RELOC_NIOS2_CACHE_OPX
6384 BFD_RELOC_NIOS2_IMM6
6386 BFD_RELOC_NIOS2_IMM8
6388 BFD_RELOC_NIOS2_HI16
6390 BFD_RELOC_NIOS2_LO16
6392 BFD_RELOC_NIOS2_HIADJ16
6394 BFD_RELOC_NIOS2_GPREL
6396 BFD_RELOC_NIOS2_UJMP
6398 BFD_RELOC_NIOS2_CJMP
6400 BFD_RELOC_NIOS2_CALLR
6402 BFD_RELOC_NIOS2_ALIGN
6404 BFD_RELOC_NIOS2_GOT16
6406 BFD_RELOC_NIOS2_CALL16
6408 BFD_RELOC_NIOS2_GOTOFF_LO
6410 BFD_RELOC_NIOS2_GOTOFF_HA
6412 BFD_RELOC_NIOS2_PCREL_LO
6414 BFD_RELOC_NIOS2_PCREL_HA
6416 BFD_RELOC_NIOS2_TLS_GD16
6418 BFD_RELOC_NIOS2_TLS_LDM16
6420 BFD_RELOC_NIOS2_TLS_LDO16
6422 BFD_RELOC_NIOS2_TLS_IE16
6424 BFD_RELOC_NIOS2_TLS_LE16
6426 BFD_RELOC_NIOS2_TLS_DTPMOD
6428 BFD_RELOC_NIOS2_TLS_DTPREL
6430 BFD_RELOC_NIOS2_TLS_TPREL
6432 BFD_RELOC_NIOS2_COPY
6434 BFD_RELOC_NIOS2_GLOB_DAT
6436 BFD_RELOC_NIOS2_JUMP_SLOT
6438 BFD_RELOC_NIOS2_RELATIVE
6440 BFD_RELOC_NIOS2_GOTOFF
6442 BFD_RELOC_NIOS2_CALL26_NOAT
6444 BFD_RELOC_NIOS2_GOT_LO
6446 BFD_RELOC_NIOS2_GOT_HA
6448 BFD_RELOC_NIOS2_CALL_LO
6450 BFD_RELOC_NIOS2_CALL_HA
6452 BFD_RELOC_NIOS2_R2_S12
6454 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6456 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6458 BFD_RELOC_NIOS2_R2_T1I7_2
6460 BFD_RELOC_NIOS2_R2_T2I4
6462 BFD_RELOC_NIOS2_R2_T2I4_1
6464 BFD_RELOC_NIOS2_R2_T2I4_2
6466 BFD_RELOC_NIOS2_R2_X1I7_2
6468 BFD_RELOC_NIOS2_R2_X2L5
6470 BFD_RELOC_NIOS2_R2_F1I5_2
6472 BFD_RELOC_NIOS2_R2_L5I4X1
6474 BFD_RELOC_NIOS2_R2_T1X1I6
6476 BFD_RELOC_NIOS2_R2_T1X1I6_2
6478 Relocations used by the Altera Nios II core.
6483 PRU LDI 16-bit unsigned data-memory relocation.
6485 BFD_RELOC_PRU_U16_PMEMIMM
6487 PRU LDI 16-bit unsigned instruction-memory relocation.
6491 PRU relocation for two consecutive LDI load instructions that load a
6492 32 bit value into a register. If the higher bits are all zero, then
6493 the second instruction may be relaxed.
6495 BFD_RELOC_PRU_S10_PCREL
6497 PRU QBBx 10-bit signed PC-relative relocation.
6499 BFD_RELOC_PRU_U8_PCREL
6501 PRU 8-bit unsigned relocation used for the LOOP instruction.
6503 BFD_RELOC_PRU_32_PMEM
6505 BFD_RELOC_PRU_16_PMEM
6507 PRU Program Memory relocations. Used to convert from byte addressing to
6508 32-bit word addressing.
6510 BFD_RELOC_PRU_GNU_DIFF8
6512 BFD_RELOC_PRU_GNU_DIFF16
6514 BFD_RELOC_PRU_GNU_DIFF32
6516 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6518 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6520 PRU relocations to mark the difference of two local symbols.
6521 These are only needed to support linker relaxation and can be ignored
6522 when not relaxing. The field is set to the value of the difference
6523 assuming no relaxation. The relocation encodes the position of the
6524 second symbol so the linker can determine whether to adjust the field
6525 value. The PMEM variants encode the word difference, instead of byte
6526 difference between symbols.
6529 BFD_RELOC_IQ2000_OFFSET_16
6531 BFD_RELOC_IQ2000_OFFSET_21
6533 BFD_RELOC_IQ2000_UHI16
6538 BFD_RELOC_XTENSA_RTLD
6540 Special Xtensa relocation used only by PLT entries in ELF shared
6541 objects to indicate that the runtime linker should set the value
6542 to one of its own internal functions or data structures.
6544 BFD_RELOC_XTENSA_GLOB_DAT
6546 BFD_RELOC_XTENSA_JMP_SLOT
6548 BFD_RELOC_XTENSA_RELATIVE
6550 Xtensa relocations for ELF shared objects.
6552 BFD_RELOC_XTENSA_PLT
6554 Xtensa relocation used in ELF object files for symbols that may require
6555 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6557 BFD_RELOC_XTENSA_DIFF8
6559 BFD_RELOC_XTENSA_DIFF16
6561 BFD_RELOC_XTENSA_DIFF32
6563 Xtensa relocations for backward compatibility. These have been replaced
6564 by BFD_RELOC_XTENSA_PDIFF and BFD_RELOC_XTENSA_NDIFF.
6565 Xtensa relocations to mark the difference of two local symbols.
6566 These are only needed to support linker relaxation and can be ignored
6567 when not relaxing. The field is set to the value of the difference
6568 assuming no relaxation. The relocation encodes the position of the
6569 first symbol so the linker can determine whether to adjust the field
6572 BFD_RELOC_XTENSA_SLOT0_OP
6574 BFD_RELOC_XTENSA_SLOT1_OP
6576 BFD_RELOC_XTENSA_SLOT2_OP
6578 BFD_RELOC_XTENSA_SLOT3_OP
6580 BFD_RELOC_XTENSA_SLOT4_OP
6582 BFD_RELOC_XTENSA_SLOT5_OP
6584 BFD_RELOC_XTENSA_SLOT6_OP
6586 BFD_RELOC_XTENSA_SLOT7_OP
6588 BFD_RELOC_XTENSA_SLOT8_OP
6590 BFD_RELOC_XTENSA_SLOT9_OP
6592 BFD_RELOC_XTENSA_SLOT10_OP
6594 BFD_RELOC_XTENSA_SLOT11_OP
6596 BFD_RELOC_XTENSA_SLOT12_OP
6598 BFD_RELOC_XTENSA_SLOT13_OP
6600 BFD_RELOC_XTENSA_SLOT14_OP
6602 Generic Xtensa relocations for instruction operands. Only the slot
6603 number is encoded in the relocation. The relocation applies to the
6604 last PC-relative immediate operand, or if there are no PC-relative
6605 immediates, to the last immediate operand.
6607 BFD_RELOC_XTENSA_SLOT0_ALT
6609 BFD_RELOC_XTENSA_SLOT1_ALT
6611 BFD_RELOC_XTENSA_SLOT2_ALT
6613 BFD_RELOC_XTENSA_SLOT3_ALT
6615 BFD_RELOC_XTENSA_SLOT4_ALT
6617 BFD_RELOC_XTENSA_SLOT5_ALT
6619 BFD_RELOC_XTENSA_SLOT6_ALT
6621 BFD_RELOC_XTENSA_SLOT7_ALT
6623 BFD_RELOC_XTENSA_SLOT8_ALT
6625 BFD_RELOC_XTENSA_SLOT9_ALT
6627 BFD_RELOC_XTENSA_SLOT10_ALT
6629 BFD_RELOC_XTENSA_SLOT11_ALT
6631 BFD_RELOC_XTENSA_SLOT12_ALT
6633 BFD_RELOC_XTENSA_SLOT13_ALT
6635 BFD_RELOC_XTENSA_SLOT14_ALT
6637 Alternate Xtensa relocations. Only the slot is encoded in the
6638 relocation. The meaning of these relocations is opcode-specific.
6640 BFD_RELOC_XTENSA_OP0
6642 BFD_RELOC_XTENSA_OP1
6644 BFD_RELOC_XTENSA_OP2
6646 Xtensa relocations for backward compatibility. These have all been
6647 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6649 BFD_RELOC_XTENSA_ASM_EXPAND
6651 Xtensa relocation to mark that the assembler expanded the
6652 instructions from an original target. The expansion size is
6653 encoded in the reloc size.
6655 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6657 Xtensa relocation to mark that the linker should simplify
6658 assembler-expanded instructions. This is commonly used
6659 internally by the linker after analysis of a
6660 BFD_RELOC_XTENSA_ASM_EXPAND.
6662 BFD_RELOC_XTENSA_TLSDESC_FN
6664 BFD_RELOC_XTENSA_TLSDESC_ARG
6666 BFD_RELOC_XTENSA_TLS_DTPOFF
6668 BFD_RELOC_XTENSA_TLS_TPOFF
6670 BFD_RELOC_XTENSA_TLS_FUNC
6672 BFD_RELOC_XTENSA_TLS_ARG
6674 BFD_RELOC_XTENSA_TLS_CALL
6676 Xtensa TLS relocations.
6678 BFD_RELOC_XTENSA_PDIFF8
6680 BFD_RELOC_XTENSA_PDIFF16
6682 BFD_RELOC_XTENSA_PDIFF32
6684 BFD_RELOC_XTENSA_NDIFF8
6686 BFD_RELOC_XTENSA_NDIFF16
6688 BFD_RELOC_XTENSA_NDIFF32
6690 Xtensa relocations to mark the difference of two local symbols.
6691 These are only needed to support linker relaxation and can be ignored
6692 when not relaxing. The field is set to the value of the difference
6693 assuming no relaxation. The relocation encodes the position of the
6694 subtracted symbol so the linker can determine whether to adjust the field
6695 value. PDIFF relocations are used for positive differences, NDIFF
6696 relocations are used for negative differences. The difference value
6697 is treated as unsigned with these relocation types, giving full
6703 8 bit signed offset in (ix+d) or (iy+d).
6707 First 8 bits of multibyte (32, 24 or 16 bit) value.
6711 Second 8 bits of multibyte (32, 24 or 16 bit) value.
6715 Third 8 bits of multibyte (32 or 24 bit) value.
6719 Fourth 8 bits of multibyte (32 bit) value.
6723 Lowest 16 bits of multibyte (32 or 24 bit) value.
6727 Highest 16 bits of multibyte (32 or 24 bit) value.
6731 Like BFD_RELOC_16 but big-endian.
6749 BFD_RELOC_LM32_BRANCH
6751 BFD_RELOC_LM32_16_GOT
6753 BFD_RELOC_LM32_GOTOFF_HI16
6755 BFD_RELOC_LM32_GOTOFF_LO16
6759 BFD_RELOC_LM32_GLOB_DAT
6761 BFD_RELOC_LM32_JMP_SLOT
6763 BFD_RELOC_LM32_RELATIVE
6765 Lattice Mico32 relocations.
6768 BFD_RELOC_MACH_O_SECTDIFF
6770 Difference between two section addreses. Must be followed by a
6771 BFD_RELOC_MACH_O_PAIR.
6773 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6775 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6777 BFD_RELOC_MACH_O_PAIR
6779 Pair of relocation. Contains the first symbol.
6781 BFD_RELOC_MACH_O_SUBTRACTOR32
6783 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6785 BFD_RELOC_MACH_O_SUBTRACTOR64
6787 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6790 BFD_RELOC_MACH_O_X86_64_BRANCH32
6792 BFD_RELOC_MACH_O_X86_64_BRANCH8
6794 PCREL relocations. They are marked as branch to create PLT entry if
6797 BFD_RELOC_MACH_O_X86_64_GOT
6799 Used when referencing a GOT entry.
6801 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6803 Used when loading a GOT entry with movq. It is specially marked so that
6804 the linker could optimize the movq to a leaq if possible.
6806 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6808 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6810 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6812 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6814 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6816 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6818 BFD_RELOC_MACH_O_X86_64_TLV
6820 Used when referencing a TLV entry.
6824 BFD_RELOC_MACH_O_ARM64_ADDEND
6826 Addend for PAGE or PAGEOFF.
6828 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6830 Relative offset to page of GOT slot.
6832 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6834 Relative offset within page of GOT slot.
6836 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6838 Address of a GOT entry.
6841 BFD_RELOC_MICROBLAZE_32_LO
6843 This is a 32 bit reloc for the microblaze that stores the
6844 low 16 bits of a value
6846 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6848 This is a 32 bit pc-relative reloc for the microblaze that
6849 stores the low 16 bits of a value
6851 BFD_RELOC_MICROBLAZE_32_ROSDA
6853 This is a 32 bit reloc for the microblaze that stores a
6854 value relative to the read-only small data area anchor
6856 BFD_RELOC_MICROBLAZE_32_RWSDA
6858 This is a 32 bit reloc for the microblaze that stores a
6859 value relative to the read-write small data area anchor
6861 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6863 This is a 32 bit reloc for the microblaze to handle
6864 expressions of the form "Symbol Op Symbol"
6866 BFD_RELOC_MICROBLAZE_64_NONE
6868 This is a 64 bit reloc that stores the 32 bit pc relative
6869 value in two words (with an imm instruction). No relocation is
6870 done here - only used for relaxing
6872 BFD_RELOC_MICROBLAZE_64_GOTPC
6874 This is a 64 bit reloc that stores the 32 bit pc relative
6875 value in two words (with an imm instruction). The relocation is
6876 PC-relative GOT offset
6878 BFD_RELOC_MICROBLAZE_64_GOT
6880 This is a 64 bit reloc that stores the 32 bit pc relative
6881 value in two words (with an imm instruction). The relocation is
6884 BFD_RELOC_MICROBLAZE_64_PLT
6886 This is a 64 bit reloc that stores the 32 bit pc relative
6887 value in two words (with an imm instruction). The relocation is
6888 PC-relative offset into PLT
6890 BFD_RELOC_MICROBLAZE_64_GOTOFF
6892 This is a 64 bit reloc that stores the 32 bit GOT relative
6893 value in two words (with an imm instruction). The relocation is
6894 relative offset from _GLOBAL_OFFSET_TABLE_
6896 BFD_RELOC_MICROBLAZE_32_GOTOFF
6898 This is a 32 bit reloc that stores the 32 bit GOT relative
6899 value in a word. The relocation is relative offset from
6900 _GLOBAL_OFFSET_TABLE_
6902 BFD_RELOC_MICROBLAZE_COPY
6904 This is used to tell the dynamic linker to copy the value out of
6905 the dynamic object into the runtime process image.
6907 BFD_RELOC_MICROBLAZE_64_TLS
6911 BFD_RELOC_MICROBLAZE_64_TLSGD
6913 This is a 64 bit reloc that stores the 32 bit GOT relative value
6914 of the GOT TLS GD info entry in two words (with an imm instruction). The
6915 relocation is GOT offset.
6917 BFD_RELOC_MICROBLAZE_64_TLSLD
6919 This is a 64 bit reloc that stores the 32 bit GOT relative value
6920 of the GOT TLS LD info entry in two words (with an imm instruction). The
6921 relocation is GOT offset.
6923 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6925 This is a 32 bit reloc that stores the Module ID to GOT(n).
6927 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6929 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6931 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6933 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6936 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6938 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6939 to two words (uses imm instruction).
6941 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6943 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6944 to two words (uses imm instruction).
6946 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6948 This is a 64 bit reloc that stores the 32 bit pc relative
6949 value in two words (with an imm instruction). The relocation is
6950 PC-relative offset from start of TEXT.
6952 BFD_RELOC_MICROBLAZE_64_TEXTREL
6954 This is a 64 bit reloc that stores the 32 bit offset
6955 value in two words (with an imm instruction). The relocation is
6956 relative offset from start of TEXT.
6959 BFD_RELOC_AARCH64_RELOC_START
6961 AArch64 pseudo relocation code to mark the start of the AArch64
6962 relocation enumerators. N.B. the order of the enumerators is
6963 important as several tables in the AArch64 bfd backend are indexed
6964 by these enumerators; make sure they are all synced.
6966 BFD_RELOC_AARCH64_NULL
6968 Deprecated AArch64 null relocation code.
6970 BFD_RELOC_AARCH64_NONE
6972 AArch64 null relocation code.
6974 BFD_RELOC_AARCH64_64
6976 BFD_RELOC_AARCH64_32
6978 BFD_RELOC_AARCH64_16
6980 Basic absolute relocations of N bits. These are equivalent to
6981 BFD_RELOC_N and they were added to assist the indexing of the howto
6984 BFD_RELOC_AARCH64_64_PCREL
6986 BFD_RELOC_AARCH64_32_PCREL
6988 BFD_RELOC_AARCH64_16_PCREL
6990 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6991 and they were added to assist the indexing of the howto table.
6993 BFD_RELOC_AARCH64_MOVW_G0
6995 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6996 of an unsigned address/value.
6998 BFD_RELOC_AARCH64_MOVW_G0_NC
7000 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
7001 an address/value. No overflow checking.
7003 BFD_RELOC_AARCH64_MOVW_G1
7005 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
7006 of an unsigned address/value.
7008 BFD_RELOC_AARCH64_MOVW_G1_NC
7010 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7011 of an address/value. No overflow checking.
7013 BFD_RELOC_AARCH64_MOVW_G2
7015 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7016 of an unsigned address/value.
7018 BFD_RELOC_AARCH64_MOVW_G2_NC
7020 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7021 of an address/value. No overflow checking.
7023 BFD_RELOC_AARCH64_MOVW_G3
7025 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7026 of a signed or unsigned address/value.
7028 BFD_RELOC_AARCH64_MOVW_G0_S
7030 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7031 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7034 BFD_RELOC_AARCH64_MOVW_G1_S
7036 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7037 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7040 BFD_RELOC_AARCH64_MOVW_G2_S
7042 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7043 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7046 BFD_RELOC_AARCH64_MOVW_PREL_G0
7048 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7049 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7052 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7054 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7055 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7058 BFD_RELOC_AARCH64_MOVW_PREL_G1
7060 AArch64 MOVK instruction with most significant bits 16 to 31
7063 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7065 AArch64 MOVK instruction with most significant bits 16 to 31
7068 BFD_RELOC_AARCH64_MOVW_PREL_G2
7070 AArch64 MOVK instruction with most significant bits 32 to 47
7073 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7075 AArch64 MOVK instruction with most significant bits 32 to 47
7078 BFD_RELOC_AARCH64_MOVW_PREL_G3
7080 AArch64 MOVK instruction with most significant bits 47 to 63
7083 BFD_RELOC_AARCH64_LD_LO19_PCREL
7085 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7086 offset. The lowest two bits must be zero and are not stored in the
7087 instruction, giving a 21 bit signed byte offset.
7089 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7091 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7093 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7095 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7096 offset, giving a 4KB aligned page base address.
7098 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7100 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7101 offset, giving a 4KB aligned page base address, but with no overflow
7104 BFD_RELOC_AARCH64_ADD_LO12
7106 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7107 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7109 BFD_RELOC_AARCH64_LDST8_LO12
7111 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7112 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7114 BFD_RELOC_AARCH64_TSTBR14
7116 AArch64 14 bit pc-relative test bit and branch.
7117 The lowest two bits must be zero and are not stored in the instruction,
7118 giving a 16 bit signed byte offset.
7120 BFD_RELOC_AARCH64_BRANCH19
7122 AArch64 19 bit pc-relative conditional branch and compare & branch.
7123 The lowest two bits must be zero and are not stored in the instruction,
7124 giving a 21 bit signed byte offset.
7126 BFD_RELOC_AARCH64_JUMP26
7128 AArch64 26 bit pc-relative unconditional branch.
7129 The lowest two bits must be zero and are not stored in the instruction,
7130 giving a 28 bit signed byte offset.
7132 BFD_RELOC_AARCH64_CALL26
7134 AArch64 26 bit pc-relative unconditional branch and link.
7135 The lowest two bits must be zero and are not stored in the instruction,
7136 giving a 28 bit signed byte offset.
7138 BFD_RELOC_AARCH64_LDST16_LO12
7140 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7141 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7143 BFD_RELOC_AARCH64_LDST32_LO12
7145 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7146 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7148 BFD_RELOC_AARCH64_LDST64_LO12
7150 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7151 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7153 BFD_RELOC_AARCH64_LDST128_LO12
7155 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7156 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7158 BFD_RELOC_AARCH64_GOT_LD_PREL19
7160 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7161 offset of the global offset table entry for a symbol. The lowest two
7162 bits must be zero and are not stored in the instruction, giving a 21
7163 bit signed byte offset. This relocation type requires signed overflow
7166 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7168 Get to the page base of the global offset table entry for a symbol as
7169 part of an ADRP instruction using a 21 bit PC relative value.Used in
7170 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7172 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7174 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7175 the GOT entry for this symbol. Used in conjunction with
7176 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7178 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7180 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7181 the GOT entry for this symbol. Used in conjunction with
7182 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7184 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7186 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7187 for this symbol. Valid in LP64 ABI only.
7189 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7191 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7192 for this symbol. Valid in LP64 ABI only.
7194 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7196 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7197 the GOT entry for this symbol. Valid in LP64 ABI only.
7199 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7201 Scaled 14 bit byte offset to the page base of the global offset table.
7203 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7205 Scaled 15 bit byte offset to the page base of the global offset table.
7207 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7209 Get to the page base of the global offset table entry for a symbols
7210 tls_index structure as part of an adrp instruction using a 21 bit PC
7211 relative value. Used in conjunction with
7212 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7214 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7216 AArch64 TLS General Dynamic
7218 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7220 Unsigned 12 bit byte offset to global offset table entry for a symbols
7221 tls_index structure. Used in conjunction with
7222 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7224 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7226 AArch64 TLS General Dynamic relocation.
7228 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7230 AArch64 TLS General Dynamic relocation.
7232 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7234 AArch64 TLS INITIAL EXEC relocation.
7236 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7238 AArch64 TLS INITIAL EXEC relocation.
7240 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7242 AArch64 TLS INITIAL EXEC relocation.
7244 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7246 AArch64 TLS INITIAL EXEC relocation.
7248 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7250 AArch64 TLS INITIAL EXEC relocation.
7252 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7254 AArch64 TLS INITIAL EXEC relocation.
7256 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7258 bit[23:12] of byte offset to module TLS base address.
7260 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7262 Unsigned 12 bit byte offset to module TLS base address.
7264 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7266 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7268 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7270 Unsigned 12 bit byte offset to global offset table entry for a symbols
7271 tls_index structure. Used in conjunction with
7272 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7274 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7276 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7279 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7281 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7283 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7285 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7288 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7290 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7292 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7294 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7297 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7299 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7301 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7303 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7306 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7308 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7310 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7312 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7315 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7317 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7319 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7321 bit[15:0] of byte offset to module TLS base address.
7323 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7325 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7327 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7329 bit[31:16] of byte offset to module TLS base address.
7331 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7333 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7335 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7337 bit[47:32] of byte offset to module TLS base address.
7339 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7341 AArch64 TLS LOCAL EXEC relocation.
7343 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7345 AArch64 TLS LOCAL EXEC relocation.
7347 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7349 AArch64 TLS LOCAL EXEC relocation.
7351 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7353 AArch64 TLS LOCAL EXEC relocation.
7355 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7357 AArch64 TLS LOCAL EXEC relocation.
7359 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7361 AArch64 TLS LOCAL EXEC relocation.
7363 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7365 AArch64 TLS LOCAL EXEC relocation.
7367 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7369 AArch64 TLS LOCAL EXEC relocation.
7371 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7373 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7376 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7378 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7380 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7382 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7385 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7387 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7389 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7391 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7394 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7396 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7398 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7400 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7403 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7405 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7407 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7409 AArch64 TLS DESC relocation.
7411 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7413 AArch64 TLS DESC relocation.
7415 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7417 AArch64 TLS DESC relocation.
7419 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7421 AArch64 TLS DESC relocation.
7423 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7425 AArch64 TLS DESC relocation.
7427 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7429 AArch64 TLS DESC relocation.
7431 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7433 AArch64 TLS DESC relocation.
7435 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7437 AArch64 TLS DESC relocation.
7439 BFD_RELOC_AARCH64_TLSDESC_LDR
7441 AArch64 TLS DESC relocation.
7443 BFD_RELOC_AARCH64_TLSDESC_ADD
7445 AArch64 TLS DESC relocation.
7447 BFD_RELOC_AARCH64_TLSDESC_CALL
7449 AArch64 TLS DESC relocation.
7451 BFD_RELOC_AARCH64_COPY
7453 AArch64 TLS relocation.
7455 BFD_RELOC_AARCH64_GLOB_DAT
7457 AArch64 TLS relocation.
7459 BFD_RELOC_AARCH64_JUMP_SLOT
7461 AArch64 TLS relocation.
7463 BFD_RELOC_AARCH64_RELATIVE
7465 AArch64 TLS relocation.
7467 BFD_RELOC_AARCH64_TLS_DTPMOD
7469 AArch64 TLS relocation.
7471 BFD_RELOC_AARCH64_TLS_DTPREL
7473 AArch64 TLS relocation.
7475 BFD_RELOC_AARCH64_TLS_TPREL
7477 AArch64 TLS relocation.
7479 BFD_RELOC_AARCH64_TLSDESC
7481 AArch64 TLS relocation.
7483 BFD_RELOC_AARCH64_IRELATIVE
7485 AArch64 support for STT_GNU_IFUNC.
7487 BFD_RELOC_AARCH64_RELOC_END
7489 AArch64 pseudo relocation code to mark the end of the AArch64
7490 relocation enumerators that have direct mapping to ELF reloc codes.
7491 There are a few more enumerators after this one; those are mainly
7492 used by the AArch64 assembler for the internal fixup or to select
7493 one of the above enumerators.
7495 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7497 AArch64 pseudo relocation code to be used internally by the AArch64
7498 assembler and not (currently) written to any object files.
7500 BFD_RELOC_AARCH64_LDST_LO12
7502 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7503 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7505 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7507 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7508 used internally by the AArch64 assembler and not (currently) written to
7511 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7513 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7515 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7517 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7518 used internally by the AArch64 assembler and not (currently) written to
7521 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7523 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7525 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7527 AArch64 pseudo relocation code to be used internally by the AArch64
7528 assembler and not (currently) written to any object files.
7530 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7532 AArch64 pseudo relocation code to be used internally by the AArch64
7533 assembler and not (currently) written to any object files.
7535 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7537 AArch64 pseudo relocation code to be used internally by the AArch64
7538 assembler and not (currently) written to any object files.
7540 BFD_RELOC_TILEPRO_COPY
7542 BFD_RELOC_TILEPRO_GLOB_DAT
7544 BFD_RELOC_TILEPRO_JMP_SLOT
7546 BFD_RELOC_TILEPRO_RELATIVE
7548 BFD_RELOC_TILEPRO_BROFF_X1
7550 BFD_RELOC_TILEPRO_JOFFLONG_X1
7552 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7554 BFD_RELOC_TILEPRO_IMM8_X0
7556 BFD_RELOC_TILEPRO_IMM8_Y0
7558 BFD_RELOC_TILEPRO_IMM8_X1
7560 BFD_RELOC_TILEPRO_IMM8_Y1
7562 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7564 BFD_RELOC_TILEPRO_MT_IMM15_X1
7566 BFD_RELOC_TILEPRO_MF_IMM15_X1
7568 BFD_RELOC_TILEPRO_IMM16_X0
7570 BFD_RELOC_TILEPRO_IMM16_X1
7572 BFD_RELOC_TILEPRO_IMM16_X0_LO
7574 BFD_RELOC_TILEPRO_IMM16_X1_LO
7576 BFD_RELOC_TILEPRO_IMM16_X0_HI
7578 BFD_RELOC_TILEPRO_IMM16_X1_HI
7580 BFD_RELOC_TILEPRO_IMM16_X0_HA
7582 BFD_RELOC_TILEPRO_IMM16_X1_HA
7584 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7586 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7588 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7590 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7592 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7594 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7596 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7598 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7600 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7602 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7604 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7606 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7608 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7610 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7612 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7614 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7616 BFD_RELOC_TILEPRO_MMSTART_X0
7618 BFD_RELOC_TILEPRO_MMEND_X0
7620 BFD_RELOC_TILEPRO_MMSTART_X1
7622 BFD_RELOC_TILEPRO_MMEND_X1
7624 BFD_RELOC_TILEPRO_SHAMT_X0
7626 BFD_RELOC_TILEPRO_SHAMT_X1
7628 BFD_RELOC_TILEPRO_SHAMT_Y0
7630 BFD_RELOC_TILEPRO_SHAMT_Y1
7632 BFD_RELOC_TILEPRO_TLS_GD_CALL
7634 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7636 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7638 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7640 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7642 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7644 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7646 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7648 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7650 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7652 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7654 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7656 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7658 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7660 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7662 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7664 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7666 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7668 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7670 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7672 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7674 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7676 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7678 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7680 BFD_RELOC_TILEPRO_TLS_TPOFF32
7682 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7684 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7686 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7688 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7690 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7692 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7694 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7696 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7698 Tilera TILEPro Relocations.
7700 BFD_RELOC_TILEGX_HW0
7702 BFD_RELOC_TILEGX_HW1
7704 BFD_RELOC_TILEGX_HW2
7706 BFD_RELOC_TILEGX_HW3
7708 BFD_RELOC_TILEGX_HW0_LAST
7710 BFD_RELOC_TILEGX_HW1_LAST
7712 BFD_RELOC_TILEGX_HW2_LAST
7714 BFD_RELOC_TILEGX_COPY
7716 BFD_RELOC_TILEGX_GLOB_DAT
7718 BFD_RELOC_TILEGX_JMP_SLOT
7720 BFD_RELOC_TILEGX_RELATIVE
7722 BFD_RELOC_TILEGX_BROFF_X1
7724 BFD_RELOC_TILEGX_JUMPOFF_X1
7726 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7728 BFD_RELOC_TILEGX_IMM8_X0
7730 BFD_RELOC_TILEGX_IMM8_Y0
7732 BFD_RELOC_TILEGX_IMM8_X1
7734 BFD_RELOC_TILEGX_IMM8_Y1
7736 BFD_RELOC_TILEGX_DEST_IMM8_X1
7738 BFD_RELOC_TILEGX_MT_IMM14_X1
7740 BFD_RELOC_TILEGX_MF_IMM14_X1
7742 BFD_RELOC_TILEGX_MMSTART_X0
7744 BFD_RELOC_TILEGX_MMEND_X0
7746 BFD_RELOC_TILEGX_SHAMT_X0
7748 BFD_RELOC_TILEGX_SHAMT_X1
7750 BFD_RELOC_TILEGX_SHAMT_Y0
7752 BFD_RELOC_TILEGX_SHAMT_Y1
7754 BFD_RELOC_TILEGX_IMM16_X0_HW0
7756 BFD_RELOC_TILEGX_IMM16_X1_HW0
7758 BFD_RELOC_TILEGX_IMM16_X0_HW1
7760 BFD_RELOC_TILEGX_IMM16_X1_HW1
7762 BFD_RELOC_TILEGX_IMM16_X0_HW2
7764 BFD_RELOC_TILEGX_IMM16_X1_HW2
7766 BFD_RELOC_TILEGX_IMM16_X0_HW3
7768 BFD_RELOC_TILEGX_IMM16_X1_HW3
7770 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7772 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7774 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7776 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7778 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7780 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7782 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7784 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7786 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7788 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7790 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7792 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7794 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7796 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7798 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7800 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7802 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7804 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7806 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7808 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7810 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7812 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7814 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7816 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7818 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7820 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7822 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7824 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7826 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7828 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7830 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7832 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7834 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7836 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7838 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7840 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7842 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7844 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7846 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7848 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7850 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7852 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7854 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7856 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7858 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7860 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7862 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7864 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7866 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7868 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7870 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7872 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7874 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7876 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7878 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7880 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7882 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7884 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7886 BFD_RELOC_TILEGX_TLS_DTPMOD64
7888 BFD_RELOC_TILEGX_TLS_DTPOFF64
7890 BFD_RELOC_TILEGX_TLS_TPOFF64
7892 BFD_RELOC_TILEGX_TLS_DTPMOD32
7894 BFD_RELOC_TILEGX_TLS_DTPOFF32
7896 BFD_RELOC_TILEGX_TLS_TPOFF32
7898 BFD_RELOC_TILEGX_TLS_GD_CALL
7900 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7902 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7904 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7906 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7908 BFD_RELOC_TILEGX_TLS_IE_LOAD
7910 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7912 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7914 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7916 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7918 Tilera TILE-Gx Relocations.
7927 BFD_RELOC_BPF_DISP16
7929 BFD_RELOC_BPF_DISP32
7931 Linux eBPF relocations.
7934 BFD_RELOC_EPIPHANY_SIMM8
7936 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7938 BFD_RELOC_EPIPHANY_SIMM24
7940 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7942 BFD_RELOC_EPIPHANY_HIGH
7944 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7946 BFD_RELOC_EPIPHANY_LOW
7948 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7950 BFD_RELOC_EPIPHANY_SIMM11
7952 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7954 BFD_RELOC_EPIPHANY_IMM11
7956 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7958 BFD_RELOC_EPIPHANY_IMM8
7960 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7963 BFD_RELOC_VISIUM_HI16
7965 BFD_RELOC_VISIUM_LO16
7967 BFD_RELOC_VISIUM_IM16
7969 BFD_RELOC_VISIUM_REL16
7971 BFD_RELOC_VISIUM_HI16_PCREL
7973 BFD_RELOC_VISIUM_LO16_PCREL
7975 BFD_RELOC_VISIUM_IM16_PCREL
7980 BFD_RELOC_WASM32_LEB128
7982 BFD_RELOC_WASM32_LEB128_GOT
7984 BFD_RELOC_WASM32_LEB128_GOT_CODE
7986 BFD_RELOC_WASM32_LEB128_PLT
7988 BFD_RELOC_WASM32_PLT_INDEX
7990 BFD_RELOC_WASM32_ABS32_CODE
7992 BFD_RELOC_WASM32_COPY
7994 BFD_RELOC_WASM32_CODE_POINTER
7996 BFD_RELOC_WASM32_INDEX
7998 BFD_RELOC_WASM32_PLT_SIG
8000 WebAssembly relocations.
8003 BFD_RELOC_CKCORE_NONE
8005 BFD_RELOC_CKCORE_ADDR32
8007 BFD_RELOC_CKCORE_PCREL_IMM8BY4
8009 BFD_RELOC_CKCORE_PCREL_IMM11BY2
8011 BFD_RELOC_CKCORE_PCREL_IMM4BY2
8013 BFD_RELOC_CKCORE_PCREL32
8015 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
8017 BFD_RELOC_CKCORE_GNU_VTINHERIT
8019 BFD_RELOC_CKCORE_GNU_VTENTRY
8021 BFD_RELOC_CKCORE_RELATIVE
8023 BFD_RELOC_CKCORE_COPY
8025 BFD_RELOC_CKCORE_GLOB_DAT
8027 BFD_RELOC_CKCORE_JUMP_SLOT
8029 BFD_RELOC_CKCORE_GOTOFF
8031 BFD_RELOC_CKCORE_GOTPC
8033 BFD_RELOC_CKCORE_GOT32
8035 BFD_RELOC_CKCORE_PLT32
8037 BFD_RELOC_CKCORE_ADDRGOT
8039 BFD_RELOC_CKCORE_ADDRPLT
8041 BFD_RELOC_CKCORE_PCREL_IMM26BY2
8043 BFD_RELOC_CKCORE_PCREL_IMM16BY2
8045 BFD_RELOC_CKCORE_PCREL_IMM16BY4
8047 BFD_RELOC_CKCORE_PCREL_IMM10BY2
8049 BFD_RELOC_CKCORE_PCREL_IMM10BY4
8051 BFD_RELOC_CKCORE_ADDR_HI16
8053 BFD_RELOC_CKCORE_ADDR_LO16
8055 BFD_RELOC_CKCORE_GOTPC_HI16
8057 BFD_RELOC_CKCORE_GOTPC_LO16
8059 BFD_RELOC_CKCORE_GOTOFF_HI16
8061 BFD_RELOC_CKCORE_GOTOFF_LO16
8063 BFD_RELOC_CKCORE_GOT12
8065 BFD_RELOC_CKCORE_GOT_HI16
8067 BFD_RELOC_CKCORE_GOT_LO16
8069 BFD_RELOC_CKCORE_PLT12
8071 BFD_RELOC_CKCORE_PLT_HI16
8073 BFD_RELOC_CKCORE_PLT_LO16
8075 BFD_RELOC_CKCORE_ADDRGOT_HI16
8077 BFD_RELOC_CKCORE_ADDRGOT_LO16
8079 BFD_RELOC_CKCORE_ADDRPLT_HI16
8081 BFD_RELOC_CKCORE_ADDRPLT_LO16
8083 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
8085 BFD_RELOC_CKCORE_TOFFSET_LO16
8087 BFD_RELOC_CKCORE_DOFFSET_LO16
8089 BFD_RELOC_CKCORE_PCREL_IMM18BY2
8091 BFD_RELOC_CKCORE_DOFFSET_IMM18
8093 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
8095 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
8097 BFD_RELOC_CKCORE_GOTOFF_IMM18
8099 BFD_RELOC_CKCORE_GOT_IMM18BY4
8101 BFD_RELOC_CKCORE_PLT_IMM18BY4
8103 BFD_RELOC_CKCORE_PCREL_IMM7BY4
8105 BFD_RELOC_CKCORE_TLS_LE32
8107 BFD_RELOC_CKCORE_TLS_IE32
8109 BFD_RELOC_CKCORE_TLS_GD32
8111 BFD_RELOC_CKCORE_TLS_LDM32
8113 BFD_RELOC_CKCORE_TLS_LDO32
8115 BFD_RELOC_CKCORE_TLS_DTPMOD32
8117 BFD_RELOC_CKCORE_TLS_DTPOFF32
8119 BFD_RELOC_CKCORE_TLS_TPOFF32
8121 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
8123 BFD_RELOC_CKCORE_NOJSRI
8125 BFD_RELOC_CKCORE_CALLGRAPH
8127 BFD_RELOC_CKCORE_IRELATIVE
8129 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8131 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8144 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8149 bfd_reloc_type_lookup
8150 bfd_reloc_name_lookup
8153 reloc_howto_type *bfd_reloc_type_lookup
8154 (bfd *abfd, bfd_reloc_code_real_type code);
8155 reloc_howto_type *bfd_reloc_name_lookup
8156 (bfd *abfd, const char *reloc_name);
8159 Return a pointer to a howto structure which, when
8160 invoked, will perform the relocation @var{code} on data from the
8166 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8168 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
8172 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
8174 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
8177 static reloc_howto_type bfd_howto_32
=
8178 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
8182 bfd_default_reloc_type_lookup
8185 reloc_howto_type *bfd_default_reloc_type_lookup
8186 (bfd *abfd, bfd_reloc_code_real_type code);
8189 Provides a default relocation lookup routine for any architecture.
8194 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8196 /* Very limited support is provided for relocs in generic targets
8197 such as elf32-little. FIXME: Should we always return NULL? */
8198 if (code
== BFD_RELOC_CTOR
8199 && bfd_arch_bits_per_address (abfd
) == 32)
8200 return &bfd_howto_32
;
8206 bfd_get_reloc_code_name
8209 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8212 Provides a printable name for the supplied relocation code.
8213 Useful mainly for printing error messages.
8217 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
8219 if (code
> BFD_RELOC_UNUSED
)
8221 return bfd_reloc_code_real_names
[code
];
8226 bfd_generic_relax_section
8229 bfd_boolean bfd_generic_relax_section
8232 struct bfd_link_info *,
8236 Provides default handling for relaxing for back ends which
8241 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8242 asection
*section ATTRIBUTE_UNUSED
,
8243 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8246 if (bfd_link_relocatable (link_info
))
8247 (*link_info
->callbacks
->einfo
)
8248 (_("%P%F: --relax and -r may not be used together\n"));
8256 bfd_generic_gc_sections
8259 bfd_boolean bfd_generic_gc_sections
8260 (bfd *, struct bfd_link_info *);
8263 Provides default handling for relaxing for back ends which
8264 don't do section gc -- i.e., does nothing.
8268 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8269 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8276 bfd_generic_lookup_section_flags
8279 bfd_boolean bfd_generic_lookup_section_flags
8280 (struct bfd_link_info *, struct flag_info *, asection *);
8283 Provides default handling for section flags lookup
8284 -- i.e., does nothing.
8285 Returns FALSE if the section should be omitted, otherwise TRUE.
8289 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8290 struct flag_info
*flaginfo
,
8291 asection
*section ATTRIBUTE_UNUSED
)
8293 if (flaginfo
!= NULL
)
8295 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8303 bfd_generic_merge_sections
8306 bfd_boolean bfd_generic_merge_sections
8307 (bfd *, struct bfd_link_info *);
8310 Provides default handling for SEC_MERGE section merging for back ends
8311 which don't have SEC_MERGE support -- i.e., does nothing.
8315 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8316 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8323 bfd_generic_get_relocated_section_contents
8326 bfd_byte *bfd_generic_get_relocated_section_contents
8328 struct bfd_link_info *link_info,
8329 struct bfd_link_order *link_order,
8331 bfd_boolean relocatable,
8335 Provides default handling of relocation effort for back ends
8336 which can't be bothered to do it efficiently.
8341 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8342 struct bfd_link_info
*link_info
,
8343 struct bfd_link_order
*link_order
,
8345 bfd_boolean relocatable
,
8348 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8349 asection
*input_section
= link_order
->u
.indirect
.section
;
8351 arelent
**reloc_vector
;
8354 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8358 /* Read in the section. */
8359 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8365 if (reloc_size
== 0)
8368 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8369 if (reloc_vector
== NULL
)
8372 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8376 if (reloc_count
< 0)
8379 if (reloc_count
> 0)
8383 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8385 char *error_message
= NULL
;
8387 bfd_reloc_status_type r
;
8389 symbol
= *(*parent
)->sym_ptr_ptr
;
8390 /* PR ld/19628: A specially crafted input file
8391 can result in a NULL symbol pointer here. */
8394 link_info
->callbacks
->einfo
8395 /* xgettext:c-format */
8396 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8397 abfd
, input_section
, (* parent
)->address
);
8401 /* Zap reloc field when the symbol is from a discarded
8402 section, ignoring any addend. Do the same when called
8403 from bfd_simple_get_relocated_section_contents for
8404 undefined symbols in debug sections. This is to keep
8405 debug info reasonably sane, in particular so that
8406 DW_FORM_ref_addr to another file's .debug_info isn't
8407 confused with an offset into the current file's
8409 if ((symbol
->section
!= NULL
&& discarded_section (symbol
->section
))
8410 || (symbol
->section
== bfd_und_section_ptr
8411 && (input_section
->flags
& SEC_DEBUGGING
) != 0
8412 && link_info
->input_bfds
== link_info
->output_bfd
))
8415 static reloc_howto_type none_howto
8416 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
8417 "unused", FALSE
, 0, 0, FALSE
);
8419 off
= ((*parent
)->address
8420 * bfd_octets_per_byte (input_bfd
, input_section
));
8421 _bfd_clear_contents ((*parent
)->howto
, input_bfd
,
8422 input_section
, data
, off
);
8423 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8424 (*parent
)->addend
= 0;
8425 (*parent
)->howto
= &none_howto
;
8429 r
= bfd_perform_relocation (input_bfd
,
8433 relocatable
? abfd
: NULL
,
8438 asection
*os
= input_section
->output_section
;
8440 /* A partial link, so keep the relocs. */
8441 os
->orelocation
[os
->reloc_count
] = *parent
;
8445 if (r
!= bfd_reloc_ok
)
8449 case bfd_reloc_undefined
:
8450 (*link_info
->callbacks
->undefined_symbol
)
8451 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8452 input_bfd
, input_section
, (*parent
)->address
, TRUE
);
8454 case bfd_reloc_dangerous
:
8455 BFD_ASSERT (error_message
!= NULL
);
8456 (*link_info
->callbacks
->reloc_dangerous
)
8457 (link_info
, error_message
,
8458 input_bfd
, input_section
, (*parent
)->address
);
8460 case bfd_reloc_overflow
:
8461 (*link_info
->callbacks
->reloc_overflow
)
8463 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8464 (*parent
)->howto
->name
, (*parent
)->addend
,
8465 input_bfd
, input_section
, (*parent
)->address
);
8467 case bfd_reloc_outofrange
:
8469 This error can result when processing some partially
8470 complete binaries. Do not abort, but issue an error
8472 link_info
->callbacks
->einfo
8473 /* xgettext:c-format */
8474 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8475 abfd
, input_section
, * parent
);
8478 case bfd_reloc_notsupported
:
8480 This error can result when processing a corrupt binary.
8481 Do not abort. Issue an error message instead. */
8482 link_info
->callbacks
->einfo
8483 /* xgettext:c-format */
8484 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8485 abfd
, input_section
, * parent
);
8489 /* PR 17512; file: 90c2a92e.
8490 Report unexpected results, without aborting. */
8491 link_info
->callbacks
->einfo
8492 /* xgettext:c-format */
8493 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8494 abfd
, input_section
, * parent
, r
);
8502 free (reloc_vector
);
8506 free (reloc_vector
);
8512 _bfd_generic_set_reloc
8515 void _bfd_generic_set_reloc
8519 unsigned int count);
8522 Installs a new set of internal relocations in SECTION.
8526 _bfd_generic_set_reloc (bfd
*abfd ATTRIBUTE_UNUSED
,
8531 section
->orelocation
= relptr
;
8532 section
->reloc_count
= count
;
8537 _bfd_unrecognized_reloc
8540 bfd_boolean _bfd_unrecognized_reloc
8543 unsigned int r_type);
8546 Reports an unrecognized reloc.
8547 Written as a function in order to reduce code duplication.
8548 Returns FALSE so that it can be called from a return statement.
8552 _bfd_unrecognized_reloc (bfd
* abfd
, sec_ptr section
, unsigned int r_type
)
8554 /* xgettext:c-format */
8555 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8556 abfd
, r_type
, section
);
8558 /* PR 21803: Suggest the most likely cause of this error. */
8559 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8560 BFD_VERSION_STRING
);
8562 bfd_set_error (bfd_error_bad_value
);
8567 _bfd_norelocs_bfd_reloc_type_lookup
8569 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED
)
8571 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8575 _bfd_norelocs_bfd_reloc_name_lookup (bfd
*abfd
,
8576 const char *reloc_name ATTRIBUTE_UNUSED
)
8578 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8582 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd
*abfd
,
8583 arelent
**relp ATTRIBUTE_UNUSED
,
8584 asymbol
**symp ATTRIBUTE_UNUSED
)
8586 return _bfd_long_bfd_n1_error (abfd
);