binutils/patches/binutils-2.23.51.0.3-arm-ldralt.patch

   1 diff -rcp ../binutils-2.23.51.0.3.orig/gas/ChangeLog ./gas/ChangeLog
   2 *** ../binutils-2.23.51.0.3.orig/gas/ChangeLog  2012-10-23 10:15:13.038870720 +0100
   3 --- ./gas/ChangeLog     2012-10-23 10:17:56.688907041 +0100
   4 ***************
   5 *** 1,3 ****
   6 --- 1,8 ----
   7 + 2012-09-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
   8 +
   9 +       * config/tc-arm.c: Changed ldra and strl-form mnemonics
  10 +       to lda and stl-form for armv8.
  11 +
  12   2012-09-17  Yufeng Zhang  <yufeng.zhang@arm.com>
  13
  14         * config/tc-aarch64.c (aarch64_archs): Rename 'armv8' to 'armv8-a'.
  15 diff -rcp ../binutils-2.23.51.0.3.orig/gas/config/tc-arm.c ./gas/config/tc-arm.c
  16 *** ../binutils-2.23.51.0.3.orig/gas/config/tc-arm.c    2012-10-23 10:15:13.379871049 +0100
  17 --- ./gas/config/tc-arm.c       2012-10-23 10:16:50.892897421 +0100
  18 *************** do_strexd (void)
  19 *** 8738,8744 ****
  20
  21   /* ARM V8 STRL.  */
  22   static void
  23 ! do_strlex (void)
  24   {
  25     constraint (inst.operands[0].reg == inst.operands[1].reg
  26               || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
  27 --- 8738,8744 ----
  28
  29   /* ARM V8 STRL.  */
  30   static void
  31 ! do_stlex (void)
  32   {
  33     constraint (inst.operands[0].reg == inst.operands[1].reg
  34               || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
  35 *************** do_strlex (void)
  36 *** 8747,8753 ****
  37   }
  38
  39   static void
  40 ! do_t_strlex (void)
  41   {
  42     constraint (inst.operands[0].reg == inst.operands[1].reg
  43               || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
  44 --- 8747,8753 ----
  45   }
  46
  47   static void
  48 ! do_t_stlex (void)
  49   {
  50     constraint (inst.operands[0].reg == inst.operands[1].reg
  51               || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
  52 *************** static const struct asm_opcode insns[] =
  53 *** 18476,18500 ****
  54
  55    tCE("sevl",  320f005, _sevl,    0, (),               noargs, t_hint),
  56    TUE("hlt",   1000070, ba80,     1, (oIffffb),        bkpt,   t_hlt),
  57 !  TCE("ldraex",        1900e9f, e8d00fef, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
  58 !  TCE("ldraexd",       1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
  59                                                         ldrexd, t_ldrexd),
  60 !  TCE("ldraexb",       1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb),   rd_rn,  rd_rn),
  61 !  TCE("ldraexh",       1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
  62 !  TCE("strlex",        1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
  63 !                                                       strlex,  t_strlex),
  64 !  TCE("strlexd",       1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
  65                                                         strexd, t_strexd),
  66 !  TCE("strlexb",       1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
  67 !                                                       strlex, t_strlex),
  68 !  TCE("strlexh",       1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
  69 !                                                       strlex, t_strlex),
  70 !  TCE("ldra",  1900c9f, e8d00faf, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
  71 !  TCE("ldrab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
  72 !  TCE("ldrah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
  73 !  TCE("strl",  180fc90, e8c00faf, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
  74 !  TCE("strlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
  75 !  TCE("strlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
  76
  77    /* ARMv8 T32 only.  */
  78   #undef ARM_VARIANT
  79 --- 18476,18500 ----
  80
  81    tCE("sevl",  320f005, _sevl,    0, (),               noargs, t_hint),
  82    TUE("hlt",   1000070, ba80,     1, (oIffffb),        bkpt,   t_hlt),
  83 !  TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
  84 !  TCE("ldaexd",        1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
  85                                                         ldrexd, t_ldrexd),
  86 !  TCE("ldaexb",        1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb),   rd_rn,  rd_rn),
  87 !  TCE("ldaexh",        1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
  88 !  TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
  89 !                                                       stlex,  t_stlex),
  90 !  TCE("stlexd",        1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
  91                                                         strexd, t_strexd),
  92 !  TCE("stlexb",        1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
  93 !                                                       stlex, t_stlex),
  94 !  TCE("stlexh",        1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
  95 !                                                       stlex, t_stlex),
  96 !  TCE("lda",   1900c9f, e8d00faf, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
  97 !  TCE("ldab",  1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
  98 !  TCE("ldah",  1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
  99 !  TCE("stl",   180fc90, e8c00faf, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
 100 !  TCE("stlb",  1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
 101 !  TCE("stlh",  1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
 102
 103    /* ARMv8 T32 only.  */
 104   #undef ARM_VARIANT
 105 diff -rcp ../binutils-2.23.51.0.3.orig/opcodes/arm-dis.c ./opcodes/arm-dis.c
 106 *** ../binutils-2.23.51.0.3.orig/opcodes/arm-dis.c      2012-10-23 10:15:16.976873621 +0100
 107 --- ./opcodes/arm-dis.c 2012-10-23 10:16:34.204894516 +0100
 108 *************** static const struct opcode32 arm_opcodes
 109 *** 889,908 ****
 110     /* V8 instructions.  */
 111     {ARM_EXT_V8,   0x0320f005, 0x0fffffff, "sevl"},
 112     {ARM_EXT_V8,   0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
 113 !   {ARM_EXT_V8,         0x01800e90, 0x0ff00ff0, "strlex%c\t%12-15r, %0-3r, [%16-19R]"},
 114 !   {ARM_EXT_V8,         0x01900e9f, 0x0ff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
 115 !   {ARM_EXT_V8,         0x01a00e90, 0x0ff00ff0, "strlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
 116 !   {ARM_EXT_V8,         0x01b00e9f, 0x0ff00fff, "ldraexd%c\t%12-15r, %12-15T, [%16-19R]"},
 117 !   {ARM_EXT_V8,         0x01c00e90, 0x0ff00ff0, "strlexb%c\t%12-15r, %0-3r, [%16-19R]"},
 118 !   {ARM_EXT_V8,         0x01d00e9f, 0x0ff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
 119 !   {ARM_EXT_V8,         0x01e00e90, 0x0ff00ff0, "strlexh%c\t%12-15r, %0-3r, [%16-19R]"},
 120 !   {ARM_EXT_V8,         0x01f00e9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
 121 !   {ARM_EXT_V8,         0x0180fc90, 0x0ff0fff0, "strl%c\t%0-3r, [%16-19R]"},
 122 !   {ARM_EXT_V8,         0x01900c9f, 0x0ff00fff, "ldra%c\t%12-15r, [%16-19R]"},
 123 !   {ARM_EXT_V8,         0x01c0fc90, 0x0ff0fff0, "strlb%c\t%0-3r, [%16-19R]"},
 124 !   {ARM_EXT_V8,         0x01d00c9f, 0x0ff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
 125 !   {ARM_EXT_V8,         0x01e0fc90, 0x0ff0fff0, "strlh%c\t%0-3r, [%16-19R]"},
 126 !   {ARM_EXT_V8,         0x01f00c9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
 127
 128     /* Virtualization Extension instructions.  */
 129     {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
 130 --- 889,908 ----
 131     /* V8 instructions.  */
 132     {ARM_EXT_V8,   0x0320f005, 0x0fffffff, "sevl"},
 133     {ARM_EXT_V8,   0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
 134 !   {ARM_EXT_V8,         0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
 135 !   {ARM_EXT_V8,         0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
 136 !   {ARM_EXT_V8,         0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
 137 !   {ARM_EXT_V8,         0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
 138 !   {ARM_EXT_V8,         0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
 139 !   {ARM_EXT_V8,         0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
 140 !   {ARM_EXT_V8,         0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
 141 !   {ARM_EXT_V8,         0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
 142 !   {ARM_EXT_V8,         0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
 143 !   {ARM_EXT_V8,         0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
 144 !   {ARM_EXT_V8,         0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
 145 !   {ARM_EXT_V8,         0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
 146 !   {ARM_EXT_V8,         0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
 147 !   {ARM_EXT_V8,         0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
 148
 149     /* Virtualization Extension instructions.  */
 150     {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
 151 *************** static const struct opcode32 thumb32_opc
 152 *** 1475,1494 ****
 153     /* V8 instructions.  */
 154     {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
 155     {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
 156 !   {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "strlb%c\t%12-15r, [%16-19R]"},
 157 !   {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "strlh%c\t%12-15r, [%16-19R]"},
 158 !   {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "strl%c\t%12-15r, [%16-19R]"},
 159 !   {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "strlexb%c\t%0-3r, %12-15r, [%16-19R]"},
 160 !   {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "strlexh%c\t%0-3r, %12-15r, [%16-19R]"},
 161 !   {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "strlex%c\t%0-3r, %12-15r, [%16-19R]"},
 162 !   {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "strlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
 163 !   {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
 164 !   {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldrah%c\t%12-15r, [%16-19R]"},
 165 !   {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "ldra%c\t%12-15r, [%16-19R]"},
 166 !   {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
 167 !   {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
 168 !   {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
 169 !   {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldraexd%c\t%12-15r, %8-11r, [%16-19R]"},
 170
 171     /* V7 instructions.  */
 172     {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
 173 --- 1475,1494 ----
 174     /* V8 instructions.  */
 175     {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
 176     {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
 177 !   {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
 178 !   {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
 179 !   {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
 180 !   {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
 181 !   {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
 182 !   {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
 183 !   {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
 184 !   {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
 185 !   {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
 186 !   {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
 187 !   {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
 188 !   {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
 189 !   {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
 190 !   {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
 191
 192     /* V7 instructions.  */
 193     {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
 194 diff -rcp ../binutils-2.23.51.0.3.orig/opcodes/ChangeLog ./opcodes/ChangeLog
 195 *** ../binutils-2.23.51.0.3.orig/opcodes/ChangeLog      2012-10-23 10:15:17.783874153 +0100
 196 --- ./opcodes/ChangeLog 2012-10-23 10:18:43.593915807 +0100
 197 ***************
 198 *** 1,3 ****
 199 --- 1,8 ----
 200 + 2012-09-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 201 +
 202 +       * arm-dis.c: Changed ldra and strl-form mnemonics
 203 +       to lda and stl-form.
 204 +
 205   2012-09-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 206
 207         * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
 208