3 * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 /*************************************************************************
9 * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
11 ************************************************************************/
14 * mpsc.c - driver for console over the MPSC.
20 #include <asm/cache.h>
27 #include "../include/memory.h"
29 DECLARE_GLOBAL_DATA_PTR
;
31 /* Define this if you wish to use the MPSC as a register based UART.
32 * This will force the serial port to not use the SDMA engine at all.
34 #undef CONFIG_MPSC_DEBUG_PORT
37 int (*mpsc_putchar
) (char ch
) = mpsc_putchar_early
;
38 char (*mpsc_getchar
) (void) = mpsc_getchar_debug
;
39 int (*mpsc_test_char
) (void) = mpsc_test_char_debug
;
42 static volatile unsigned int *rx_desc_base
= NULL
;
43 static unsigned int rx_desc_index
= 0;
44 static volatile unsigned int *tx_desc_base
= NULL
;
45 static unsigned int tx_desc_index
= 0;
47 /* local function declarations */
48 static int galmpsc_connect (int channel
, int connect
);
49 static int galmpsc_route_rx_clock (int channel
, int brg
);
50 static int galmpsc_route_tx_clock (int channel
, int brg
);
51 static int galmpsc_write_config_regs (int mpsc
, int mode
);
52 static int galmpsc_config_channel_regs (int mpsc
);
53 static int galmpsc_set_char_length (int mpsc
, int value
);
54 static int galmpsc_set_stop_bit_length (int mpsc
, int value
);
55 static int galmpsc_set_parity (int mpsc
, int value
);
56 static int galmpsc_enter_hunt (int mpsc
);
57 static int galmpsc_set_brkcnt (int mpsc
, int value
);
58 static int galmpsc_set_tcschar (int mpsc
, int value
);
59 static int galmpsc_set_snoop (int mpsc
, int value
);
60 static int galmpsc_shutdown (int mpsc
);
62 static int galsdma_set_RFT (int channel
);
63 static int galsdma_set_SFM (int channel
);
64 static int galsdma_set_rxle (int channel
);
65 static int galsdma_set_txle (int channel
);
66 static int galsdma_set_burstsize (int channel
, unsigned int value
);
67 static int galsdma_set_RC (int channel
, unsigned int value
);
69 static int galbrg_set_CDV (int channel
, int value
);
70 static int galbrg_enable (int channel
);
71 static int galbrg_disable (int channel
);
72 static int galbrg_set_clksrc (int channel
, int value
);
73 static int galbrg_set_CUV (int channel
, int value
);
75 static void galsdma_enable_rx (void);
76 static int galsdma_set_mem_space (unsigned int memSpace
,
77 unsigned int memSpaceTarget
,
78 unsigned int memSpaceAttr
,
79 unsigned int baseAddress
,
83 #define SOFTWARE_CACHE_MANAGEMENT
85 #ifdef SOFTWARE_CACHE_MANAGEMENT
86 #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
87 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
88 #define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
90 #define FLUSH_DCACHE(a,b)
91 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
92 #define INVALIDATE_DCACHE(a,b)
95 #ifdef CONFIG_MPSC_DEBUG_PORT
96 static void mpsc_debug_init (void)
99 volatile unsigned int temp
;
101 /* Clear the CFR (CHR4) */
102 /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
103 temp
= GTREGREAD (GALMPSC_CHANNELREG_4
+ (CHANNEL
* GALMPSC_REG_GAP
));
106 GT_REG_WRITE (GALMPSC_CHANNELREG_4
+ (CHANNEL
* GALMPSC_REG_GAP
),
109 /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
110 temp
= GTREGREAD (GALMPSC_CHANNELREG_5
+ (CHANNEL
* GALMPSC_REG_GAP
));
111 temp
|= (BIT12
| BIT15
);
112 GT_REG_WRITE (GALMPSC_CHANNELREG_5
+ (CHANNEL
* GALMPSC_REG_GAP
),
116 temp
= GTREGREAD (GALMPSC_0_INT_MASK
);
118 GT_REG_WRITE (GALMPSC_0_INT_MASK
, temp
);
122 char mpsc_getchar_debug (void)
125 volatile unsigned int cause
;
127 cause
= GTREGREAD (GALMPSC_0_INT_CAUSE
);
128 while ((cause
& BIT6
) == 0) {
129 cause
= GTREGREAD (GALMPSC_0_INT_CAUSE
);
132 temp
= GTREGREAD (GALMPSC_CHANNELREG_10
+
133 (CHANNEL
* GALMPSC_REG_GAP
));
134 /* By writing 1's to the set bits, the register is cleared */
135 GT_REG_WRITE (GALMPSC_CHANNELREG_10
+ (CHANNEL
* GALMPSC_REG_GAP
),
137 GT_REG_WRITE (GALMPSC_0_INT_CAUSE
, cause
& ~BIT6
);
138 return (temp
>> 16) & 0xff;
141 /* special function for running out of flash. doesn't modify any
142 * global variables [josh] */
143 int mpsc_putchar_early (char ch
)
147 GTREGREAD (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
));
148 galmpsc_set_tcschar (mpsc
, ch
);
149 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
),
152 #define MAGIC_FACTOR (10*1000000)
154 udelay (MAGIC_FACTOR
/ gd
->baudrate
);
158 /* This is used after relocation, see serial.c and mpsc_init2 */
159 static int mpsc_putchar_sdma (char ch
)
161 volatile unsigned int *p
;
165 /* align the descriptor */
167 memset ((void *) p
, 0, 8 * sizeof (unsigned int));
169 /* fill one 64 bit buffer */
170 /* word swap, pad with 0 */
172 p
[5] = (unsigned int) ch
; /* x */
174 /* CHANGED completely according to GT64260A dox - NTL */
175 p
[0] = 0x00010001; /* 0 */
176 p
[1] = DESC_OWNER_BIT
| DESC_FIRST
| DESC_LAST
; /* 4 */
178 p
[3] = (unsigned int) &p
[4]; /* c */
181 p
[9] = DESC_FIRST
| DESC_LAST
;
182 p
[10] = (unsigned int) &p
[0];
183 p
[11] = (unsigned int) &p
[12];
186 FLUSH_DCACHE (&p
[0], &p
[8]);
188 GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR
+ (CHANNEL
* GALSDMA_REG_DIFF
),
189 (unsigned int) &p
[0]);
190 GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR
+ (CHANNEL
* GALSDMA_REG_DIFF
),
191 (unsigned int) &p
[0]);
193 temp
= GTREGREAD (GALSDMA_0_COM_REG
+ (CHANNEL
* GALSDMA_REG_DIFF
));
194 temp
|= (TX_DEMAND
| TX_STOP
);
195 GT_REG_WRITE (GALSDMA_0_COM_REG
+ (CHANNEL
* GALSDMA_REG_DIFF
), temp
);
197 INVALIDATE_DCACHE (&p
[1], &p
[2]);
199 while (p
[1] & DESC_OWNER_BIT
) {
201 INVALIDATE_DCACHE (&p
[1], &p
[2]);
206 char mpsc_getchar_sdma (void)
208 static unsigned int done
= 0;
210 unsigned int len
= 0, idx
= 0, temp
;
212 volatile unsigned int *p
;
216 p
= &rx_desc_base
[rx_desc_index
* 8];
218 INVALIDATE_DCACHE (&p
[0], &p
[1]);
219 /* Wait for character */
220 while (p
[1] & DESC_OWNER_BIT
) {
222 INVALIDATE_DCACHE (&p
[0], &p
[1]);
225 /* Handle error case */
226 if (p
[1] & (1 << 15)) {
227 printf ("oops, error: %08x\n", p
[1]);
229 temp
= GTREGREAD (GALMPSC_CHANNELREG_2
+
230 (CHANNEL
* GALMPSC_REG_GAP
));
232 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+
233 (CHANNEL
* GALMPSC_REG_GAP
), temp
);
235 /* Can't poll on abort bit, so we just wait. */
238 galsdma_enable_rx ();
241 /* Number of bytes left in this descriptor */
254 INVALIDATE_DCACHE (&p
[idx
], &p
[idx
+ 1]);
260 /* this descriptor has more bytes still
261 * shift down the char we just read, and leave the
262 * buffer in place for the next time around
264 p
[idx
] = p
[idx
] >> 8;
265 FLUSH_DCACHE (&p
[idx
], &p
[idx
+ 1]);
269 /* nothing left in this descriptor.
272 p
[1] = DESC_OWNER_BIT
| DESC_FIRST
| DESC_LAST
;
274 FLUSH_DCACHE (&p
[0], &p
[1]);
275 /* Next descriptor */
276 rx_desc_index
= (rx_desc_index
+ 1) % RX_DESC
;
279 } while (len
== 0); /* galileo bug.. len might be zero */
285 int mpsc_test_char_debug (void)
287 if ((GTREGREAD (GALMPSC_0_INT_CAUSE
) & BIT6
) == 0)
295 int mpsc_test_char_sdma (void)
297 volatile unsigned int *p
= &rx_desc_base
[rx_desc_index
* 8];
299 INVALIDATE_DCACHE (&p
[1], &p
[2]);
301 if (p
[1] & DESC_OWNER_BIT
)
307 int mpsc_init (int baud
)
310 galbrg_set_baudrate (CHANNEL
, baud
);
311 galbrg_set_clksrc (CHANNEL
, 8); /* set source=Tclk */
312 galbrg_set_CUV (CHANNEL
, 0); /* set up CountUpValue */
313 galbrg_enable (CHANNEL
); /* Enable BRG */
315 /* Set up clock routing */
316 galmpsc_connect (CHANNEL
, GALMPSC_CONNECT
); /* connect it */
318 galmpsc_route_rx_clock (CHANNEL
, CHANNEL
); /* chosse BRG0 for Rx */
319 galmpsc_route_tx_clock (CHANNEL
, CHANNEL
); /* chose BRG0 for Tx */
321 /* reset MPSC state */
322 galmpsc_shutdown (CHANNEL
);
325 galsdma_set_burstsize (CHANNEL
, L1_CACHE_BYTES
/ 8); /* in 64 bit words (8 bytes) */
326 galsdma_set_txle (CHANNEL
);
327 galsdma_set_rxle (CHANNEL
);
328 galsdma_set_RC (CHANNEL
, 0xf);
329 galsdma_set_SFM (CHANNEL
);
330 galsdma_set_RFT (CHANNEL
);
333 galmpsc_write_config_regs (CHANNEL
, GALMPSC_UART
);
334 galmpsc_config_channel_regs (CHANNEL
);
335 galmpsc_set_char_length (CHANNEL
, GALMPSC_CHAR_LENGTH_8
); /* 8 */
336 galmpsc_set_parity (CHANNEL
, GALMPSC_PARITY_NONE
); /* N */
337 galmpsc_set_stop_bit_length (CHANNEL
, GALMPSC_STOP_BITS_1
); /* 1 */
339 #ifdef CONFIG_MPSC_DEBUG_PORT
343 /* COMM_MPSC CONFIG */
344 #ifdef SOFTWARE_CACHE_MANAGEMENT
345 galmpsc_set_snoop (CHANNEL
, 0); /* disable snoop */
347 galmpsc_set_snoop (CHANNEL
, 1); /* enable snoop */
354 void mpsc_sdma_init (void)
356 /* Setup SDMA channel0 SDMA_CONFIG_REG*/
357 GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
359 /* Enable MPSC-Window0 for DRAM Bank0 */
360 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT
,
361 MV64360_SDMA_DRAM_CS_0_TARGET
,
363 memoryGetBankBaseAddress
364 (CS_0_LOW_DECODE_ADDRESS
),
365 memoryGetBankSize (BANK0
)) != true)
366 printf ("%s: SDMA_Window0 memory setup failed !!! \n",
370 /* Disable MPSC-Window1 */
371 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT
,
372 MV64360_SDMA_DRAM_CS_0_TARGET
,
374 memoryGetBankBaseAddress
375 (CS_1_LOW_DECODE_ADDRESS
),
376 memoryGetBankSize (BANK3
)) != true)
377 printf ("%s: SDMA_Window1 memory setup failed !!! \n",
381 /* Disable MPSC-Window2 */
382 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT
,
383 MV64360_SDMA_DRAM_CS_0_TARGET
,
385 memoryGetBankBaseAddress
386 (CS_2_LOW_DECODE_ADDRESS
),
387 memoryGetBankSize (BANK3
)) != true)
388 printf ("%s: SDMA_Window2 memory setup failed !!! \n",
392 /* Disable MPSC-Window3 */
393 if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT
,
394 MV64360_SDMA_DRAM_CS_0_TARGET
,
396 memoryGetBankBaseAddress
397 (CS_3_LOW_DECODE_ADDRESS
),
398 memoryGetBankSize (BANK3
)) != true)
399 printf ("%s: SDMA_Window3 memory setup failed !!! \n",
402 /* Setup MPSC0 access mode Window0 full access */
403 GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG
,
404 (MV64360_SDMA_WIN_ACCESS_FULL
<<
405 (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT
* 2)));
407 /* Setup MPSC1 access mode Window1 full access */
408 GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG
,
409 (MV64360_SDMA_WIN_ACCESS_FULL
<<
410 (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT
* 2)));
412 /* Setup MPSC internal address space base address */
413 GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG
, CONFIG_SYS_GT_REGS
);
415 /* no high address remap*/
416 GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0
, 0x00);
417 GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1
, 0x00);
419 /* clear interrupt cause register for MPSC (fault register)*/
420 GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG
, 0x00);
424 void mpsc_init2 (void)
428 #ifndef CONFIG_MPSC_DEBUG_PORT
429 mpsc_putchar
= mpsc_putchar_sdma
;
430 mpsc_getchar
= mpsc_getchar_sdma
;
431 mpsc_test_char
= mpsc_test_char_sdma
;
434 rx_desc_base
= (unsigned int *) malloc (((RX_DESC
+ 1) * 8) *
435 sizeof (unsigned int));
437 /* align descriptors */
438 rx_desc_base
= (unsigned int *)
439 (((unsigned int) rx_desc_base
+ 32) & 0xFFFFFFF0);
443 memset ((void *) rx_desc_base
, 0,
444 (RX_DESC
* 8) * sizeof (unsigned int));
446 for (i
= 0; i
< RX_DESC
; i
++) {
447 rx_desc_base
[i
* 8 + 3] = (unsigned int) &rx_desc_base
[i
* 8 + 4]; /* Buffer */
448 rx_desc_base
[i
* 8 + 2] = (unsigned int) &rx_desc_base
[(i
+ 1) * 8]; /* Next descriptor */
449 rx_desc_base
[i
* 8 + 1] = DESC_OWNER_BIT
| DESC_FIRST
| DESC_LAST
; /* Command & control */
450 rx_desc_base
[i
* 8] = 0x00100000;
452 rx_desc_base
[(i
- 1) * 8 + 2] = (unsigned int) &rx_desc_base
[0];
454 FLUSH_DCACHE (&rx_desc_base
[0], &rx_desc_base
[RX_DESC
* 8]);
455 GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR
+ (CHANNEL
* GALSDMA_REG_DIFF
),
456 (unsigned int) &rx_desc_base
[0]);
459 tx_desc_base
= (unsigned int *) malloc (((TX_DESC
+ 1) * 8) *
460 sizeof (unsigned int));
462 /* align descriptors */
463 tx_desc_base
= (unsigned int *)
464 (((unsigned int) tx_desc_base
+ 32) & 0xFFFFFFF0);
468 memset ((void *) tx_desc_base
, 0,
469 (TX_DESC
* 8) * sizeof (unsigned int));
471 for (i
= 0; i
< TX_DESC
; i
++) {
472 tx_desc_base
[i
* 8 + 5] = (unsigned int) 0x23232323;
473 tx_desc_base
[i
* 8 + 4] = (unsigned int) 0x23232323;
474 tx_desc_base
[i
* 8 + 3] =
475 (unsigned int) &tx_desc_base
[i
* 8 + 4];
476 tx_desc_base
[i
* 8 + 2] =
477 (unsigned int) &tx_desc_base
[(i
+ 1) * 8];
478 tx_desc_base
[i
* 8 + 1] =
479 DESC_OWNER_BIT
| DESC_FIRST
| DESC_LAST
;
481 /* set sbytecnt and shadow byte cnt to 1 */
482 tx_desc_base
[i
* 8] = 0x00010001;
484 tx_desc_base
[(i
- 1) * 8 + 2] = (unsigned int) &tx_desc_base
[0];
486 FLUSH_DCACHE (&tx_desc_base
[0], &tx_desc_base
[TX_DESC
* 8]);
490 galsdma_enable_rx ();
495 int galbrg_set_baudrate (int channel
, int rate
)
499 galbrg_disable (channel
); /*ok */
503 clock
= (CONFIG_SYS_TCLK
/ (16 * rate
)) - 1;
505 clock
= (CONFIG_SYS_TCLK
/ (16 * rate
)) - 1;
508 galbrg_set_CDV (channel
, clock
); /* set timer Reg. for BRG */
510 galbrg_enable (channel
);
517 /* ------------------------------------------------------------------ */
519 /* Below are all the private functions that no one else needs */
521 static int galbrg_set_CDV (int channel
, int value
)
525 temp
= GTREGREAD (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
527 temp
|= (value
& 0x0000FFFF);
528 GT_REG_WRITE (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
533 static int galbrg_enable (int channel
)
537 temp
= GTREGREAD (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
539 GT_REG_WRITE (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
544 static int galbrg_disable (int channel
)
548 temp
= GTREGREAD (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
550 GT_REG_WRITE (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
555 static int galbrg_set_clksrc (int channel
, int value
)
559 temp
= GTREGREAD (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
560 temp
&= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */
561 temp
|= (value
<< 18);
562 GT_REG_WRITE (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
566 static int galbrg_set_CUV (int channel
, int value
)
568 /* set CountUpValue */
569 GT_REG_WRITE (GALBRG_0_BTREG
+ (channel
* GALBRG_REG_GAP
), value
);
575 static int galbrg_reset (int channel
)
579 temp
= GTREGREAD (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
));
581 GT_REG_WRITE (GALBRG_0_CONFREG
+ (channel
* GALBRG_REG_GAP
), temp
);
587 static int galsdma_set_RFT (int channel
)
591 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
593 GT_REG_WRITE (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
),
599 static int galsdma_set_SFM (int channel
)
603 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
605 GT_REG_WRITE (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
),
611 static int galsdma_set_rxle (int channel
)
615 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
617 GT_REG_WRITE (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
),
623 static int galsdma_set_txle (int channel
)
627 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
629 GT_REG_WRITE (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
),
635 static int galsdma_set_RC (int channel
, unsigned int value
)
639 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
641 temp
|= (value
<< 2);
642 GT_REG_WRITE (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
),
648 static int galsdma_set_burstsize (int channel
, unsigned int value
)
652 temp
= GTREGREAD (GALSDMA_0_CONF_REG
+ (channel
* GALSDMA_REG_DIFF
));
656 GT_REG_WRITE (GALSDMA_0_CONF_REG
+
657 (channel
* GALSDMA_REG_DIFF
),
658 (temp
| (0x3 << 12)));
662 GT_REG_WRITE (GALSDMA_0_CONF_REG
+
663 (channel
* GALSDMA_REG_DIFF
),
664 (temp
| (0x2 << 12)));
668 GT_REG_WRITE (GALSDMA_0_CONF_REG
+
669 (channel
* GALSDMA_REG_DIFF
),
670 (temp
| (0x1 << 12)));
674 GT_REG_WRITE (GALSDMA_0_CONF_REG
+
675 (channel
* GALSDMA_REG_DIFF
),
676 (temp
| (0x0 << 12)));
687 static int galmpsc_connect (int channel
, int connect
)
691 temp
= GTREGREAD (GALMPSC_ROUTING_REGISTER
);
693 if ((channel
== 0) && connect
)
695 else if ((channel
== 1) && connect
)
696 temp
&= ~(0x00000007 << 6);
697 else if ((channel
== 0) && !connect
)
700 temp
|= (0x00000007 << 6);
702 /* Just in case... */
705 GT_REG_WRITE (GALMPSC_ROUTING_REGISTER
, temp
);
710 static int galmpsc_route_rx_clock (int channel
, int brg
)
714 temp
= GTREGREAD (GALMPSC_RxC_ROUTE
);
724 GT_REG_WRITE (GALMPSC_RxC_ROUTE
, temp
);
729 static int galmpsc_route_tx_clock (int channel
, int brg
)
733 temp
= GTREGREAD (GALMPSC_TxC_ROUTE
);
743 GT_REG_WRITE (GALMPSC_TxC_ROUTE
, temp
);
748 static int galmpsc_write_config_regs (int mpsc
, int mode
)
750 if (mode
== GALMPSC_UART
) {
751 /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
752 GT_REG_WRITE (GALMPSC_MCONF_LOW
+ (mpsc
* GALMPSC_REG_GAP
),
755 /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
756 GT_REG_WRITE (GALMPSC_MCONF_HIGH
+ (mpsc
* GALMPSC_REG_GAP
),
760 /* 0000 0010 0000 0000 */
763 /* 0000 0011 1111 1000 */
770 static int galmpsc_config_channel_regs (int mpsc
)
772 GT_REG_WRITE (GALMPSC_CHANNELREG_1
+ (mpsc
* GALMPSC_REG_GAP
), 0);
773 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
), 0);
774 GT_REG_WRITE (GALMPSC_CHANNELREG_3
+ (mpsc
* GALMPSC_REG_GAP
), 1);
775 GT_REG_WRITE (GALMPSC_CHANNELREG_4
+ (mpsc
* GALMPSC_REG_GAP
), 0);
776 GT_REG_WRITE (GALMPSC_CHANNELREG_5
+ (mpsc
* GALMPSC_REG_GAP
), 0);
777 GT_REG_WRITE (GALMPSC_CHANNELREG_6
+ (mpsc
* GALMPSC_REG_GAP
), 0);
778 GT_REG_WRITE (GALMPSC_CHANNELREG_7
+ (mpsc
* GALMPSC_REG_GAP
), 0);
779 GT_REG_WRITE (GALMPSC_CHANNELREG_8
+ (mpsc
* GALMPSC_REG_GAP
), 0);
780 GT_REG_WRITE (GALMPSC_CHANNELREG_9
+ (mpsc
* GALMPSC_REG_GAP
), 0);
781 GT_REG_WRITE (GALMPSC_CHANNELREG_10
+ (mpsc
* GALMPSC_REG_GAP
), 0);
783 galmpsc_set_brkcnt (mpsc
, 0x3);
784 galmpsc_set_tcschar (mpsc
, 0xab);
789 static int galmpsc_set_brkcnt (int mpsc
, int value
)
793 temp
= GTREGREAD (GALMPSC_CHANNELREG_1
+ (mpsc
* GALMPSC_REG_GAP
));
795 temp
|= (value
<< 16);
796 GT_REG_WRITE (GALMPSC_CHANNELREG_1
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
801 static int galmpsc_set_tcschar (int mpsc
, int value
)
805 temp
= GTREGREAD (GALMPSC_CHANNELREG_1
+ (mpsc
* GALMPSC_REG_GAP
));
808 GT_REG_WRITE (GALMPSC_CHANNELREG_1
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
813 static int galmpsc_set_char_length (int mpsc
, int value
)
817 temp
= GTREGREAD (GALMPSC_PROTOCONF_REG
+ (mpsc
* GALMPSC_REG_GAP
));
819 temp
|= (value
<< 12);
820 GT_REG_WRITE (GALMPSC_PROTOCONF_REG
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
825 static int galmpsc_set_stop_bit_length (int mpsc
, int value
)
829 temp
= GTREGREAD (GALMPSC_PROTOCONF_REG
+ (mpsc
* GALMPSC_REG_GAP
));
831 temp
|= (value
<< 14);
832 GT_REG_WRITE (GALMPSC_PROTOCONF_REG
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
837 static int galmpsc_set_parity (int mpsc
, int value
)
841 temp
= GTREGREAD (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
));
844 temp
|= ((value
<< 18) | (value
<< 2));
845 temp
|= ((value
<< 17) | (value
<< 1));
850 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
855 static int galmpsc_enter_hunt (int mpsc
)
859 temp
= GTREGREAD (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
));
861 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
863 while (GTREGREAD (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
)) &
871 static int galmpsc_shutdown (int mpsc
)
875 /* cause RX abort (clears RX) */
876 temp
= GTREGREAD (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
));
877 temp
|= MPSC_RX_ABORT
| MPSC_TX_ABORT
;
878 temp
&= ~MPSC_ENTER_HUNT
;
879 GT_REG_WRITE (GALMPSC_CHANNELREG_2
+ (mpsc
* GALMPSC_REG_GAP
), temp
);
881 GT_REG_WRITE (GALSDMA_0_COM_REG
, 0);
882 GT_REG_WRITE (GALSDMA_0_COM_REG
, SDMA_TX_ABORT
| SDMA_RX_ABORT
);
884 /* shut down the MPSC */
885 GT_REG_WRITE (GALMPSC_MCONF_LOW
, 0);
886 GT_REG_WRITE (GALMPSC_MCONF_HIGH
, 0);
887 GT_REG_WRITE (GALMPSC_PROTOCONF_REG
+ (mpsc
* GALMPSC_REG_GAP
), 0);
891 /* shut down the sdma engines. */
892 /* reset config to default */
893 GT_REG_WRITE (GALSDMA_0_CONF_REG
, 0x000000fc);
897 /* clear the SDMA current and first TX and RX pointers */
898 GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR
, 0);
899 GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR
, 0);
900 GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR
, 0);
907 static void galsdma_enable_rx (void)
911 /* Enable RX processing */
912 temp
= GTREGREAD (GALSDMA_0_COM_REG
+ (CHANNEL
* GALSDMA_REG_DIFF
));
914 GT_REG_WRITE (GALSDMA_0_COM_REG
+ (CHANNEL
* GALSDMA_REG_DIFF
), temp
);
916 galmpsc_enter_hunt (CHANNEL
);
919 static int galmpsc_set_snoop (int mpsc
, int value
)
922 mpsc
? MPSC_1_ADDRESS_CONTROL_LOW
:
923 MPSC_0_ADDRESS_CONTROL_LOW
;
924 int temp
= GTREGREAD (reg
);
927 temp
|= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
929 temp
&= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
930 GT_REG_WRITE (reg
, temp
);
934 /*******************************************************************************
935 * galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
938 * the MV64360 SDMA has its own address decoding map that is de-coupled
939 * from the CPU interface address decoding windows. The SDMA channels
940 * share four address windows. Each region can be individually configured
941 * by this function by associating it to a target interface and setting
942 * base and size values.
945 * The size must be in 64Kbyte granularity.
946 * The base address must be aligned to the size.
947 * The size must be a series of 1s followed by a series of zeros
953 * true for success, false otherwise.
955 *******************************************************************************/
957 static int galsdma_set_mem_space (unsigned int memSpace
,
958 unsigned int memSpaceTarget
,
959 unsigned int memSpaceAttr
,
960 unsigned int baseAddress
, unsigned int size
)
965 GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG
,
970 /* The base address must be aligned to the size. */
971 if (baseAddress
% size
!= 0) {
974 if (size
< 0x10000) {
978 /* Align size and base to 64K */
979 baseAddress
&= 0xffff0000;
983 /* Checking that the size is a sequence of '1' followed by a
984 sequence of '0' starting from LSB to MSB. */
985 while ((temp
> 0) && (temp
& 0x1)) {
990 GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0
+ memSpace
* 8,
991 (baseAddress
| memSpaceTarget
| memSpaceAttr
));
992 GT_REG_WRITE ((MV64360_CUNIT_SIZE0
+ memSpace
* 8),
993 (size
- 1) & 0xffff0000);
994 GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG
,
997 /* An invalid size was specified */