board/RPXClassic/eccx.c

   1 /*
   2  * (C) Copyright 2002
   3  * Stäubli Faverges - <www.staubli.com>
   4  * Pierre AUBERT  p.aubert@staubli.com
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24 /* Video support for the ECCX daughter board                                 */
  25
  26
  27 #include <common.h>
  28 #include <config.h>
  29
  30 #ifdef CONFIG_VIDEO_SED13806
  31 #include <sed13806.h>
  32
  33
  34 /* Screen configurations: the initialization of the SD13806 depends on
  35    screen and on display mode. We handle only 8bpp and 16 bpp modes          */
  36
  37 /* ECCX board is supplied with a NEC NL6448BC20 screen                       */
  38 #ifdef CONFIG_NEC_NL6448BC20
  39 #define DISPLAY_WIDTH   640
  40 #define DISPLAY_HEIGHT  480
  41
  42 #ifdef CONFIG_VIDEO_SED13806_8BPP
  43 static const S1D_REGS init_regs [] =
  44 {
  45     {0x0001,0x00},   /* Miscellaneous Register */
  46     {0x01FC,0x00},   /* Display Mode Register */
  47     {0x0004,0x1b},   /* General IO Pins Configuration Register 0 */
  48     {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
  49     {0x0008,0xe5},   /* General IO Pins Control Register 0 */
  50     {0x0009,0x1f},   /* General IO Pins Control Register 1 */
  51     {0x0010,0x02},   /* Memory Clock Configuration Register */
  52     {0x0014,0x10},   /* LCD Pixel Clock Configuration Register */
  53     {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
  54     {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
  55     {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
  56     {0x0021,0x04},   /* DRAM Refresh Rate Register */
  57     {0x002A,0x00},   /* DRAM Timings Control Register 0 */
  58     {0x002B,0x01},   /* DRAM Timings Control Register 1 */
  59     {0x0020,0x80},   /* Memory Configuration Register */
  60     {0x0030,0x25},   /* Panel Type Register */
  61     {0x0031,0x00},   /* MOD Rate Register */
  62     {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
  63     {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
  64     {0x0035,0x01},   /* TFT FPLINE Start Position Register */
  65     {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
  66     {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
  67     {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
  68     {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
  69     {0x003B,0x00},   /* TFT FPFRAME Start Position Register */
  70     {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
  71     {0x0040,0x03},   /* LCD Display Mode Register */
  72     {0x0041,0x02},   /* LCD Miscellaneous Register */
  73     {0x0042,0x00},   /* LCD Display Start Address Register 0 */
  74     {0x0043,0x00},   /* LCD Display Start Address Register 1 */
  75     {0x0044,0x00},   /* LCD Display Start Address Register 2 */
  76     {0x0046,0x40},   /* LCD Memory Address Offset Register 0 */
  77     {0x0047,0x01},   /* LCD Memory Address Offset Register 1 */
  78     {0x0048,0x00},   /* LCD Pixel Panning Register */
  79     {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
  80     {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
  81     {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
  82     {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
  83     {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
  84     {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
  85     {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
  86     {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
  87     {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
  88     {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
  89     {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
  90     {0x005B,0x00},   /* TV Output Control Register */
  91     {0x0060,0x03},   /* CRT/TV Display Mode Register */
  92     {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
  93     {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
  94     {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
  95     {0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
  96     {0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
  97     {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
  98     {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
  99     {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
 100     {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
 101     {0x0071,0x00},   /* LCD Ink/Cursor Start Address Register */
 102     {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
 103     {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
 104     {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
 105     {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
 106     {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
 107     {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
 108     {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
 109     {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
 110     {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
 111     {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
 112     {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
 113     {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
 114     {0x0081,0x00},   /* CRT/TV Ink/Cursor Start Address Register */
 115     {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
 116     {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
 117     {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
 118     {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
 119     {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
 120     {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
 121     {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
 122     {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
 123     {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
 124     {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
 125     {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
 126     {0x0100,0x00},   /* BitBlt Control Register 0 */
 127     {0x0101,0x00},   /* BitBlt Control Register 1 */
 128     {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
 129     {0x0103,0x00},   /* BitBlt Operation Register */
 130     {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
 131     {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
 132     {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
 133     {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
 134     {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
 135     {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
 136     {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
 137     {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
 138     {0x0110,0x00},   /* BitBlt Width Register 0 */
 139     {0x0111,0x00},   /* BitBlt Width Register 1 */
 140     {0x0112,0x00},   /* BitBlt Height Register 0 */
 141     {0x0113,0x00},   /* BitBlt Height Register 1 */
 142     {0x0114,0x00},   /* BitBlt Background Color Register 0 */
 143     {0x0115,0x00},   /* BitBlt Background Color Register 1 */
 144     {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
 145     {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
 146     {0x01E0,0x00},   /* Look-Up Table Mode Register */
 147     {0x01E2,0x00},   /* Look-Up Table Address Register */
 148     {0x01E4,0x00},   /* Look-Up Table Data Register */
 149     {0x01F0,0x10},   /* Power Save Configuration Register */
 150     {0x01F1,0x00},   /* Power Save Status Register */
 151     {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
 152     {0x01FC,0x01},   /* Display Mode Register */
 153     {0, 0}
 154 };
 155 #endif /* CONFIG_VIDEO_SED13806_8BPP */
 156
 157 #ifdef CONFIG_VIDEO_SED13806_16BPP
 158
 159 static const S1D_REGS init_regs [] =
 160 {
 161     {0x0001,0x00},   /* Miscellaneous Register */
 162     {0x01FC,0x00},   /* Display Mode Register */
 163     {0x0004,0x1b},   /* General IO Pins Configuration Register 0 */
 164     {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
 165     {0x0008,0xe5},   /* General IO Pins Control Register 0 */
 166     {0x0009,0x1f},   /* General IO Pins Control Register 1 */
 167     {0x0010,0x02},   /* Memory Clock Configuration Register */
 168     {0x0014,0x10},   /* LCD Pixel Clock Configuration Register */
 169     {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
 170     {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
 171     {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
 172     {0x0021,0x04},   /* DRAM Refresh Rate Register */
 173     {0x002A,0x00},   /* DRAM Timings Control Register 0 */
 174     {0x002B,0x01},   /* DRAM Timings Control Register 1 */
 175     {0x0020,0x80},   /* Memory Configuration Register */
 176     {0x0030,0x25},   /* Panel Type Register */
 177     {0x0031,0x00},   /* MOD Rate Register */
 178     {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
 179     {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
 180     {0x0035,0x01},   /* TFT FPLINE Start Position Register */
 181     {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
 182     {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
 183     {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
 184     {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
 185     {0x003B,0x00},   /* TFT FPFRAME Start Position Register */
 186     {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
 187     {0x0040,0x05},   /* LCD Display Mode Register */
 188     {0x0041,0x02},   /* LCD Miscellaneous Register */
 189     {0x0042,0x00},   /* LCD Display Start Address Register 0 */
 190     {0x0043,0x00},   /* LCD Display Start Address Register 1 */
 191     {0x0044,0x00},   /* LCD Display Start Address Register 2 */
 192     {0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
 193     {0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
 194     {0x0048,0x00},   /* LCD Pixel Panning Register */
 195     {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
 196     {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
 197     {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
 198     {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
 199     {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
 200     {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
 201     {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
 202     {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
 203     {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
 204     {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
 205     {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
 206     {0x005B,0x00},   /* TV Output Control Register */
 207     {0x0060,0x05},   /* CRT/TV Display Mode Register */
 208     {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
 209     {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
 210     {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
 211     {0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
 212     {0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
 213     {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
 214     {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
 215     {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
 216     {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
 217     {0x0071,0x00},   /* LCD Ink/Cursor Start Address Register */
 218     {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
 219     {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
 220     {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
 221     {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
 222     {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
 223     {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
 224     {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
 225     {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
 226     {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
 227     {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
 228     {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
 229     {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
 230     {0x0081,0x00},   /* CRT/TV Ink/Cursor Start Address Register */
 231     {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
 232     {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
 233     {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
 234     {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
 235     {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
 236     {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
 237     {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
 238     {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
 239     {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
 240     {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
 241     {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
 242     {0x0100,0x00},   /* BitBlt Control Register 0 */
 243     {0x0101,0x00},   /* BitBlt Control Register 1 */
 244     {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
 245     {0x0103,0x00},   /* BitBlt Operation Register */
 246     {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
 247     {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
 248     {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
 249     {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
 250     {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
 251     {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
 252     {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
 253     {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
 254     {0x0110,0x00},   /* BitBlt Width Register 0 */
 255     {0x0111,0x00},   /* BitBlt Width Register 1 */
 256     {0x0112,0x00},   /* BitBlt Height Register 0 */
 257     {0x0113,0x00},   /* BitBlt Height Register 1 */
 258     {0x0114,0x00},   /* BitBlt Background Color Register 0 */
 259     {0x0115,0x00},   /* BitBlt Background Color Register 1 */
 260     {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
 261     {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
 262     {0x01E0,0x01},   /* Look-Up Table Mode Register */
 263     {0x01E2,0x00},   /* Look-Up Table Address Register */
 264     {0x01E4,0x00},   /* Look-Up Table Data Register */
 265     {0x01F0,0x10},   /* Power Save Configuration Register */
 266     {0x01F1,0x00},   /* Power Save Status Register */
 267     {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
 268     {0x01FC,0x01},   /* Display Mode Register */
 269     {0, 0}
 270 };
 271
 272 #endif /* CONFIG_VIDEO_SED13806_16BPP */
 273 #endif /* CONFIG_NEC_NL6448BC20 */
 274
 275
 276 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 277
 278 /*-----------------------------------------------------------------------------
 279  * video_get_info_str -- setup a board string: type, speed, etc.
 280  * line_number= location to place info string beside logo
 281  * info= buffer for info string
 282  *-----------------------------------------------------------------------------
 283  */
 284 void video_get_info_str (int line_number, char *info)
 285 {
 286     if (line_number == 1) {
 287         strcpy (info, " RPXClassic board");
 288     }
 289     else {
 290         info [0] = '\0';
 291     }
 292
 293 }
 294 #endif
 295
 296 /*-----------------------------------------------------------------------------
 297  * board_video_init -- init de l'EPSON, config du CS
 298  *-----------------------------------------------------------------------------
 299  */
 300 unsigned int board_video_init (void)
 301 {
 302     volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 303     volatile memctl8xx_t *memctl = &immap->im_memctl;
 304
 305     /* Program ECCX registers                                                */
 306     *(ECCX_CSR12) |= ECCX_860;
 307     *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2;
 308     *(ECCX_CSR8) |= ECCX_ENEPSON;
 309
 310     memctl->memc_or2 = SED13806_OR;
 311     memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES;
 312
 313     return (SED13806_REG_ADDR);
 314 }
 315
 316 /*-----------------------------------------------------------------------------
 317  * board_validate_screen --
 318  *-----------------------------------------------------------------------------
 319  */
 320 void board_validate_screen (unsigned int base)
 321 {
 322     /* Activate the panel bias power                                         */
 323     *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80;
 324 }
 325 /*-----------------------------------------------------------------------------
 326  * board_get_regs --
 327  *-----------------------------------------------------------------------------
 328  */
 329 const S1D_REGS *board_get_regs (void)
 330 {
 331     return (init_regs);
 332 }
 333 /*-----------------------------------------------------------------------------
 334  * board_get_width --
 335  *-----------------------------------------------------------------------------
 336  */
 337 int board_get_width (void)
 338 {
 339     return (DISPLAY_WIDTH);
 340 }
 341
 342 /*-----------------------------------------------------------------------------
 343  * board_get_height --
 344  *-----------------------------------------------------------------------------
 345  */
 346 int board_get_height (void)
 347 {
 348     return (DISPLAY_HEIGHT);
 349 }
 350
 351 #endif /* CONFIG_VIDEO_SED13806 */