2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
11 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
13 * SPDX-License-Identifier: GPL-2.0+
21 #include <linux/compiler.h>
22 #include <asm/processor.h>
26 #include "is46r16320d.h"
28 #include "mt46v16m16-75.h"
31 DECLARE_GLOBAL_DATA_PTR
;
33 #if !defined(CONFIG_SYS_RAMBOOT) && \
34 (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
35 static void sdram_start(int hi_addr
)
37 long hi_addr_bit
= hi_addr
? 0x01000000 : 0;
38 long control
= SDRAM_CONTROL
| hi_addr_bit
;
40 /* unlock mode register */
41 out_be32((void *)MPC5XXX_SDRAM_CTRL
, control
| 0x80000000);
43 /* precharge all banks */
44 out_be32((void *)MPC5XXX_SDRAM_CTRL
, control
| 0x80000002);
47 /* set mode register: extended mode */
48 out_be32((void *)MPC5XXX_SDRAM_MODE
, SDRAM_EMODE
);
50 /* set mode register: reset DLL */
51 out_be32((void *)MPC5XXX_SDRAM_MODE
, SDRAM_MODE
| 0x04000000);
54 /* precharge all banks */
55 out_be32((void *)MPC5XXX_SDRAM_CTRL
, control
| 0x80000002);
58 out_be32((void *)MPC5XXX_SDRAM_CTRL
, control
| 0x80000004);
60 /* set mode register */
61 out_be32((void *)MPC5XXX_SDRAM_MODE
, SDRAM_MODE
);
63 /* normal operation */
64 out_be32((void *)MPC5XXX_SDRAM_CTRL
, control
);
67 * Wait a short while for the DLL to lock before accessing
75 * ATTENTION: Although partially referenced dram_init does NOT make real use
76 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
77 * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
84 #if !defined(CONFIG_SYS_RAMBOOT) && \
85 (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
88 /* setup SDRAM chip selects */
89 out_be32((void *)MPC5XXX_SDRAM_CS0CFG
, 0x0000001e); /* 2GB at 0x0 */
90 out_be32((void *)MPC5XXX_SDRAM_CS1CFG
, 0x80000000); /* disabled */
92 /* setup config registers */
93 out_be32((void *)MPC5XXX_SDRAM_CONFIG1
, SDRAM_CONFIG1
);
94 out_be32((void *)MPC5XXX_SDRAM_CONFIG2
, SDRAM_CONFIG2
);
98 out_be32((void *)MPC5XXX_CDM_PORCFG
, SDRAM_TAPDELAY
);
101 /* find RAM size using SDRAM CS0 only */
103 test1
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
105 test2
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
113 /* memory smaller than 1MB is impossible */
114 if (dramsize
< (1 << 20))
117 /* set SDRAM CS0 size according to the amount of RAM found */
119 out_be32((void *)MPC5XXX_SDRAM_CS0CFG
,
120 0x13 + __builtin_ffs(dramsize
>> 20) - 1);
122 out_be32((void *)MPC5XXX_SDRAM_CS0CFG
, 0); /* disabled */
124 #else /* CONFIG_SYS_RAMBOOT */
126 /* retrieve size of memory connected to SDRAM CS0 */
127 dramsize
= in_be32((void *)MPC5XXX_SDRAM_CS0CFG
) & 0xFF;
128 if (dramsize
>= 0x13)
129 dramsize
= (1 << (dramsize
- 0x13)) << 20;
133 /* retrieve size of memory connected to SDRAM CS1 */
134 dramsize2
= in_be32((void *)MPC5XXX_SDRAM_CS1CFG
) & 0xFF;
135 if (dramsize2
>= 0x13)
136 dramsize2
= (1 << (dramsize2
- 0x13)) << 20;
140 #endif /* CONFIG_SYS_RAMBOOT */
143 * On MPC5200B we need to set the special configuration delay in the
144 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
145 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
147 * "The SDelay should be written to a value of 0x00000004. It is
148 * required to account for changes caused by normal wafer processing
153 if ((SVR_MJREV(svr
) >= 2) && (PVR_MAJ(pvr
) == 1) && (PVR_MIN(pvr
) == 4))
154 out_be32((void *)MPC5XXX_SDRAM_SDELAY
, 0x04);
156 gd
->ram_size
= dramsize
+ dramsize2
;
161 static void get_revisions(int *failsavelevel
, int *digiboardversion
,
164 struct mpc5xxx_gpt_0_7
*gpt
= (struct mpc5xxx_gpt_0_7
*)MPC5XXX_GPT
;
167 /* read digitalboard-version from TMR[2..4] */
169 val
|= (gpt
->gpt2
.sr
& (1 << (31 - 23))) ? (1) : 0;
170 val
|= (gpt
->gpt3
.sr
& (1 << (31 - 23))) ? (1 << 1) : 0;
171 val
|= (gpt
->gpt4
.sr
& (1 << (31 - 23))) ? (1 << 2) : 0;
172 *digiboardversion
= val
;
175 * A4M2K only supports digiboardversion. No failsavelevel and
178 #if !defined(CONFIG_A4M2K)
180 * Figure out failsavelevel
183 *failsavelevel
= 0; /* 0=failsave, 1=board ok, 2=fpga ok */
185 if (*digiboardversion
== 0) {
186 *failsavelevel
= 1; /* digiboard-version ok */
188 /* read fpga-version from TMR[5..7] */
190 val
|= (gpt
->gpt5
.sr
& (1 << (31 - 23))) ? (1) : 0;
191 val
|= (gpt
->gpt6
.sr
& (1 << (31 - 23))) ? (1 << 1) : 0;
192 val
|= (gpt
->gpt7
.sr
& (1 << (31 - 23))) ? (1 << 2) : 0;
195 if (*fpgaversion
== 1)
196 *failsavelevel
= 2; /* fpga-version ok */
202 * This function is called from the SPL U-Boot version for
203 * early init stuff, that needs to be done for OS (e.g. Linux)
204 * booting. Doing it later in the real U-Boot would not work
205 * in case that the SPL U-Boot boots Linux directly.
207 void spl_board_init(void)
209 struct mpc5xxx_gpio
*gpio
= (struct mpc5xxx_gpio
*)MPC5XXX_GPIO
;
210 struct mpc5xxx_mmap_ctl
*mm
=
211 (struct mpc5xxx_mmap_ctl
*)CONFIG_SYS_MBAR
;
213 #if defined(CONFIG_A4M2K)
214 /* enable CS3 and CS5 (FPGA) */
215 setbits_be32(&mm
->ipbi_ws_ctrl
, (1 << 19) | (1 << 21));
217 int digiboardversion
;
222 get_revisions(&failsavelevel
, &digiboardversion
, &fpgaversion
);
224 val
= in_be32(&mm
->ipbi_ws_ctrl
);
226 /* first clear bits 19..21 (CS3...5) */
227 val
&= ~((1 << 19) | (1 << 20) | (1 << 21));
228 if (failsavelevel
== 2) {
230 val
|= (1 << 19) | (1 << 21);
233 if (failsavelevel
>= 1) {
234 /* at least digiboard-version ok */
238 /* And write new value back to register */
239 out_be32(&mm
->ipbi_ws_ctrl
, val
);
242 /* Setup pin multiplexing */
243 if (failsavelevel
== 2) {
244 /* fpga-version ok */
245 #if defined(CONFIG_SYS_GPS_PORT_CONFIG_2)
246 out_be32(&gpio
->port_config
, CONFIG_SYS_GPS_PORT_CONFIG_2
);
248 } else if (failsavelevel
== 1) {
249 /* digiboard-version ok - fpga not */
250 #if defined(CONFIG_SYS_GPS_PORT_CONFIG_1)
251 out_be32(&gpio
->port_config
, CONFIG_SYS_GPS_PORT_CONFIG_1
);
254 /* full failsave-mode */
255 #if defined(CONFIG_SYS_GPS_PORT_CONFIG)
256 out_be32(&gpio
->port_config
, CONFIG_SYS_GPS_PORT_CONFIG
);
262 * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
265 * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
266 * set bit 0(msb) to 1
268 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE
, CONFIG_WDOG_GPIO_PIN
);
270 #if defined(CONFIG_A4M2K)
271 /* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
273 /* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
274 gpio
->simple_ddr
|= 1 << (31 - 15);
275 gpio
->simple_ddr
|= 1 << (31 - 14);
276 gpio
->simple_ddr
|= 1 << (31 - 13);
277 gpio
->simple_ddr
|= 1 << (31 - 12);
279 /* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
280 gpio
->simple_gpioe
|= 1 << (31 - 15);
281 gpio
->simple_gpioe
|= 1 << (31 - 14);
282 gpio
->simple_gpioe
|= 1 << (31 - 13);
283 gpio
->simple_gpioe
|= 1 << (31 - 12);
285 /* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
287 /* set PSC2[0..2] (STSLED[0..2]) direction to output */
288 gpio
->simple_ddr
|= 1 << (31 - 27);
289 gpio
->simple_ddr
|= 1 << (31 - 26);
290 gpio
->simple_ddr
|= 1 << (31 - 25);
292 /* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
293 gpio
->simple_gpioe
|= 1 << (31 - 27);
294 gpio
->simple_gpioe
|= 1 << (31 - 26);
295 gpio
->simple_gpioe
|= 1 << (31 - 25);
297 /* Setup PSC6[2] as MRST2 self reset GPIO output */
299 /* set PSC6[2]/IRDA_TX (MRST2) direction to output */
300 gpio
->simple_ddr
|= 1 << (31 - 3);
302 /* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
303 gpio
->simple_ode
|= 1 << (31 - 3);
305 /* set PSC6[2]/IRDA_TX (MRST2) output as default high */
306 gpio
->simple_dvo
|= 1 << (31 - 3);
308 /* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
309 gpio
->simple_gpioe
|= 1 << (31 - 3);
311 /* Setup PSC6[3] as HARNSSCD harness code GPIO input */
313 /* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
314 gpio
->simple_ddr
|= 0 << (31 - 2);
316 /* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
317 gpio
->simple_gpioe
|= 1 << (31 - 2);
319 /* setup GPIOs for status-leds if needed - see ticket #57 */
320 if (failsavelevel
> 0) {
321 /* digiboard-version is OK */
322 /* LED is LOW ACTIVE - so deactivate by set output to 1 */
323 gpio
->simple_dvo
|= 1 << (31 - 12);
324 gpio
->simple_dvo
|= 1 << (31 - 13);
325 /* set GPIO direction to output */
326 gpio
->simple_ddr
|= 1 << (31 - 12);
327 gpio
->simple_ddr
|= 1 << (31 - 13);
328 /* open drain config is set to "normal output" at reset */
329 /* gpio->simple_ode &=~ ( 1 << (31-12) ); */
330 /* gpio->simple_ode &=~ ( 1 << (31-13) ); */
332 gpio
->simple_gpioe
|= 1 << (31 - 12);
333 gpio
->simple_gpioe
|= 1 << (31 - 13);
336 /* setup fpga irq - see ticket #65 */
337 if (failsavelevel
> 1) {
339 * The main irq initialisation is done in interrupts.c
342 struct mpc5xxx_intr
*intr
=
343 (struct mpc5xxx_intr
*)(MPC5XXX_ICTL
);
345 setbits_be32(&intr
->ctrl
, 0x08C01801);
348 * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
349 * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
357 int digiboardversion
;
361 get_revisions(&failsavelevel
, &digiboardversion
, &fpgaversion
);
364 puts("Board: A4M2K\n");
365 printf(" digiboard IO version %u\n", digiboardversion
);
367 puts("Board: A3M071\n");
368 printf("Rev: failsave level %u\n", failsavelevel
);
369 printf(" digiboard IO version %u\n", digiboardversion
);
370 if (failsavelevel
> 0) /* only if fpga-version red */
371 printf(" fpga IO version %u\n", fpgaversion
);
377 /* miscellaneous platform dependent initialisations */
378 int misc_init_r(void)
380 /* adjust flash start and offset to detected values */
381 gd
->bd
->bi_flashstart
= flash_info
[0].start
[0];
382 gd
->bd
->bi_flashoffset
= 0;
385 out_be32((void *)MPC5XXX_BOOTCS_START
,
386 START_REG(gd
->bd
->bi_flashstart
));
387 out_be32((void *)MPC5XXX_CS0_START
, START_REG(gd
->bd
->bi_flashstart
));
388 out_be32((void *)MPC5XXX_BOOTCS_STOP
,
389 STOP_REG(gd
->bd
->bi_flashstart
, gd
->bd
->bi_flashsize
));
390 out_be32((void *)MPC5XXX_CS0_STOP
,
391 STOP_REG(gd
->bd
->bi_flashstart
, gd
->bd
->bi_flashsize
));
396 #ifdef CONFIG_OF_BOARD_SETUP
397 int ft_board_setup(void *blob
, bd_t
*bd
)
399 ft_cpu_setup(blob
, bd
);
403 #endif /* CONFIG_OF_BOARD_SETUP */
405 #ifdef CONFIG_SPL_OS_BOOT
407 * A3M071 specific implementation of spl_start_uboot()
410 * 0 if booting into OS is selected (default)
411 * 1 if booting into U-Boot is selected
413 int spl_start_uboot(void)
418 getenv_f("boot_os", s
, sizeof(s
));
419 if ((s
!= NULL
) && (*s
== '1' || *s
== 'y' || *s
== 'Y' ||
420 *s
== 't' || *s
== 'T'))
427 #if defined(CONFIG_HW_WATCHDOG)
428 static int watchdog_toggle
;
430 void hw_watchdog_reset(void)
435 * Check if watchdog is enabled via user command
437 if ((gd
->flags
& GD_FLG_RELOC
) && watchdog_toggle
) {
438 /* Set direction to output */
439 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR
, CONFIG_WDOG_GPIO_PIN
);
442 * Toggle watchdog output
444 val
= (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O
) &
445 CONFIG_WDOG_GPIO_PIN
);
447 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O
,
448 CONFIG_WDOG_GPIO_PIN
);
450 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O
,
451 CONFIG_WDOG_GPIO_PIN
);
456 int do_wdog_toggle(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
461 if (strncmp(argv
[1], "on", 2) == 0)
463 else if (strncmp(argv
[1], "off", 3) == 0)
470 printf("Usage: wdogtoggle %s\n", cmdtp
->usage
);
475 wdogtoggle
, CONFIG_SYS_MAXARGS
, 2, do_wdog_toggle
,
476 "toggle GPIO pin to service watchdog",
477 "[on/off] - Switch watchdog toggling via GPIO pin on/off"