2 * (C) Copyright 2007 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/bitops.h>
28 #include <asm/processor.h>
29 #include <fdt_support.h>
30 #ifdef CONFIG_MISC_INIT_R
35 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
36 CLOCK_SCCR1_LPC_EN | \
37 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
38 CLOCK_SCCR1_PSCFIFO_EN | \
39 CLOCK_SCCR1_DDR_EN | \
40 CLOCK_SCCR1_FEC_EN | \
41 CLOCK_SCCR1_PCI_EN | \
44 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
45 CLOCK_SCCR2_SPDIF_EN | \
46 CLOCK_SCCR2_DIU_EN | \
49 #define CSAW_START(start) ((start) & 0xFFFF0000)
50 #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
52 long int fixed_sdram(void);
54 int board_early_init_f (void)
56 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
60 * Initialize Local Window for the CPLD registers access (CS2 selects
63 im
->sysconf
.lpcs2aw
= CSAW_START(CONFIG_SYS_CPLD_BASE
) |
64 CSAW_STOP(CONFIG_SYS_CPLD_BASE
, CONFIG_SYS_CPLD_SIZE
);
65 im
->lpc
.cs_cfg
[2] = CONFIG_SYS_CS2_CFG
;
68 * According to MPC5121e RM, configuring local access windows should
69 * be followed by a dummy read of the config register that was
70 * modified last and an isync
72 lpcaw
= im
->sysconf
.lpcs2aw
;
73 __asm__
__volatile__ ("isync");
76 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
78 * Without this the flash identification routine fails, as it needs to issue
79 * write commands in order to establish the device ID.
82 #ifdef CONFIG_ADS5121_REV2
83 *((volatile u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08)) = 0xC1;
85 if (*((u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08)) & 0x04) {
86 *((volatile u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08)) = 0xC1;
88 /* running from Backup flash */
89 *((volatile u8
*)(CONFIG_SYS_CPLD_BASE
+ 0x08)) = 0x32;
93 * Configure Flash Speed
95 *((volatile u32
*)(CONFIG_SYS_IMMR
+ LPC_OFFSET
+ CS0_CONFIG
)) = CONFIG_SYS_CS0_CFG
;
96 if (SVR_MJREV (im
->sysconf
.spridr
) >= 2) {
97 *((volatile u32
*)(CONFIG_SYS_IMMR
+ LPC_OFFSET
+ CS_ALE_TIMING_CONFIG
)) = CONFIG_SYS_CS_ALETIMING
;
102 im
->clk
.sccr
[0] = SCCR1_CLOCKS_EN
;
103 im
->clk
.sccr
[1] = SCCR2_CLOCKS_EN
;
108 phys_size_t
initdram (int board_type
)
112 msize
= fixed_sdram ();
118 * fixed sdram init -- the board doesn't use memory modules that have serial presence
119 * detect or similar mechanism for discovery of the DRAM settings
121 long int fixed_sdram (void)
123 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
124 u32 msize
= CONFIG_SYS_DDR_SIZE
* 1024 * 1024;
125 u32 msize_log2
= __ilog2 (msize
);
128 /* Initialize IO Control */
129 im
->io_ctrl
.regs
[IOCTL_MEM
/4] = IOCTRL_MUX_DDR
;
131 /* Initialize DDR Local Window */
132 im
->sysconf
.ddrlaw
.bar
= CONFIG_SYS_DDR_BASE
& 0xFFFFF000;
133 im
->sysconf
.ddrlaw
.ar
= msize_log2
- 1;
136 * According to MPC5121e RM, configuring local access windows should
137 * be followed by a dummy read of the config register that was
138 * modified last and an isync
140 i
= im
->sysconf
.ddrlaw
.ar
;
141 __asm__
__volatile__ ("isync");
144 im
->mddrc
.ddr_sys_config
= CONFIG_SYS_MDDRC_SYS_CFG_EN
;
146 /* Initialize DDR Priority Manager */
147 im
->mddrc
.prioman_config1
= CONFIG_SYS_MDDRCGRP_PM_CFG1
;
148 im
->mddrc
.prioman_config2
= CONFIG_SYS_MDDRCGRP_PM_CFG2
;
149 im
->mddrc
.hiprio_config
= CONFIG_SYS_MDDRCGRP_HIPRIO_CFG
;
150 im
->mddrc
.lut_table0_main_upper
= CONFIG_SYS_MDDRCGRP_LUT0_MU
;
151 im
->mddrc
.lut_table0_main_lower
= CONFIG_SYS_MDDRCGRP_LUT0_ML
;
152 im
->mddrc
.lut_table1_main_upper
= CONFIG_SYS_MDDRCGRP_LUT1_MU
;
153 im
->mddrc
.lut_table1_main_lower
= CONFIG_SYS_MDDRCGRP_LUT1_ML
;
154 im
->mddrc
.lut_table2_main_upper
= CONFIG_SYS_MDDRCGRP_LUT2_MU
;
155 im
->mddrc
.lut_table2_main_lower
= CONFIG_SYS_MDDRCGRP_LUT2_ML
;
156 im
->mddrc
.lut_table3_main_upper
= CONFIG_SYS_MDDRCGRP_LUT3_MU
;
157 im
->mddrc
.lut_table3_main_lower
= CONFIG_SYS_MDDRCGRP_LUT3_ML
;
158 im
->mddrc
.lut_table4_main_upper
= CONFIG_SYS_MDDRCGRP_LUT4_MU
;
159 im
->mddrc
.lut_table4_main_lower
= CONFIG_SYS_MDDRCGRP_LUT4_ML
;
160 im
->mddrc
.lut_table0_alternate_upper
= CONFIG_SYS_MDDRCGRP_LUT0_AU
;
161 im
->mddrc
.lut_table0_alternate_lower
= CONFIG_SYS_MDDRCGRP_LUT0_AL
;
162 im
->mddrc
.lut_table1_alternate_upper
= CONFIG_SYS_MDDRCGRP_LUT1_AU
;
163 im
->mddrc
.lut_table1_alternate_lower
= CONFIG_SYS_MDDRCGRP_LUT1_AL
;
164 im
->mddrc
.lut_table2_alternate_upper
= CONFIG_SYS_MDDRCGRP_LUT2_AU
;
165 im
->mddrc
.lut_table2_alternate_lower
= CONFIG_SYS_MDDRCGRP_LUT2_AL
;
166 im
->mddrc
.lut_table3_alternate_upper
= CONFIG_SYS_MDDRCGRP_LUT3_AU
;
167 im
->mddrc
.lut_table3_alternate_lower
= CONFIG_SYS_MDDRCGRP_LUT3_AL
;
168 im
->mddrc
.lut_table4_alternate_upper
= CONFIG_SYS_MDDRCGRP_LUT4_AU
;
169 im
->mddrc
.lut_table4_alternate_lower
= CONFIG_SYS_MDDRCGRP_LUT4_AL
;
171 /* Initialize MDDRC */
172 im
->mddrc
.ddr_sys_config
= CONFIG_SYS_MDDRC_SYS_CFG
;
173 im
->mddrc
.ddr_time_config0
= CONFIG_SYS_MDDRC_TIME_CFG0
;
174 im
->mddrc
.ddr_time_config1
= CONFIG_SYS_MDDRC_TIME_CFG1
;
175 im
->mddrc
.ddr_time_config2
= CONFIG_SYS_MDDRC_TIME_CFG2
;
178 for (i
= 0; i
< 10; i
++)
179 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_NOP
;
181 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_PCHG_ALL
;
182 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_NOP
;
183 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_RFSH
;
184 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_NOP
;
185 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_RFSH
;
186 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_NOP
;
187 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_INIT_DEV_OP
;
188 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_NOP
;
189 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_EM2
;
190 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_NOP
;
191 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_PCHG_ALL
;
192 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_EM2
;
193 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_EM3
;
194 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_EN_DLL
;
195 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_INIT_DEV_OP
;
196 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_PCHG_ALL
;
197 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_RFSH
;
198 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_INIT_DEV_OP
;
199 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_OCD_DEFAULT
;
200 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_PCHG_ALL
;
201 im
->mddrc
.ddr_command
= CONFIG_SYS_MICRON_NOP
;
204 im
->mddrc
.ddr_time_config0
= CONFIG_SYS_MDDRC_TIME_CFG0_RUN
;
205 im
->mddrc
.ddr_sys_config
= CONFIG_SYS_MDDRC_SYS_CFG_RUN
;
210 int misc_init_r(void)
213 extern int ads5121_diu_init(void);
215 /* Using this for DIU init before the driver in linux takes over
216 * Enable the TFP410 Encoder (I2C address 0x38)
221 i2c_write(0x38, 0x08, 1, &tmp_val
, sizeof(tmp_val
));
222 /* Verify if enabled */
224 i2c_read(0x38, 0x08, 1, &tmp_val
, sizeof(tmp_val
));
225 debug("DVI Encoder Read: 0x%02lx\n", tmp_val
);
228 i2c_write(0x38, 0x0A, 1, &tmp_val
, sizeof(tmp_val
));
229 /* Verify if enabled */
231 i2c_read(0x38, 0x0A, 1, &tmp_val
, sizeof(tmp_val
));
232 debug("DVI Encoder Read: 0x%02lx\n", tmp_val
);
234 #ifdef CONFIG_FSL_DIU_FB
235 #if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
242 static iopin_t ioregs_init
[] = {
243 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
245 IOCTL_SPDIF_TXCLK
, 3, 0,
246 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
247 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
249 /* Set highest Slew on 9 PATA pins */
251 IOCTL_PATA_CE1
, 9, 1,
252 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
253 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
255 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
258 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
259 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
261 /* FUNC1=SPDIF_TXCLK */
264 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
265 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
267 /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
269 IOCTL_I2C1_SCL
, 2, 0,
270 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
271 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
276 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
277 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
279 /* FUNC2=DIU_HSYNC */
282 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
283 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
285 /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
288 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
289 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
293 int checkboard (void)
295 ushort brd_rev
= *(vu_short
*) (CONFIG_SYS_CPLD_BASE
+ 0x00);
296 uchar cpld_rev
= *(vu_char
*) (CONFIG_SYS_CPLD_BASE
+ 0x02);
298 printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
300 /* initialize function mux & slew rate IO inter alia on IO Pins */
303 iopin_initialize(ioregs_init
, sizeof(ioregs_init
) / sizeof(ioregs_init
[0]));
308 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
309 void ft_board_setup(void *blob
, bd_t
*bd
)
311 ft_cpu_setup(blob
, bd
);
312 fdt_fixup_memory(blob
, (u64
)bd
->bi_memstart
, (u64
)bd
->bi_memsize
);
314 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */